Total properties:
1095
Page
10
of
11
Pages:
1 2 3 4 5 6 7 8 9 10 11
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
10699021
|
Filing Dt:
|
10/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR THE DETECTION OF DAMAGED REGIONS ON DIELECTRIC FILM OR OTHER PORTIONS OF A DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2005
|
Application #:
|
10704449
|
Filing Dt:
|
11/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/20/2004
| | | | |
|
Title:
|
MULTI-LAYERED SEMICONDUCTOR STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10706120
|
Filing Dt:
|
11/12/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/03/2004
| | | | |
|
Title:
|
LOW VOLTAGE BREAKDOWN ELEMENT FOR ESD TRIGGER DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
10706467
|
Filing Dt:
|
11/12/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
|
Title:
|
REVERSE CONDUCTION PROTECTION METHOD AND APPARATUS FOR A DUAL POWER SUPPLY DRIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2005
|
Application #:
|
10716299
|
Filing Dt:
|
11/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
|
Title:
|
CONTACT FOR USE IN AN INTEGRATED CIRCUIT AND A METHOD OF MANUFACTURE THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10721126
|
Filing Dt:
|
11/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2004
| | | | |
|
Title:
|
MASK LAYER AND DUAL DAMASCENE INTERCONNECT STRUCTURE IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10723547
|
Filing Dt:
|
11/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/10/2004
| | | | |
|
Title:
|
VERTICAL REPLACEMENT-GATE JUNCTION FIELD-EFFECT TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
10746824
|
Filing Dt:
|
12/24/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/07/2005
| | | | |
|
Title:
|
ELECTRICAL DEVICES HAVING ADJUSTABLE ELECTRICAL CHARACTERISTICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10750348
|
Filing Dt:
|
12/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/19/2004
| | | | |
|
Title:
|
METHOD OF PREVENTING RESIST POISONING IN DUAL DAMASCENE STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
10762962
|
Filing Dt:
|
01/22/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
THIN FILM RESISTOR DEVICE AND A METHOD OF MANUFACTURE THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10768771
|
Filing Dt:
|
01/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
|
Title:
|
SEMICONDUCTOR RESISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
10772133
|
Filing Dt:
|
02/03/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/12/2004
| | | | |
|
Title:
|
MULTI-STEP PROCESS FOR FORMING A BARRIER FILM FOR USE IN COPPER LAYER FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10773900
|
Filing Dt:
|
02/06/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/12/2004
| | | | |
|
Title:
|
VERTICAL REPLACEMENT-GATE SILICON-ON-INSULATOR TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10776752
|
Filing Dt:
|
02/11/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/19/2004
| | | | |
|
Title:
|
INTERDIGITATED CAPACITOR AND METHOD OF MANUFACTURING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
10778454
|
Filing Dt:
|
02/13/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/18/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2005
|
Application #:
|
10799279
|
Filing Dt:
|
03/12/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/15/2005
| | | | |
|
Title:
|
CHEMICAL MECHANICAL POLISHING PAD WITH GROOVES ALTERNATING BETWEEN A LARGER GROOVE SIZE AND A SMALLER GROOVE SIZE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2008
|
Application #:
|
10801310
|
Filing Dt:
|
03/16/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
|
Title:
|
YIELD PROFILE MANIPULATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
10804980
|
Filing Dt:
|
03/18/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/09/2004
| | | | |
|
Title:
|
METHOD FOR GROWING THIN FILMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10814680
|
Filing Dt:
|
03/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/23/2004
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A DOPED LATTICE MATCHING LAYER AND A METHOD OF MANUFACTURE THEREFOR
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10814682
|
Filing Dt:
|
03/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/23/2004
| | | | |
|
Title:
|
Semiconductor device having a doped lattice matching layer and a method of manufacture therefor
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
10819253
|
Filing Dt:
|
04/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/30/2004
| | | | |
|
Title:
|
STRUCTURE AND FABRICATION METHOD FOR CAPACITORS INTEGRATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
10825342
|
Filing Dt:
|
04/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
|
Title:
|
OPTIMIZED MIRROR DESIGN FOR OPTICAL DIRECT WRITE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10838384
|
Filing Dt:
|
05/04/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/14/2004
| | | | |
|
Title:
|
Implementation of Si-Ge HBT module with CMOS process
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10842139
|
Filing Dt:
|
05/10/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A DUMMY CONDUCTIVE VIA AND A METHOD OF MANUFACTURE THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10867003
|
Filing Dt:
|
06/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
|
Title:
|
SUBSTRATE PROFILE ANALYSIS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10870834
|
Filing Dt:
|
06/17/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/02/2004
| | | | |
|
Title:
|
Process for semiconductor device fabrication in which a insulating layer is formed on a semiconductor substrate
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
10879629
|
Filing Dt:
|
06/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
|
Title:
|
METHOD TO MONITOR PAD WEAR IN CMP PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10886763
|
Filing Dt:
|
07/08/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
|
Title:
|
INTERDIGITADED CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
10889901
|
Filing Dt:
|
07/13/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/19/2006
| | | | |
|
Title:
|
DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING SI1-XGEX AS SACRIFICIAL MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10893659
|
Filing Dt:
|
07/16/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/16/2004
| | | | |
|
Title:
|
DUAL LAYER BARRIER FILM TECHNIQUES TO PREVENT RESIST POISONING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10895574
|
Filing Dt:
|
07/21/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/26/2006
| | | | |
|
Title:
|
CARRIER HEAD FOR CHEMICAL MECHANICAL POLISHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10898792
|
Filing Dt:
|
07/26/2004
|
|
Title:
|
OPERATION OF SEMICONDUCTOR DEVICES SUBJECT TO HOT CARRIER INJECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
10900642
|
Filing Dt:
|
07/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
|
Title:
|
SELF-TIMED RELIABILITY AND YIELD VEHICLE WITH GATED DATA AND CLOCK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
10903938
|
Filing Dt:
|
07/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
|
Title:
|
METAL CAPACITOR STACKED WITH A MOS CAPACITOR TO PROVIDE INCREASED CAPACITANCE DENSITY
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10909821
|
Filing Dt:
|
08/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
Semiconductor wafer chuck assembly for a semiconductor processing device
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
10915719
|
Filing Dt:
|
08/10/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/16/2006
| | | | |
|
Title:
|
INTERCONNECT DIELECTRIC TUNING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
10918981
|
Filing Dt:
|
08/16/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
INCREASED QUALITY FACTOR OF A VARACTOR IN AN INTEGRATED CIRCUIT VIA A HIGH CONDUCTIVE REGION IN A WELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10920656
|
Filing Dt:
|
08/18/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/23/2006
| | | | |
|
Title:
|
METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING AN ENHANCED SHIELDING STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
10921538
|
Filing Dt:
|
08/18/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
FAILURE ANALYSIS VEHICLE FOR YIELD ENHANCEMENT WITH SELF TEST AT SPEED BURNIN CAPABILITY FOR RELIABILITY TESTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
10925497
|
Filing Dt:
|
08/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
|
Title:
|
WAFER EDGE STRUCTURE MEASUREMENT METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10925555
|
Filing Dt:
|
08/25/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
|
Title:
|
METHODS OF DOWNSTREAM MICROWAVE PHOTORESIST REMOVAL AND VIA CLEAN, PARTICULARLY FOLLOWING STOP-ON TIN ETCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10927985
|
Filing Dt:
|
08/26/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR IMPLEMENTING A CO-AXIAL WIRE IN A SEMICONDUCTOR CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
10929843
|
Filing Dt:
|
08/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
|
Title:
|
THREE-TERMINAL, TUNABLE ACTIVE INDUCTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
10930544
|
Filing Dt:
|
08/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
|
Title:
|
PREDICTIVE APPLICATIONS FOR DEVICES WITH THIN DIELECTRIC REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
10930590
|
Filing Dt:
|
08/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
|
Title:
|
METHOD FOR HEAT DISSIPATION ON SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
10941665
|
Filing Dt:
|
09/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
|
Title:
|
GUARD RING FOR IMPROVED MATCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
10942444
|
Filing Dt:
|
09/16/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
|
Title:
|
APPARATUS AND METHOD TO IMPROVE THE RESOLUTION OF PHOTOLITHOGRAPHY SYSTEMS BY IMPROVING THE TEMPERATURE STABILITY OF THE RETICLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10944373
|
Filing Dt:
|
09/16/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
|
Title:
|
TECHNIQUES FOR FORMING PASSIVE DEVICES DURING SEMICONDUCTOR BACK-END PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2010
|
Application #:
|
10944996
|
Filing Dt:
|
09/20/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
|
Title:
|
WAFER EDGE EXPOSE ALIGNMENT METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
10945177
|
Filing Dt:
|
09/20/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
|
Title:
|
FULLY SHIELDED CAPACITOR CELL STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10947069
|
Filing Dt:
|
09/22/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
|
Title:
|
TEST STRUCTURE AND METHOD FOR YIELD IMPROVEMENT OF DOUBLE POLY BIPOLAR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
10948897
|
Filing Dt:
|
09/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/06/2006
| | | | |
|
Title:
|
III-V POWER FIELD EFFECT TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10950839
|
Filing Dt:
|
09/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/06/2006
| | | | |
|
Title:
|
DYNAMIC EDGE BEAD REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10953292
|
Filing Dt:
|
09/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
|
Title:
|
TEST SEMICONDUCTOR DEVICE AND METHOD FOR DETERMINING JOULE HEATING EFFECTS IN SUCH A DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10953478
|
Filing Dt:
|
09/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/27/2006
| | | | |
|
Title:
|
STRUCTURE AND METHOD FOR ADJUSTING INTEGRATED CIRCUIT RESISTOR VALUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
10953585
|
Filing Dt:
|
09/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
|
Title:
|
SEMICONDUCTOR TESTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10953632
|
Filing Dt:
|
09/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
|
Title:
|
TRENCH ISOLATION STRUCTURE AND METHOD OF MANUFACTURE THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10953894
|
Filing Dt:
|
09/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
|
Title:
|
MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS AND METHOD FOR FORMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10953897
|
Filing Dt:
|
09/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
|
Title:
|
BASE CURRENT COMPENSATION CIRCUIT FOR A BIPOLAR JUNCTION TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10955168
|
Filing Dt:
|
09/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/06/2006
| | | | |
|
Title:
|
METHOD OF PREDICTING QUIESCENT CURRENT VARIATION OF AN INTEGRATED CIRCUIT DIE FROM A PROCESS MONITOR DERATING FACTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10969745
|
Filing Dt:
|
10/20/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
|
Title:
|
METHOD OF SCREENING ASIC DEFECTS USING INDEPENDENT COMPONENT ANALYSIS OF QUIESCENT CURRENT MEASUREMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10972898
|
Filing Dt:
|
10/25/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
|
Title:
|
ADJUSTABLE TRANSMISSION PHASE SHIFT MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10977732
|
Filing Dt:
|
10/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/21/2005
| | | | |
|
Title:
|
CONTROL OF HOT CARRIER INJECTION IN A METAL-OXIDE SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10980945
|
Filing Dt:
|
11/03/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
|
Title:
|
METHOD OF WAFER PATTERNING FOR REDUCING EDGE EXCLUSION ZONE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2008
|
Application #:
|
10999705
|
Filing Dt:
|
11/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/01/2006
| | | | |
|
Title:
|
DUAL-GATE METAL-OXIDE SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2009
|
Application #:
|
11007392
|
Filing Dt:
|
12/07/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
|
Title:
|
BI-AXIAL TEXTURING OF HIGH-K DIELECTRIC FILMS TO REDUCE LEAKAGE CURRENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11007694
|
Filing Dt:
|
12/07/2004
|
|
Title:
|
ELECTRO CHEMICAL MECHANICAL POLISHING METHOD AND DEVICE FOR PLANARIZING SEMICONDUCTOR SURFACES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11010970
|
Filing Dt:
|
12/12/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
|
Title:
|
APPARATUS FOR CONFINING INDUCTIVELY COUPLED SURFACE CURRENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2011
|
Application #:
|
11011896
|
Filing Dt:
|
12/14/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
|
Title:
|
MASKLESS VORTEX PHASE SHIFT OPTICAL DIRECT WRITE LITHOGRAPHY
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11014476
|
Filing Dt:
|
12/16/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
|
Title:
|
Method to use a laser to perform the edge clean operation on a semiconductor wafer
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2006
|
Application #:
|
11016468
|
Filing Dt:
|
12/16/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
|
Title:
|
DIAMOND METAL-FILLED PATTERNS ACHIEVING LOW PARASITIC COUPLING CAPACITANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
11028695
|
Filing Dt:
|
01/04/2005
|
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
|
Title:
|
FAILURE ANALYSIS AND TESTING OF SEMI-CONDUCTOR DEVICES USING INTELLIGENT SOFTWARE ON AUTOMATED TEST EQUIPMENT (ATE)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
11031564
|
Filing Dt:
|
01/06/2005
|
|
Publication #:
|
|
Pub Dt:
|
07/07/2005
| | | | |
|
Title:
|
METHOD TO SELECTIVELY IDENTIFY RELIABILITY RISK DIE BASED ON CHARACTERISTICS OF LOCAL REGIONS ON THE WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2009
|
Application #:
|
11046949
|
Filing Dt:
|
01/31/2005
|
|
Title:
|
PROCESS AND APPARATUS FOR SIMULTANEOUS LIGHT AND RADICAL SURFACE TREATMENT OF INTEGRATED CIRCUIT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
11058498
|
Filing Dt:
|
02/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
07/21/2005
| | | | |
|
Title:
|
LOCAL INTERCONNECT FOR INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
11071903
|
Filing Dt:
|
03/02/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
|
Title:
|
REDUCED DRY ETCHING LAG
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
11072127
|
Filing Dt:
|
03/04/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/18/2005
| | | | |
|
Title:
|
INTEGRATED CIRCUIT PROCESS MONITORING AND METROLOGY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
11072158
|
Filing Dt:
|
03/04/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
|
Title:
|
SUPERCONDUCTOR WIRES FOR BACK END INTERCONNECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11074456
|
Filing Dt:
|
03/07/2005
|
|
Title:
|
FORMING COPPER INTERCONNECTS WITH SN COATINGS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
11075195
|
Filing Dt:
|
03/07/2005
|
|
Title:
|
OPTICAL ERROR MINIMIZATION IN A SEMICONDUCTOR MANUFACTURING APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2010
|
Application #:
|
11078179
|
Filing Dt:
|
03/10/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR INCREASING YIELD FROM SEMICONDUCTOR WAFER ELECTROPLATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11078830
|
Filing Dt:
|
03/11/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
|
Title:
|
BIPOLAR TRANSISTORS HAVING CONTROLLABLE TEMPERATURE COEFFICIENT OF CURRENT GAIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2008
|
Application #:
|
11094975
|
Filing Dt:
|
03/31/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
|
Title:
|
SEMICONDUCTOR STRUCTURE FORMED USING A SACRIFICIAL STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
11098290
|
Filing Dt:
|
04/04/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
|
Title:
|
ION RECOIL IMPLANTATION AND ENHANCED CARRIER MOBILITY IN CMOS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
11104050
|
Filing Dt:
|
04/11/2005
|
|
Title:
|
SEMICONDUCTOR CHIP WITH BORDERLESS CONTACT THAT AVOIDS WELL LEAKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
11104763
|
Filing Dt:
|
04/12/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/18/2005
| | | | |
|
Title:
|
METHOD FOR CREATING BARRIERS FOR COPPER DIFFUSION
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11106307
|
Filing Dt:
|
04/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/11/2005
| | | | |
|
Title:
|
Ultra low dielectric constant thin film
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11122375
|
Filing Dt:
|
05/05/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
|
Title:
|
Capacitor with stoichiometrically adjusted dielectric and method of fabricating same
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2008
|
Application #:
|
11131003
|
Filing Dt:
|
05/16/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
|
Title:
|
DIELECTRIC BARRIER FILMS FOR USE AS COPPER BARRIER LAYERS IN SEMICONDUCTOR TRENCH AND VIA STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
11131705
|
Filing Dt:
|
05/18/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
|
Title:
|
VOLTAGE CONTRAST MONITOR FOR INTEGRATED CIRCUIT DEFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
11138152
|
Filing Dt:
|
05/26/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
|
Title:
|
METHOD OF ELECTRICAL TESTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
11153893
|
Filing Dt:
|
06/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
|
Title:
|
SHALLOW TRENCH ISOLATION STRUCTURES COMPRISING A GRADED DOPED SACRIFICIAL SILICON DIOXIDE MATERIAL AND A METHOD FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2010
|
Application #:
|
11167772
|
Filing Dt:
|
06/27/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
11184621
|
Filing Dt:
|
07/19/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
|
Title:
|
TESTING WITH HIGH SPEED PULSE GENERATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2010
|
Application #:
|
11189217
|
Filing Dt:
|
07/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
|
Title:
|
DESIGN OF SILICON-CONTROLLED RECTIFIER BY CONSIDERING ELECTROSTATIC DISCHARGE ROBUSTNESS IN HUMAN-BODY MODEL AND CHARGED-DEVICE MODEL DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
11201039
|
Filing Dt:
|
08/10/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
|
Title:
|
STRINGER ELIMINATION IN A BICMOS PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
11205382
|
Filing Dt:
|
08/17/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/22/2007
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR CLEANING SLURRY DEPOSITIONS FROM A WATER CARRIER
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11210986
|
Filing Dt:
|
08/24/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2005
| | | | |
|
Title:
|
Temperature control system
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11225310
|
Filing Dt:
|
09/12/2005
|
|
Title:
|
METHOD OF FORMING A LOW K POLYMER E-BEAM PRINTABLE MECHANICAL SUPPORT
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11230188
|
Filing Dt:
|
09/19/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
|
Title:
|
Shallow trench isolation structures and a method for forming shallow trench isolation structures
|
|
