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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10719108
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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IMPRINT-FREE CODING FOR FERROELECTRIC NONVOLATILE COUNTERS
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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10721643
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Filing Dt:
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11/24/2003
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Title:
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READING FLASH MEMORY
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Patent #:
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Issue Dt:
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11/08/2005
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Application #:
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10729732
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Filing Dt:
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12/05/2003
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Title:
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HARD MASK SPACER FOR SUBLITHOGRAPHIC BITLINE
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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10731659
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Filing Dt:
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12/09/2003
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Title:
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PROCESS FOR FABRICATION OF NITRIDE LAYER WITH REDUCED HYDROGEN CONTENT IN ONO STRUCTURE IN SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/01/2005
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Application #:
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10738301
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Filing Dt:
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12/16/2003
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Title:
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METHOD AND DEVICE FOR PROGRAMMING CELLS IN A MEMORY ARRAY IN A NARROW DISTRIBUTION
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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10758173
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Filing Dt:
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01/14/2004
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Title:
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ELECTROSTATIC DISCHARGE PERFORMANCE OF A SILICON STRUCTURE AND EFFICIENT USE OF AREA WITH ELECTROSTATIC DISCHARGE PROTECTIVE DEVICE UNDER THE PAD APPROACH AND ADJUSTMENT OF VIA CONFIGURATION THERETO TO CONTROL DRAIN JUNCTION RESISTANCE
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Patent #:
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Issue Dt:
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04/11/2006
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Application #:
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10759855
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Filing Dt:
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01/16/2004
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Title:
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FLEXIBLE CASCODE AMPLIFIER CIRCUIT WITH HIGH GAIN FOR FLASH MEMORY CELLS
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10762071
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Filing Dt:
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01/20/2004
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Title:
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METHOD FOR ERASING A MEMORY SECTOR IN VIRTUAL GROUND ARCHITECTURE WITH REDUCED LEAKAGE CURRENT
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Patent #:
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Issue Dt:
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11/27/2007
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Application #:
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10762445
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Filing Dt:
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01/22/2004
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Publication #:
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Pub Dt:
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07/28/2005
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Title:
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STRUCTURE AND METHOD FOR LOW VSS RESISTANCE AND REDUCED DIBL IN A FLOATING GATE MEMORY CELL
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Patent #:
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Issue Dt:
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01/17/2006
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Application #:
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10768188
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Filing Dt:
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02/02/2004
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Publication #:
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Pub Dt:
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11/04/2004
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Title:
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SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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10770245
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Filing Dt:
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02/02/2004
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Title:
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DISPOSABLE HARD MASK FOR MEMORY BITLINE SCALING
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10770260
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Filing Dt:
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02/02/2004
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Title:
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FLASH MEMORY CELL WITH UV PROTECTIVE LAYER
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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10770673
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Filing Dt:
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02/02/2004
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Title:
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BITLINE HARD MASK SPACER FLOW FOR MEMORY CELL SCALING
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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10785599
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Filing Dt:
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02/24/2004
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Title:
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POWER SUPPLY DETECTING INPUT RECEIVER CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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12/12/2006
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Application #:
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10803011
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Filing Dt:
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03/17/2004
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Publication #:
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Pub Dt:
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09/22/2005
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Title:
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LATCH CIRCUIT AND METHOD FOR WRITING AND READING VOLATILE AND NON-VOLATILE DATA TO AND FROM THE LATCH
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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10821312
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Filing Dt:
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04/08/2004
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Title:
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NARROW WIDE SPACER
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Patent #:
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Issue Dt:
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12/15/2009
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Application #:
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10823970
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Filing Dt:
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04/13/2004
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Title:
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SEMICONDUCTOR DEVICE HAVING A PAD METAL LAYER AND A LOWER METAL LAYER THAT ARE ELECTRICALLY COUPLED, WHEREAS APERTURES ARE FORMED IN THE LOWER METAL LAYER BELOW A CENTER AREA OF THE PAD METAL LAYER
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Patent #:
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Issue Dt:
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06/05/2007
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Application #:
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10827785
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Filing Dt:
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04/19/2004
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Title:
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CURRENT SOURCE ARCHITECTURE FOR MEMORY DEVICE STANDBY CURRENT REDUCTION
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10835341
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Filing Dt:
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04/28/2004
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Title:
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METHOD FOR PROVIDING SHORT CHANNEL EFFECT CONTROL USING A SILICIDE VSS LINE
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Patent #:
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Issue Dt:
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10/16/2007
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Application #:
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10838962
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Filing Dt:
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05/04/2004
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Title:
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METHOD FOR MINIMIZING FALSE DETECTION OF STATES IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10839561
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Filing Dt:
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05/04/2004
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Title:
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METHOD AND APPARATUS FOR ELIMINATING WORD LINE BENDING BY SOURCE SIDE IMPLANTATION
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Patent #:
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Issue Dt:
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11/28/2006
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Application #:
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10839562
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Filing Dt:
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05/04/2004
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Title:
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POSITIVE GATE STRESS DURING ERASE TO IMPROVE RETENTION IN MULTI-LEVEL, NON-VOLATILE FLASH MEMORY
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Patent #:
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Issue Dt:
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01/09/2007
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Application #:
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10839614
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Filing Dt:
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05/05/2004
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Publication #:
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Pub Dt:
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11/10/2005
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Title:
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METHODS AND APPARATUS FOR WORDLINE PROTECTION IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10843289
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Filing Dt:
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05/11/2004
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Publication #:
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Pub Dt:
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11/17/2005
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Title:
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BITLINE IMPLANT UTILIZING DUAL POLY
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10844116
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Filing Dt:
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05/12/2004
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Title:
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CASCODE AMPLIFIER CIRCUIT FOR GENERATING AND MAINTAINING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
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Patent #:
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Issue Dt:
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03/07/2006
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Application #:
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10860450
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Filing Dt:
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06/03/2004
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Title:
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METHOD OF DETERMINING VOLTAGE COMPENSATION FOR FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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06/05/2007
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Application #:
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10861575
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Filing Dt:
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06/04/2004
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Title:
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METHOD AND SYSTEM FOR IMPROVING THE TOPOGRAPHY OF A MEMORY ARRAY
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Patent #:
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Issue Dt:
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11/25/2014
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Application #:
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10861581
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Filing Dt:
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06/04/2004
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Title:
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Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10862636
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Filing Dt:
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06/07/2004
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Title:
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LDC IMPLANT FOR MIRRORBIT TO IMPROVE VT ROLL-OFF AND FORM SHARPER JUNCTION
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Patent #:
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Issue Dt:
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08/29/2006
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Application #:
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10869286
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Filing Dt:
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06/16/2004
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Title:
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ALIGNMENT MARKS WITH SALICIDED SPACERS BETWEEN BITLINES FOR ALIGNMENT SIGNAL IMPROVEMENT
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Patent #:
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Issue Dt:
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02/07/2006
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Application #:
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10869774
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Filing Dt:
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06/16/2004
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Title:
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SEMICONDUCTOR DEVICE WITH CORE AND PERIPHERY REGIONS
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Patent #:
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Issue Dt:
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11/28/2006
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Application #:
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10871825
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Filing Dt:
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06/18/2004
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Title:
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MEMORY INTERFACE SYSTEM AND METHOD FOR REDUCING CYCLE TIME OF SEQUENTIAL READ AND WRITE ACCESSES USING SEPARATE ADDRESS AND DATA BUSES
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Patent #:
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Issue Dt:
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08/10/2010
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Application #:
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10877313
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Filing Dt:
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06/25/2004
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Publication #:
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Pub Dt:
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12/29/2005
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Title:
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MEMORY CELL ARRAY LATCHUP PREVENTION
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Patent #:
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Issue Dt:
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05/19/2009
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Application #:
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10877932
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Filing Dt:
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06/25/2004
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Title:
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CONFIGURABLE DATA PATH ARCHITECTURE AND CLOCKING SCHEME
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Patent #:
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Issue Dt:
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09/09/2008
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Application #:
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10896292
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Filing Dt:
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07/20/2004
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Title:
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APPARATUS AND METHOD FOR A MEMORY ARRAY WITH SHALLOW TRENCH ISOLATION REGIONS BETWEEN BIT LINES FOR INCREASED PROCESS MARGINS
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|
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10896299
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Filing Dt:
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07/20/2004
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Title:
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METHOD FOR PROGRAMMING DUAL BIT MEMORY DEVICES TO REDUCE COMPLEMENTARY BIT DISTURBANCE
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|
|
|
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Patent #:
|
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Issue Dt:
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05/09/2006
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Application #:
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10909693
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Filing Dt:
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08/02/2004
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Publication #:
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Pub Dt:
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02/02/2006
| | | | |
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Title:
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FLASH MEMORY UNIT AND METHOD OF PROGRAMMING A FLASH MEMORY DEVICE
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|
|
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Patent #:
|
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Issue Dt:
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03/24/2009
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Application #:
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10916167
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Filing Dt:
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08/11/2004
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Publication #:
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Pub Dt:
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02/16/2006
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Title:
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METHOD OF FORMING NARROWLY SPACED FLASH MEMORY CONTACT OPENINGS AND LITHOGRAPHY MASKS
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|
|
|
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Patent #:
|
|
Issue Dt:
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01/02/2007
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Application #:
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10917562
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Filing Dt:
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08/13/2004
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Title:
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USING THIN UNDOPED TEOS WITH BPTEOS ILD OR BPTEOS ILD ALONE TO IMPROVE CHARGE LOSS AND CONTACT RESISTANCE IN MULTI BIT MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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02/09/2010
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Application #:
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10927365
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Filing Dt:
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08/26/2004
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Title:
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METHOD OF REDUCING STEP HEIGHT DIFFERENCE BETWEEN DOPED REGIONS OF FIELD OXIDE IN AN INTEGRATED CIRCUIT
|
|
|
|
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Patent #:
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Issue Dt:
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03/27/2007
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Application #:
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10927583
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Filing Dt:
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08/26/2004
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Title:
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MEMORY ARRAY WITH CURRENT LIMITING DEVICE FOR PREVENTING PARTICLE INDUCED LATCH-UP
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Patent #:
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Issue Dt:
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09/11/2007
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Application #:
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10936275
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Filing Dt:
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09/08/2004
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Title:
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METHOD FOR REDUCING SOFT ERROR RATES OF MEMORY CELLS
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10945914
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Filing Dt:
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09/22/2004
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Title:
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METHODS AND SYSTEMS FOR REDUCING ERASE TIMES IN FLASH MEMORY DEVICES
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|
|
|
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Patent #:
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Issue Dt:
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05/13/2008
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Application #:
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10950332
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Filing Dt:
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09/24/2004
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Publication #:
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Pub Dt:
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03/31/2005
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Title:
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OXIDE-NITRIDE STACK GATE DIELECTRIC
|
|
|
|
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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10968713
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Filing Dt:
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10/19/2004
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Title:
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PATTERNING FOR ELONGATED VSS CONTACT FLASH MEMORY
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|
|
|
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Patent #:
|
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Issue Dt:
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07/22/2008
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Application #:
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10976816
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Filing Dt:
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11/01/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
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Title:
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SYSTEM AND METHOD FOR PROTECTING SEMICONDUCTOR DEVICES
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|
|
|
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Patent #:
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Issue Dt:
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11/28/2006
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Application #:
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10979516
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Filing Dt:
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11/02/2004
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Title:
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METHOD OF MAKING A MEMORY CELL
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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10982296
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Filing Dt:
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11/05/2004
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Title:
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MULTI BIT PROGRAM ALGORITHM
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|
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10984065
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Filing Dt:
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11/09/2004
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Publication #:
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Pub Dt:
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05/11/2006
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Title:
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CIRCUIT FOR GENERATING A CENTERED REFERENCE VOLTAGE FOR A 1T/1C FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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11001940
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Filing Dt:
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12/01/2004
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Title:
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METHOD, SYSTEM, AND CIRCUIT FOR PERFORMING A MEMORY RELATED OPERATION
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Patent #:
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Issue Dt:
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10/17/2006
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Application #:
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11003208
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Filing Dt:
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12/02/2004
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Title:
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METHOD FOR ACHIEVING INCREASED CONTROL OVER INTERCONNECT LINE THICKNESS ACROSS A WAFER AND BETWEEN WAFERS
|
|
|
|
|
Patent #:
|
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Issue Dt:
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03/02/2010
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Application #:
|
11006034
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Filing Dt:
|
12/07/2004
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Title:
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INPUT OF TEST CONDITIONS AND OUTPUT GENERATION FOR BUILT-IN SELF TEST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
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Application #:
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11021394
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Filing Dt:
|
12/23/2004
|
|
Publication #:
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|
Pub Dt:
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06/29/2006
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Title:
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NON-VOLATILE COUNTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
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Application #:
|
11023914
|
Filing Dt:
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12/28/2004
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|
Title:
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CURRENT SENSING ARCHITECTURE FOR HIGH BITLINE VOLTAGE, RAIL TO RAIL OUTPUT SWING AND VCC NOISE CANCELLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
11024257
|
Filing Dt:
|
12/28/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
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Title:
|
SENSE AMPLIFIERS WITH HIGH VOLTAGE SWING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
11052688
|
Filing Dt:
|
02/07/2005
|
|
Publication #:
|
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Pub Dt:
|
08/10/2006
| | | | |
|
Title:
|
MEMORY ELEMENT USING ACTIVE LAYER OF BLENDED MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
11061119
|
Filing Dt:
|
02/18/2005
|
|
Publication #:
|
|
Pub Dt:
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08/25/2005
| | | | |
|
Title:
|
CURRENT-VOLTAGE CONVERTER CIRCUIT AND ITS CONTROL METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
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Application #:
|
11061307
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Filing Dt:
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02/18/2005
|
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Publication #:
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Pub Dt:
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08/25/2005
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Title:
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SEMICONDUCTOR MEMORY STORAGE DEVICE AND A REDUNDANCY CONTROL METHOD THEREFOR
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|
|
|
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Patent #:
|
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Issue Dt:
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06/13/2006
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Application #:
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11061365
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Filing Dt:
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02/18/2005
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Publication #:
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Pub Dt:
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08/25/2005
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Title:
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SEMICONDUCTOR MEMORY STORAGE DEVICE AND ITS REDUNDANT METHOD
|
|
|
|
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Patent #:
|
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Issue Dt:
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01/22/2008
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Application #:
|
11062629
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Filing Dt:
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02/23/2005
|
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Title:
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SYSTEM AND METHOD FOR GATE FORMATION IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
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Issue Dt:
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01/23/2007
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Application #:
|
11062641
|
Filing Dt:
|
02/23/2005
|
|
Title:
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SYSTEM AND METHOD FOR ERASING A MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11075999
|
Filing Dt:
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03/08/2005
|
|
Title:
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METHOD FOR CONTAINING A SILICIDED GATE WITHIN A SIDEWALL SPACER IN INTEGRATED CIRCUIT TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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10/24/2006
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Application #:
|
11076252
|
Filing Dt:
|
03/08/2005
|
|
Publication #:
|
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Pub Dt:
|
09/14/2006
| | | | |
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Title:
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DECODER FOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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11/28/2006
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Application #:
|
11082526
|
Filing Dt:
|
03/17/2005
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Publication #:
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Pub Dt:
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06/29/2006
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Title:
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COUNTING SCHEME WITH AUTOMATIC POINT-OF-REFERENCE GENERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
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Application #:
|
11087944
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Filing Dt:
|
03/23/2005
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Title:
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CURRENT SENSING CIRCUIT WITH A CURRENT-COMPENSATED DRAIN VOLTAGE REGULATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
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Application #:
|
11089708
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Filing Dt:
|
03/25/2005
|
|
Publication #:
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Pub Dt:
|
09/28/2006
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Title:
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MEMORY DEVICE WITH IMPROVED DATA RETENTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
11089732
|
Filing Dt:
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03/25/2005
|
|
Title:
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INCREASING SELF-ALIGNED CONTACT AREAS IN INTEGRATED CIRCUITS USING A DISPOSABLE SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
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Application #:
|
11090716
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Filing Dt:
|
03/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
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Title:
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SEMICONDUCTOR DEVICE AND METHOD FOR WRITING DATA INTO THE SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
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Application #:
|
11091982
|
Filing Dt:
|
03/29/2005
|
|
Title:
|
QUAD BIT USING HOT-HOLE ERASE FOR CBD CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
11099339
|
Filing Dt:
|
04/04/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
|
Title:
|
NON-CRITICAL COMPLEMENTARY MASKING METHOD FOR POLY-1 DEFINITION IN FLASH MEMORY DEVICE FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2007
|
Application #:
|
11116571
|
Filing Dt:
|
04/27/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
MULTI-CHIP MODULE AND METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2008
|
Application #:
|
11126330
|
Filing Dt:
|
05/11/2005
|
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11126739
|
Filing Dt:
|
05/11/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/08/2005
| | | | |
|
Title:
|
CARRIER FOR STACKED TYPE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
11152375
|
Filing Dt:
|
06/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/08/2007
| | | | |
|
Title:
|
JUNCTION LEAKAGE SUPPRESSION IN MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2007
|
Application #:
|
11152547
|
Filing Dt:
|
06/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2008
|
Application #:
|
11154070
|
Filing Dt:
|
06/16/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
|
Title:
|
DUAL-LEVEL STACKED FLASH MEMORY CELL WITH A MOSFET STORAGE TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
11164556
|
Filing Dt:
|
11/29/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/31/2007
| | | | |
|
Title:
|
SRAM VOLTAGE CONTROL FOR IMPROVED OPERATIONAL MARGINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
11165008
|
Filing Dt:
|
06/23/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND SOURCE VOLTAGE CONTROL METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
11165329
|
Filing Dt:
|
06/24/2005
|
|
Title:
|
MEMORY DEVICE WITH BURIED BIT LINE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
11173930
|
Filing Dt:
|
07/01/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2007
| | | | |
|
Title:
|
POWER INTERCONNECT STRUCTURE FOR BALANCED BITLINE CAPACITANCE IN A MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
11174560
|
Filing Dt:
|
07/06/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
|
Title:
|
PROGRAMMING A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
11189874
|
Filing Dt:
|
07/27/2005
|
|
Title:
|
System and method for improving reliability in a semiconductor device
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
11193391
|
Filing Dt:
|
08/01/2005
|
|
Title:
|
METHODS AND SYSTEMS FOR REDUCING THE THRESHOLD VOLTAGE DISTRIBUTION FOLLOWING A MEMORY CELL ERASE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
11195201
|
Filing Dt:
|
08/01/2005
|
|
Title:
|
SEMICONDUCTOR MEMORY WITH DATA RETENTION LINER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
11212850
|
Filing Dt:
|
08/29/2005
|
|
Title:
|
FLASH MEMORY DEVICE HAVING IMPROVED PROGRAM RATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
11215850
|
Filing Dt:
|
08/30/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
|
Title:
|
NON-VOLATILE MEMORY DEVICE, AND CONTROL METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11229527
|
Filing Dt:
|
09/20/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
|
Title:
|
HIGH PERFORMANCE FLASH MEMORY DEVICE CAPABLE OF HIGH DENSITY DATA STORAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2013
|
Application #:
|
11229529
|
Filing Dt:
|
09/20/2005
|
|
Title:
|
Flash memory programming with data dependent control of source lines
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
11234429
|
Filing Dt:
|
09/23/2005
|
|
Publication #:
|
|
Pub Dt:
|
06/01/2006
| | | | |
|
Title:
|
ONE TIME PROGRAMMABLE LATCH AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11237378
|
Filing Dt:
|
09/27/2005
|
|
Title:
|
SINGLE LATE-WRITE FOR STANDARD SYNCHRONOUS SRAMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
11242773
|
Filing Dt:
|
10/04/2005
|
|
Title:
|
RELIABLE AND SCALABLE VIRTUAL GROUND MEMORY ARRAY FORMED WITH REDUCED THERMAL CYCLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
11247328
|
Filing Dt:
|
10/12/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
11250913
|
Filing Dt:
|
10/14/2005
|
|
Title:
|
VOLTAGE SUPPLY CIRCUIT FOR MEMORY ARRAY PROGRAMMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
11259874
|
Filing Dt:
|
10/26/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
|
Title:
|
NON-VOLATILE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
11262651
|
Filing Dt:
|
10/31/2005
|
|
Title:
|
MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
11290001
|
Filing Dt:
|
11/30/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING SAID SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2010
|
Application #:
|
11291318
|
Filing Dt:
|
11/30/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE, FABRICATING METHOD THEREOF, AND PHOTOMASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11291342
|
Filing Dt:
|
11/30/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY AND METHOD OF FABRICATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
11317083
|
Filing Dt:
|
12/21/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
|
Title:
|
Fabrication method for a semiconductor device
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
11333208
|
Filing Dt:
|
01/18/2006
|
|
Title:
|
CONTROLLING THE LATCHUP EFFECT
|
|
