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Patent #:
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Issue Dt:
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06/10/2014
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Application #:
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12004969
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Filing Dt:
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12/20/2007
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Publication #:
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Pub Dt:
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01/29/2009
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Title:
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METHODS AND STRUCTURES FOR DISCHARGING PLASMA FORMED DURING THE FABRICATION OF SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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08/26/2014
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Application #:
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12006228
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Filing Dt:
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12/31/2007
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Publication #:
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Pub Dt:
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09/25/2008
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Title:
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CURRENT CONTROLLED RECALL SCHEMA
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Patent #:
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Issue Dt:
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03/09/2010
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Application #:
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12006744
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Filing Dt:
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01/04/2008
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Publication #:
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Pub Dt:
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07/09/2009
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Title:
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TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS
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Patent #:
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Issue Dt:
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12/07/2010
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Application #:
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12012388
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Filing Dt:
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02/01/2008
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Publication #:
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Pub Dt:
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02/12/2009
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Title:
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FLIP-CHIP PACKAGE COVERED WITH TAPE
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Patent #:
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Issue Dt:
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04/26/2011
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Application #:
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12012390
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Filing Dt:
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02/01/2008
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Publication #:
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Pub Dt:
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02/19/2009
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Title:
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PROGRAM AND ERASE DISABLING CONTROL OF WPCAM BY DOUBLE CONTROLS
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Patent #:
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Issue Dt:
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10/20/2009
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Application #:
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12017693
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Filing Dt:
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01/22/2008
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Publication #:
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Pub Dt:
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05/22/2008
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Title:
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MEMORY WITH A CORE-BASED VIRTUAL GROUND AND DYNAMIC REFERENCE SENSING SCHEME
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Patent #:
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Issue Dt:
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10/05/2010
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Application #:
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12026417
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Filing Dt:
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02/05/2008
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Publication #:
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Pub Dt:
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08/14/2008
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Title:
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SEMICONDUCTOR DEVICE AND METHOD FOR ADJUSTING REFERENCE LEVELS OF REFERENCE CELLS
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Patent #:
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Issue Dt:
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07/26/2011
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Application #:
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12030485
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Filing Dt:
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02/13/2008
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Publication #:
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Pub Dt:
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08/13/2009
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Title:
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MEMORY DEVICE AND METHOD THEREOF
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Patent #:
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Issue Dt:
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08/23/2011
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Application #:
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12031458
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Filing Dt:
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02/14/2008
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Publication #:
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Pub Dt:
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08/20/2009
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Title:
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METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING FEATURES WITHIN A MASK AND A SELECTIVE REMOVAL PROCESS
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Patent #:
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Issue Dt:
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05/24/2011
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Application #:
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12034316
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Filing Dt:
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02/20/2008
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Publication #:
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Pub Dt:
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08/20/2009
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Title:
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DECODING SYSTEM CAPABLE OF CHARGING PROTECTION FOR FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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01/22/2013
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Application #:
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12048474
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Filing Dt:
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03/14/2008
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Publication #:
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Pub Dt:
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09/17/2009
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Title:
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USING LPDDR1 BUS AS TRANSPORT LAYER TO COMMUNICATE TO FLASH
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Patent #:
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Issue Dt:
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10/12/2010
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Application #:
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12048549
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Filing Dt:
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03/14/2008
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Publication #:
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Pub Dt:
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07/03/2008
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Title:
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METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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08/31/2010
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Application #:
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12057203
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Filing Dt:
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03/27/2008
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Publication #:
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Pub Dt:
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10/01/2009
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Title:
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BITLINE VOLTAGE DRIVER
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Patent #:
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Issue Dt:
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12/28/2010
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Application #:
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12058471
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Filing Dt:
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03/28/2008
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Publication #:
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Pub Dt:
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10/09/2008
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Title:
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NON-VOLATILE MEMORY DEVICE, NON-VOLATILE MEMORY SYSTEM AND CONTROL METHOD FOR THE NON-VOLATILE MEMORY DEVICE IN WHICH DRIVING ABILITY OF A SELECTOR TRANSISTOR IS VARIED
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Patent #:
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Issue Dt:
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06/04/2013
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Application #:
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12059816
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Filing Dt:
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03/31/2008
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Publication #:
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Pub Dt:
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10/01/2009
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Title:
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FLASH MEMORY AND OPERATING SYSTEM KERNEL
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Patent #:
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Issue Dt:
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12/28/2010
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Application #:
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12079802
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Filing Dt:
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03/28/2008
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Title:
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NON-VOLATILE MEMORY AND METHOD OF OPERATING THE SAME
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Patent #:
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Issue Dt:
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07/29/2014
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Application #:
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12082988
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Filing Dt:
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04/16/2008
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Publication #:
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Pub Dt:
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10/22/2009
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Title:
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METHOD OF IMPROVING ADHESION OF DIELECTRIC CAP TO COPPER
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Patent #:
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Issue Dt:
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05/06/2014
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Application #:
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12108256
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Filing Dt:
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04/23/2008
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Publication #:
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Pub Dt:
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08/28/2008
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Title:
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SEMICONDUCTOR MEMORY DEVICE HAVING NON-VOLATILE MEMORY CIRCUITS IN SINGLE CHIP
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Patent #:
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Issue Dt:
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05/10/2011
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Application #:
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12109239
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Filing Dt:
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04/24/2008
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Publication #:
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Pub Dt:
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12/25/2008
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Title:
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NONVOLATILE STORAGE DEVICE AND BIAS CONTROL METHOD THEREOF
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Patent #:
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Issue Dt:
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09/28/2010
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Application #:
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12114966
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Filing Dt:
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05/05/2008
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Publication #:
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Pub Dt:
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11/05/2009
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Title:
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BITCELL CURRENT SENSE DEVICE AND METHOD THEREOF
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Patent #:
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Issue Dt:
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06/01/2010
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Application #:
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12126686
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Filing Dt:
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05/23/2008
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Publication #:
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Pub Dt:
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05/21/2009
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Title:
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MULTIPLE PROGRAMMING OF SPARE MEMORY REGION FOR NONVOLATILE MEMORY
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Patent #:
|
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Issue Dt:
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06/11/2013
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Application #:
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12127919
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Filing Dt:
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05/28/2008
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Publication #:
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Pub Dt:
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12/03/2009
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Title:
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ADDRESS CACHING STORED TRANSLATION
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|
|
|
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Patent #:
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Issue Dt:
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08/31/2010
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Application #:
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12130583
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Filing Dt:
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05/30/2008
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Publication #:
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Pub Dt:
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01/08/2009
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Title:
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SEMICONDUCTOR DEVICE AND CONTROLLING METHOD FOR THE SAME
|
|
|
|
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Patent #:
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Issue Dt:
|
03/08/2016
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Application #:
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12133689
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Filing Dt:
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06/05/2008
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Publication #:
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Pub Dt:
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07/09/2009
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Title:
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ULTRAVIOLET BLOCKING STRUCTURE AND METHOD FOR SEMICONDUCTOR DEVICE
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|
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Patent #:
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Issue Dt:
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07/19/2011
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Application #:
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12134905
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Filing Dt:
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06/06/2008
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Publication #:
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Pub Dt:
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12/10/2009
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Title:
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SENSE AMPLIFIER WITH CAPACITANCE-COUPLED DIFFERENTIAL SENSE AMPLIFIER
|
|
|
|
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Patent #:
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Issue Dt:
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09/07/2010
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Application #:
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12166288
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Filing Dt:
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07/01/2008
|
|
Publication #:
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Pub Dt:
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01/08/2009
| | | | |
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING A SEMICONDUCTOR DEVICE
|
|
|
|
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Patent #:
|
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Issue Dt:
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12/07/2010
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Application #:
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12166293
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Filing Dt:
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07/01/2008
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Publication #:
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Pub Dt:
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11/06/2008
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Title:
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CARRIER FOR STACKED TYPE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING STACKED TYPE SEMICONDUCTOR DEVICES
|
|
|
|
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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12176997
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Filing Dt:
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07/21/2008
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Publication #:
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Pub Dt:
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08/20/2009
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Title:
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SYNCHRONOUS MEMORY DEVICES AND CONTROL METHODS FOR PERFORMING BURST WRITE OPERATIONS
|
|
|
|
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Patent #:
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Issue Dt:
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10/05/2010
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Application #:
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12177039
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Filing Dt:
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07/21/2008
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|
Publication #:
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Pub Dt:
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02/05/2009
| | | | |
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Title:
|
NONVOLATILE MEMORY DEVICE HAVING A PLURALITY OF MEMORY BLOCKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
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Application #:
|
12180306
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Filing Dt:
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07/25/2008
|
|
Publication #:
|
|
Pub Dt:
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07/23/2009
| | | | |
|
Title:
|
LATERAL CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR WORDLINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2011
|
Application #:
|
12183756
|
Filing Dt:
|
07/31/2008
|
|
Publication #:
|
|
Pub Dt:
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02/05/2009
| | | | |
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Title:
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SELF-ALIGNED CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
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Application #:
|
12187276
|
Filing Dt:
|
08/06/2008
|
|
Publication #:
|
|
Pub Dt:
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02/19/2009
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR A MEMORY ARRAY WITH SHALLOW TRENCH ISOLATION REGIONS BETWEEN BIT LINES FOR INCREASED PROCESS MARGINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
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Application #:
|
12189746
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Filing Dt:
|
08/11/2008
|
|
Publication #:
|
|
Pub Dt:
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02/11/2010
| | | | |
|
Title:
|
MULTI-LEVEL STORAGE ALGORITHM TO EMPHASIZE DISTURB CONDITIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
12195307
|
Filing Dt:
|
08/20/2008
|
|
Publication #:
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|
Pub Dt:
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02/26/2009
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Title:
|
PLASMA TREATED METAL SILICIDE LAYER FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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10/12/2010
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Application #:
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12199684
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Filing Dt:
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08/27/2008
|
|
Publication #:
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|
Pub Dt:
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12/25/2008
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
12228691
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Filing Dt:
|
08/15/2008
|
|
Publication #:
|
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Pub Dt:
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02/18/2010
| | | | |
|
Title:
|
METHOD OF MEASURING FLASH MEMORY CELL CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2016
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Application #:
|
12231369
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Filing Dt:
|
09/02/2008
|
|
Publication #:
|
|
Pub Dt:
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03/04/2010
| | | | |
|
Title:
|
Method for achieving very small feature size in semiconductor device by undertaking silicide sidewall growth and etching
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2012
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Application #:
|
12234337
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Filing Dt:
|
09/19/2008
|
|
Publication #:
|
|
Pub Dt:
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09/24/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING A PRESSURE-CONTACT SECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2011
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Application #:
|
12234733
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Filing Dt:
|
09/22/2008
|
|
Publication #:
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Pub Dt:
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03/25/2010
| | | | |
|
Title:
|
HIGH VT STATE USED AS ERASE CONDITION IN TRAP BASED NOR FLASH CELL DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2010
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Application #:
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12234734
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Filing Dt:
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09/22/2008
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|
Publication #:
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|
Pub Dt:
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03/25/2010
| | | | |
|
Title:
|
EEPROM EMULATION IN FLASH DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
12234736
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Filing Dt:
|
09/22/2008
|
|
Publication #:
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|
Pub Dt:
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03/25/2010
| | | | |
|
Title:
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DYNAMIC ERASE STATE IN FLASH DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12234737
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Filing Dt:
|
09/22/2008
|
|
Publication #:
|
|
Pub Dt:
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03/25/2010
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|
Title:
|
FLASH MIRROR BIT ARCHITECTURE USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
12234738
|
Filing Dt:
|
09/22/2008
|
|
Publication #:
|
|
Pub Dt:
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03/25/2010
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|
Title:
|
SECTOR CONFIGURE REGISTERS FOR A FLASH DEVICE GENERATING MULTIPLE VIRTUAL GROUND DECODING SCHEMES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12234740
|
Filing Dt:
|
09/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2010
| | | | |
|
Title:
|
QUAD+BIT STORAGE IN TRAP BASED FLASH DESIGN USING SINGLE PROGRAM AND ERASE ENTITY AS LOGICAL CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
12249261
|
Filing Dt:
|
10/10/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR MULTI-LAYER GLOBAL BITLINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
12255622
|
Filing Dt:
|
10/21/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/22/2010
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR GENERATING WIDE-RANGE REGULATED SUPPLY VOLTAGES FOR A FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
12258067
|
Filing Dt:
|
10/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/29/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2012
|
Application #:
|
12262123
|
Filing Dt:
|
10/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/06/2010
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR PLACEMENT OF BOOSTING CELL WITH ADAPTIVE BOOSTER SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12266512
|
Filing Dt:
|
11/06/2008
|
|
Publication #:
|
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Pub Dt:
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05/06/2010
| | | | |
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Title:
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FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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05/10/2016
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Application #:
|
12273289
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Filing Dt:
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11/18/2008
|
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Publication #:
|
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Pub Dt:
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05/20/2010
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Title:
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ELECTROPLATING APPARATUS AND METHOD WITH UNIFORMITY IMPROVEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
12276604
|
Filing Dt:
|
11/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2010
| | | | |
|
Title:
|
MULTI-PHASE PROGRAMMING OF MULTI-LEVEL MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
12284002
|
Filing Dt:
|
09/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/18/2010
| | | | |
|
Title:
|
ELECTRICALLY PROGRAMMABLE AND ERASABLE MEMORY DEVICE AND METHOD OF FABRICATION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
12313134
|
Filing Dt:
|
11/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/20/2010
| | | | |
|
Title:
|
HIGH ULTRAVIOLET LIGHT ABSORBANCE SILICON OXYNITRIDE FILM FOR IMPROVED FLASH MEMORY DEVICE PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
12316041
|
Filing Dt:
|
12/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
|
Title:
|
DIE OFFSET DIE TO BONDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
12316042
|
Filing Dt:
|
12/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
|
Title:
|
DIE OFFSET DIE TO DIE BONDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2011
|
Application #:
|
12329475
|
Filing Dt:
|
12/05/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/10/2010
| | | | |
|
Title:
|
MEMORY EMPLOYING REDUNDANT CELL ARRAY OF MULTI-BIT CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
12330928
|
Filing Dt:
|
12/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/10/2010
| | | | |
|
Title:
|
DETERMINISTIC-BASED PROGRAMMING IN MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
12334221
|
Filing Dt:
|
12/12/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/18/2009
| | | | |
|
Title:
|
ELECTRONIC CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
12337396
|
Filing Dt:
|
12/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
STACKED SEMICONDUCTOR DEVICES AND A METHOD FOR FABRICATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
12340288
|
Filing Dt:
|
12/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
|
Title:
|
RADIATION DETECTING ELECTRONIC DEVICE AND METHODS OF OPERATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12341886
|
Filing Dt:
|
12/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
12342008
|
Filing Dt:
|
12/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
|
Title:
|
HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12342011
|
Filing Dt:
|
12/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
|
Title:
|
HTO OFFSET SPACERS AND DIP OFF PROCESS TO DEFINE JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
12342016
|
Filing Dt:
|
12/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
|
Title:
|
HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2011
|
Application #:
|
12346699
|
Filing Dt:
|
12/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR PERFORMING SEMICONDUCTOR MEMORY OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
|
Application #:
|
12366519
|
Filing Dt:
|
02/05/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2010
| | | | |
|
Title:
|
FRACTURED ERASE SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2012
|
Application #:
|
12368835
|
Filing Dt:
|
02/10/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/12/2010
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR LOCATING ERROR BITS IN ENCODED DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2015
|
Application #:
|
12390550
|
Filing Dt:
|
02/23/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2010
| | | | |
|
Title:
|
ADJACENT WORDLINE DISTURB REDUCTION USING BORON/INDIUM IMPLANT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2011
|
Application #:
|
12434084
|
Filing Dt:
|
05/01/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
|
Title:
|
MEMORY CELL ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12468615
|
Filing Dt:
|
05/19/2009
|
|
Publication #:
|
|
Pub Dt:
|
11/25/2010
| | | | |
|
Title:
|
RADIATION DETECTING DEVICE AND METHOD OF OPERATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12472735
|
Filing Dt:
|
05/27/2009
|
|
Publication #:
|
|
Pub Dt:
|
12/10/2009
| | | | |
|
Title:
|
IMAGING DEVICE HAVING A RADIATION DETECTING STRUCTURE DISPOSED AT A SEMICONDUCTOR SUBSTRATE WITH A THERMALIZING MATERIAL AND A FIRST RADIATION-REACTIVE MATERIAL SENSITIVE TO NEUTRON RADIATION (AS AMENDED)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
12473037
|
Filing Dt:
|
05/27/2009
|
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
|
Title:
|
IMPROVEMENT IN CHARGE RETENTION FOR FLASH MEMORY BY MANIPULATING THE PROGRAM DATA METHODOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
12494114
|
Filing Dt:
|
06/29/2009
|
|
Publication #:
|
|
Pub Dt:
|
12/30/2010
| | | | |
|
Title:
|
MEMORY EMPLOYING INDEPENDENT DYNAMIC REFERENCE AREAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12502592
|
Filing Dt:
|
07/14/2009
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
|
Title:
|
MEMORY, MEMORY OPERATING METHOD, AND MEMORY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12502891
|
Filing Dt:
|
07/14/2009
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12512638
|
Filing Dt:
|
07/30/2009
|
|
Publication #:
|
|
Pub Dt:
|
11/19/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12512741
|
Filing Dt:
|
07/30/2009
|
|
Publication #:
|
|
Pub Dt:
|
11/26/2009
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12543404
|
Filing Dt:
|
08/18/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2011
|
Application #:
|
12557721
|
Filing Dt:
|
09/11/2009
|
|
Publication #:
|
|
Pub Dt:
|
02/04/2010
| | | | |
|
Title:
|
FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
12574413
|
Filing Dt:
|
10/06/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12574427
|
Filing Dt:
|
10/06/2009
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12620172
|
Filing Dt:
|
11/17/2009
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2010
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY AND METHOD AND SYSTEM FOR ACTUATING SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
12642162
|
Filing Dt:
|
12/18/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
|
Title:
|
HIGH READ SPEED ELECTRONIC MEMORY WITH SERIAL ARRAY TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
12644457
|
Filing Dt:
|
12/22/2009
|
|
Publication #:
|
|
Pub Dt:
|
04/22/2010
| | | | |
|
Title:
|
SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
12646279
|
Filing Dt:
|
12/23/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
|
Title:
|
READ PREAMBLE FOR DATA CAPTURE OPTIMIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
12646291
|
Filing Dt:
|
12/23/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
|
Title:
|
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
12648984
|
Filing Dt:
|
12/29/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/03/2010
| | | | |
|
Title:
|
NONVOLATILE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2011
|
Application #:
|
12650118
|
Filing Dt:
|
12/30/2009
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2010
| | | | |
|
Title:
|
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
12683732
|
Filing Dt:
|
01/07/2010
|
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
|
Title:
|
MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2013
|
Application #:
|
12690590
|
Filing Dt:
|
01/20/2010
|
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
|
Title:
|
FIELD PROGRAMMABLE REDUNDANT MEMORY FOR ELECTRONIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
12691633
|
Filing Dt:
|
01/21/2010
|
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
|
Title:
|
HIGH SPEED MEMORY HAVING A PROGRAMMABLE READ PREAMBLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
12696409
|
Filing Dt:
|
01/29/2010
|
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
|
Title:
|
METHOD OF FORMING SPACED-APART CHARGE TRAPPING STACKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2016
|
Application #:
|
12701391
|
Filing Dt:
|
02/05/2010
|
|
Publication #:
|
|
Pub Dt:
|
08/11/2011
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR AUTOMATED GENERATION OF MASKS FOR SPACER FORMATION FROM A DESIRED FINAL WAFER PATTERN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12710153
|
Filing Dt:
|
02/22/2010
|
|
Publication #:
|
|
Pub Dt:
|
06/17/2010
| | | | |
|
Title:
|
TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
12720547
|
Filing Dt:
|
03/09/2010
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR MULTI-CHIP PACKAGING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12729905
|
Filing Dt:
|
03/23/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
|
Title:
|
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2012
|
Application #:
|
12770805
|
Filing Dt:
|
04/30/2010
|
|
Publication #:
|
|
Pub Dt:
|
09/02/2010
| | | | |
|
Title:
|
METHOD FOR CONTAINING A SILICIDED GATE WITHIN A SIDEWALL SPACER IN INTEGRATED CIRCUIT TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2011
|
Application #:
|
12819071
|
Filing Dt:
|
06/18/2010
|
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
12824352
|
Filing Dt:
|
06/28/2010
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
|
Title:
|
HIGH READ SPEED MEMORY WITH GATE ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2011
|
Application #:
|
12827069
|
Filing Dt:
|
06/30/2010
|
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
|
Title:
|
USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS
|
|
