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Reel/Frame:059721/0467   Pages: 54
Recorded: 04/15/2022
Attorney Dkt #:CYPRESS TO IFXLLC
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 668
Page 5 of 7
Pages: 1 2 3 4 5 6 7
1
Patent #:
Issue Dt:
03/27/2012
Application #:
12831085
Filing Dt:
07/06/2010
Publication #:
Pub Dt:
10/21/2010
Title:
ERASING FLASH MEMORY USING ADAPTIVE DRAIN AND/OR GATE BIAS
2
Patent #:
Issue Dt:
12/13/2011
Application #:
12840165
Filing Dt:
07/20/2010
Publication #:
Pub Dt:
11/11/2010
Title:
SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION
3
Patent #:
Issue Dt:
10/23/2012
Application #:
12842409
Filing Dt:
07/23/2010
Publication #:
Pub Dt:
11/11/2010
Title:
BITLINE VOLTAGE DRIVER
4
Patent #:
Issue Dt:
05/07/2013
Application #:
12844888
Filing Dt:
07/28/2010
Title:
SYSTEM AND METHOD FOR DETECTING PARTICLES WITH A SEMICONDUCTOR DEVICE
5
Patent #:
Issue Dt:
12/18/2012
Application #:
12850470
Filing Dt:
08/04/2010
Publication #:
Pub Dt:
02/10/2011
Title:
SEMICONDUCTOR MEMORY, SYSTEM, AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY
6
Patent #:
Issue Dt:
01/22/2013
Application #:
12853856
Filing Dt:
08/10/2010
Publication #:
Pub Dt:
02/16/2012
Title:
STITCH BUMP STACKING DESIGN FOR OVERALL PACKAGE SIZE REDUCTION FOR MULTIPLE STACK
7
Patent #:
Issue Dt:
10/04/2011
Application #:
12871693
Filing Dt:
08/30/2010
Publication #:
Pub Dt:
12/23/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD FOR ADJUSTING REFERENCE LEVELS OF REFERENCE CELLS
8
Patent #:
Issue Dt:
01/10/2012
Application #:
12878656
Filing Dt:
09/09/2010
Publication #:
Pub Dt:
01/06/2011
Title:
NONVOLATILE MEMORY DEVICE HAVING A PLURALITY OF MEMORY BLOCKS
9
Patent #:
Issue Dt:
08/28/2012
Application #:
12879643
Filing Dt:
09/10/2010
Publication #:
Pub Dt:
03/17/2011
Title:
SYSTEM AND METHOD TO COMPENSATE FOR PROCESS AND ENVIRONMENTAL VARIATIONS IN SEMICONDUCTOR DEVICES
10
Patent #:
Issue Dt:
03/24/2015
Application #:
12879992
Filing Dt:
09/10/2010
Publication #:
Pub Dt:
03/15/2012
Title:
Apparatus and method for read preamble disable
11
Patent #:
Issue Dt:
03/20/2012
Application #:
12880018
Filing Dt:
09/10/2010
Publication #:
Pub Dt:
03/15/2012
Title:
APPARATUS AND METHOD FOR DATA CAPTURE USING A READ PREAMBLE
12
Patent #:
Issue Dt:
05/31/2016
Application #:
12880021
Filing Dt:
09/10/2010
Publication #:
Pub Dt:
03/15/2012
Title:
APPARATUS, METHOD, AND MANUFACTURE FOR USING A READ PREAMBLE TO OPTIMIZE DATA CAPTURE
13
Patent #:
Issue Dt:
07/05/2011
Application #:
12880541
Filing Dt:
09/13/2010
Publication #:
Pub Dt:
12/30/2010
Title:
METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES
14
Patent #:
Issue Dt:
06/18/2013
Application #:
12888737
Filing Dt:
09/23/2010
Title:
NVSRAM WITH INVERTED RECALL
15
Patent #:
Issue Dt:
09/11/2012
Application #:
12901990
Filing Dt:
10/11/2010
Publication #:
Pub Dt:
07/28/2011
Title:
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
16
Patent #:
Issue Dt:
09/20/2011
Application #:
12903065
Filing Dt:
10/12/2010
Publication #:
Pub Dt:
02/03/2011
Title:
METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SEMICONDUCTOR DEVICE
17
Patent #:
Issue Dt:
03/06/2012
Application #:
12905716
Filing Dt:
10/15/2010
Publication #:
Pub Dt:
02/10/2011
Title:
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
18
Patent #:
Issue Dt:
10/09/2012
Application #:
12970675
Filing Dt:
12/16/2010
Publication #:
Pub Dt:
06/02/2011
Title:
LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
19
Patent #:
Issue Dt:
11/20/2012
Application #:
12970687
Filing Dt:
12/16/2010
Publication #:
Pub Dt:
04/14/2011
Title:
LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
20
Patent #:
Issue Dt:
09/10/2013
Application #:
12974754
Filing Dt:
12/21/2010
Publication #:
Pub Dt:
03/22/2012
Title:
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR
21
Patent #:
Issue Dt:
10/18/2011
Application #:
12980716
Filing Dt:
12/29/2010
Publication #:
Pub Dt:
04/28/2011
Title:
SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS
22
Patent #:
Issue Dt:
10/04/2011
Application #:
12987466
Filing Dt:
01/10/2011
Publication #:
Pub Dt:
05/05/2011
Title:
TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY
23
Patent #:
Issue Dt:
01/01/2013
Application #:
13011706
Filing Dt:
01/21/2011
Publication #:
Pub Dt:
07/26/2012
Title:
SYSTEM AND METHOD FOR ADDRESSING THRESHOLD VOLTAGE SHIFTS OF MEMORY CELLS IN AN ELECTRONIC PRODUCT
24
Patent #:
Issue Dt:
05/06/2014
Application #:
13012664
Filing Dt:
01/24/2011
Publication #:
Pub Dt:
05/19/2011
Title:
SEMICONDUCTOR DEVICE, METHOD OF CONTROLLING THE SAME, AND METHOD OF MANUFACTURING THE SAME
25
Patent #:
Issue Dt:
02/26/2013
Application #:
13020636
Filing Dt:
02/03/2011
Publication #:
Pub Dt:
10/20/2011
Title:
SEMICONDUCTOR MEMORY
26
Patent #:
Issue Dt:
08/20/2013
Application #:
13022410
Filing Dt:
02/07/2011
Publication #:
Pub Dt:
08/25/2011
Title:
SEMICONDUCTOR MEMORY INCLUDING PROGRAM CIRCUIT OF NONVOLATILE MEMORY CELLS AND SYSTEM
27
Patent #:
Issue Dt:
06/25/2013
Application #:
13037157
Filing Dt:
02/28/2011
Title:
SYSTEM AND METHOD FOR DE-LATCH OF AN INTEGRATED CIRCUIT
28
Patent #:
Issue Dt:
10/21/2014
Application #:
13039839
Filing Dt:
03/03/2011
Publication #:
Pub Dt:
09/29/2011
Title:
DATA-PROCESSING METHOD, PROGRAM, AND SYSTEM
29
Patent #:
Issue Dt:
07/10/2012
Application #:
13052486
Filing Dt:
03/21/2011
Publication #:
Pub Dt:
07/14/2011
Title:
SEMICONDUCTOR DEVICE WITH DOUBLE PROGRAM PROHIBITION CONTROL
30
Patent #:
Issue Dt:
12/11/2012
Application #:
13069710
Filing Dt:
03/23/2011
Publication #:
Pub Dt:
07/14/2011
Title:
HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVICE PERFORMANCE
31
Patent #:
Issue Dt:
01/21/2014
Application #:
13070186
Filing Dt:
03/23/2011
Publication #:
Pub Dt:
10/20/2011
Title:
DATA WRITING METHOD AND SYSTEM
32
Patent #:
Issue Dt:
09/17/2013
Application #:
13074836
Filing Dt:
03/29/2011
Publication #:
Pub Dt:
07/21/2011
Title:
JUNCTION LEAKAGE SUPPRESSION IN MEMORY DEVICES
33
Patent #:
Issue Dt:
11/27/2012
Application #:
13094744
Filing Dt:
04/26/2011
Publication #:
Pub Dt:
08/18/2011
Title:
SELF-ALIGNED CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR DEVICE
34
Patent #:
Issue Dt:
07/30/2013
Application #:
13098364
Filing Dt:
04/29/2011
Publication #:
Pub Dt:
11/01/2012
Title:
METHOD, APPARATUS, AND MANUFACTURE FOR FLASH MEMORY WRITE ALGORITHM FOR FAST BITS
35
Patent #:
Issue Dt:
09/24/2013
Application #:
13098378
Filing Dt:
04/29/2011
Publication #:
Pub Dt:
11/01/2012
Title:
METHOD AND APPARATUS FOR TEMPERATURE COMPENSATION FOR PROGRAMMING AND ERASE DISTRIBUTIONS IN A FLASH MEMORY
36
Patent #:
Issue Dt:
01/28/2014
Application #:
13098389
Filing Dt:
04/29/2011
Publication #:
Pub Dt:
11/01/2012
Title:
APPARATUS AND METHOD FOR EXTERNAL CHARGE PUMP ON FLASH MEMORY MODULE
37
Patent #:
Issue Dt:
05/29/2012
Application #:
13107724
Filing Dt:
05/13/2011
Publication #:
Pub Dt:
09/01/2011
Title:
TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS
38
Patent #:
Issue Dt:
08/20/2013
Application #:
13154616
Filing Dt:
06/07/2011
Publication #:
Pub Dt:
09/29/2011
Title:
DETERMINING A LOGIC STATE BASED ON CURRENTS RECEIVED BY A SENSE AMPLIFER
39
Patent #:
Issue Dt:
02/19/2013
Application #:
13155278
Filing Dt:
06/07/2011
Publication #:
Pub Dt:
09/29/2011
Title:
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
40
Patent #:
Issue Dt:
09/11/2012
Application #:
13156763
Filing Dt:
06/09/2011
Publication #:
Pub Dt:
09/29/2011
Title:
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
41
Patent #:
Issue Dt:
12/17/2013
Application #:
13158179
Filing Dt:
06/10/2011
Publication #:
Pub Dt:
04/26/2012
Title:
NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND DATA WRITE METHOD FOR THE SAME
42
Patent #:
Issue Dt:
01/07/2014
Application #:
13162520
Filing Dt:
06/16/2011
Publication #:
Pub Dt:
12/20/2012
Title:
METHOD AND APPARATUS FOR STAGGERED START-UP OF A PREDEFINED, RANDOM, OR DYNAMIC NUMBER OF FLASH MEMORY DEVICES
43
Patent #:
Issue Dt:
02/21/2017
Application #:
13179307
Filing Dt:
07/08/2011
Publication #:
Pub Dt:
01/12/2012
Title:
MEMORY DEVICES AND METHODS HAVING MULTIPLE ADDRESS ACCESSES IN SAME CYCLE
44
Patent #:
Issue Dt:
05/08/2018
Application #:
13180337
Filing Dt:
07/11/2011
Title:
MEMORY DEVICES HAVING EMBEDDED HARDWARE ACCELERATION AND CORRESPONDING METHODS
45
Patent #:
Issue Dt:
12/03/2013
Application #:
13185390
Filing Dt:
07/18/2011
Publication #:
Pub Dt:
01/24/2013
Title:
METHOD AND MANUFACTURE FOR EMBEDDED FLASH TO ACHIEVE HIGH QUALITY SPACERS FOR CORE AND HIGH VOLTAGE DEVICES AND LOW TEMPERATURE SPACERS FOR HIGH PERFORMANCE LOGIC DEVICES
46
Patent #:
Issue Dt:
01/26/2016
Application #:
13190565
Filing Dt:
07/26/2011
Publication #:
Pub Dt:
11/17/2011
Title:
ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB
47
Patent #:
Issue Dt:
11/20/2012
Application #:
13216546
Filing Dt:
08/24/2011
Publication #:
Pub Dt:
08/23/2012
Title:
METHOD AND APPARATUS TO IMPLEMENT A RESET FUNCTION IN A NON-VOLATILE STATIC RANDOM ACCESS MEMORY
48
Patent #:
Issue Dt:
01/08/2013
Application #:
13253634
Filing Dt:
10/05/2011
Publication #:
Pub Dt:
03/22/2012
Title:
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
49
Patent #:
Issue Dt:
07/23/2013
Application #:
13280937
Filing Dt:
10/25/2011
Publication #:
Pub Dt:
05/30/2013
Title:
MEMORY CELL ARRAY LATCHUP PREVENTION
50
Patent #:
Issue Dt:
07/04/2017
Application #:
13313699
Filing Dt:
12/07/2011
Publication #:
Pub Dt:
06/13/2013
Title:
HIGH SPEED SERIAL PERIPHERAL INTERFACE MEMORY SUBSYSTEM
51
Patent #:
Issue Dt:
04/15/2014
Application #:
13314932
Filing Dt:
12/08/2011
Publication #:
Pub Dt:
04/05/2012
Title:
CAPACITIVE ELEMENT USING MOS TRANSISTORS
52
Patent #:
Issue Dt:
02/04/2014
Application #:
13315060
Filing Dt:
12/08/2011
Publication #:
Pub Dt:
12/06/2012
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
53
Patent #:
Issue Dt:
04/29/2014
Application #:
13316137
Filing Dt:
12/09/2011
Publication #:
Pub Dt:
04/05/2012
Title:
SWITCHABLE MEMORY DIODES BASED ON FERROELECTRIC/CONJUGATED POLYMER HETEROSTRUCTURES AND/OR THEIR COMPOSITES
54
Patent #:
Issue Dt:
10/18/2016
Application #:
13323538
Filing Dt:
12/12/2011
Publication #:
Pub Dt:
12/13/2012
Title:
SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR
55
Patent #:
Issue Dt:
09/17/2013
Application #:
13326012
Filing Dt:
12/14/2011
Publication #:
Pub Dt:
04/05/2012
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING LOWER LEAKAGE CURRENT BETWEEN SEMICONDUCTOR SUBSTRATE AND BIT LINES
56
Patent #:
Issue Dt:
10/15/2013
Application #:
13340439
Filing Dt:
12/29/2011
Publication #:
Pub Dt:
07/04/2013
Title:
CAPACITOR POWER SOURCE TAMPER PROTECTION AND RELIABILITY TEST
57
Patent #:
Issue Dt:
08/04/2015
Application #:
13340453
Filing Dt:
12/29/2011
Title:
Device and Method of Establishing Sleep Mode Architecture for NVSRAMs
58
Patent #:
Issue Dt:
11/12/2013
Application #:
13355145
Filing Dt:
01/20/2012
Publication #:
Pub Dt:
08/09/2012
Title:
AUTHENTICATING FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) DEVICE AND METHOD
59
Patent #:
Issue Dt:
08/12/2014
Application #:
13357842
Filing Dt:
01/25/2012
Publication #:
Pub Dt:
07/25/2013
Title:
CONTINUOUS READ BURST SUPPORT AT HIGH CLOCK RATES
60
Patent #:
Issue Dt:
08/05/2014
Application #:
13399537
Filing Dt:
02/17/2012
Publication #:
Pub Dt:
08/22/2013
Title:
REDUNDANCY LOADING EFFICIENCY
61
Patent #:
Issue Dt:
04/22/2014
Application #:
13413527
Filing Dt:
03/06/2012
Publication #:
Pub Dt:
03/14/2013
Title:
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
62
Patent #:
Issue Dt:
02/24/2015
Application #:
13435445
Filing Dt:
03/30/2012
Publication #:
Pub Dt:
10/03/2013
Title:
APPARATUS AND METHOD FOR A REDUCED PIN COUNT (RPC) MEMORY BUS INTERFACE INCLUDING A READ DATA STROBE SIGNAL
63
Patent #:
Issue Dt:
05/13/2014
Application #:
13437324
Filing Dt:
04/02/2012
Publication #:
Pub Dt:
10/03/2013
Title:
ADAPTIVELY PROGRAMMING OR ERASING FLASH MEMORY BLOCKS
64
Patent #:
Issue Dt:
03/18/2014
Application #:
13459206
Filing Dt:
04/29/2012
Title:
HIGH SPEED TIME INTERLEAVED SENSE AMPLIFIER CIRCUITS, METHODS AND MEMORY DEVICES INCORPORATING THE SAME
65
Patent #:
Issue Dt:
12/23/2014
Application #:
13470117
Filing Dt:
05/11/2012
Publication #:
Pub Dt:
11/14/2013
Title:
ENHANCED HYDROGEN BARRIER ENCAPSULATION METHOD FOR THE CONTROL OF HYDROGEN INDUCED DEGRADATION OF FERROELECTRIC CAPACITORS IN AN F-RAM PROCESS
66
Patent #:
Issue Dt:
02/03/2015
Application #:
13471854
Filing Dt:
05/15/2012
Publication #:
Pub Dt:
11/21/2013
Title:
SOFT ERROR RESISTANT CIRCUITRY
67
Patent #:
Issue Dt:
06/04/2013
Application #:
13481582
Filing Dt:
05/25/2012
Publication #:
Pub Dt:
09/13/2012
Title:
TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS
68
Patent #:
Issue Dt:
09/23/2014
Application #:
13486972
Filing Dt:
06/01/2012
Publication #:
Pub Dt:
12/05/2013
Title:
METHOD, APPARATUS, AND MANUFACTURE FOR FLASH MEMORY ADAPTIVE ALGORITHM
69
Patent #:
Issue Dt:
10/14/2014
Application #:
13536661
Filing Dt:
06/28/2012
Title:
HIGH RELIABILITY NON-VOLATILE STATIC RANDOM ACCESS MEMORY DEVICES, METHODS AND SYSTEMS
70
Patent #:
Issue Dt:
04/05/2016
Application #:
13537877
Filing Dt:
06/29/2012
Publication #:
Pub Dt:
01/02/2014
Title:
MEMORY CONTROLLER DEVICES, SYSTEMS AND METHODS FOR TRANSLATING MEMORY REQUESTS BETWEEN FIRST AND SECOND FORMATS FOR HIGH RELIABILITY MEMORY DEVICES
71
Patent #:
Issue Dt:
11/24/2015
Application #:
13545469
Filing Dt:
07/10/2012
Publication #:
Pub Dt:
01/16/2014
Title:
LEAKAGE REDUCING WRITELINE CHARGE PROTECTION CIRCUIT
72
Patent #:
Issue Dt:
08/12/2014
Application #:
13556819
Filing Dt:
07/24/2012
Publication #:
Pub Dt:
02/07/2013
Title:
IMAGING DEVICE HAVING A RADIATION DETECTING STRUCTURE SENSITIVE TO NEUTRON RADIATION
73
Patent #:
Issue Dt:
04/15/2014
Application #:
13563206
Filing Dt:
07/31/2012
Publication #:
Pub Dt:
02/06/2014
Title:
BITLINE VOLTAGE REGULATION IN NON-VOLATILE MEMORY
74
Patent #:
Issue Dt:
06/02/2015
Application #:
13566187
Filing Dt:
08/03/2012
Publication #:
Pub Dt:
02/06/2014
Title:
Power Savings Apparatus and Method for Memory Device Using Delay Locked Loop
75
Patent #:
Issue Dt:
10/15/2013
Application #:
13569442
Filing Dt:
08/08/2012
Publication #:
Pub Dt:
11/22/2012
Title:
CONTROLLING AC DISTURBANCE WHILE PROGRAMMING
76
Patent #:
Issue Dt:
10/08/2013
Application #:
13569735
Filing Dt:
08/08/2012
Publication #:
Pub Dt:
02/14/2013
Title:
METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) DEVICE STRUCTURE EMPLOYING REDUCED PROCESSING STEPS
77
Patent #:
Issue Dt:
08/27/2013
Application #:
13569755
Filing Dt:
08/08/2012
Publication #:
Pub Dt:
02/14/2013
Title:
METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) WITH SIMULTANEOUS FORMATION OF SIDEWALL FERROELECTRIC CAPACITORS
78
Patent #:
Issue Dt:
08/27/2013
Application #:
13569785
Filing Dt:
08/08/2012
Publication #:
Pub Dt:
02/14/2013
Title:
METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) HAVING A FERROELECTRIC CAPACITOR ALIGNED WITH A THREE DIMENSIONAL TRANSISTOR STRUCTURE
79
Patent #:
Issue Dt:
08/27/2013
Application #:
13600527
Filing Dt:
08/31/2012
Publication #:
Pub Dt:
12/27/2012
Title:
HIGH READ SPEED MEMORY WITH GATE ISOLATION
80
Patent #:
Issue Dt:
12/31/2013
Application #:
13608698
Filing Dt:
09/10/2012
Publication #:
Pub Dt:
01/03/2013
Title:
LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE
81
Patent #:
Issue Dt:
12/17/2013
Application #:
13610368
Filing Dt:
09/11/2012
Publication #:
Pub Dt:
06/20/2013
Title:
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
82
Patent #:
Issue Dt:
11/12/2013
Application #:
13613448
Filing Dt:
09/13/2012
Publication #:
Pub Dt:
01/03/2013
Title:
RADIATION DETECTING DEVICE AND METHOD OF OPERATING
83
Patent #:
Issue Dt:
07/08/2014
Application #:
13622796
Filing Dt:
09/19/2012
Publication #:
Pub Dt:
01/17/2013
Title:
SEMICONDUCTOR MEMORY DEVICE FEATURING SELECTIVE DATA STORAGE IN A STACKED MEMORY CELL STRUCTURE
84
Patent #:
Issue Dt:
11/03/2015
Application #:
13644895
Filing Dt:
10/04/2012
Publication #:
Pub Dt:
04/10/2014
Title:
SUPPLY POWER DEPENDENT CONTROLLABLE WRITE THROUGHPUT FOR MEMORY APPLICATIONS
85
Patent #:
Issue Dt:
05/13/2014
Application #:
13668935
Filing Dt:
11/05/2012
Publication #:
Pub Dt:
03/07/2013
Title:
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
86
Patent #:
Issue Dt:
03/03/2015
Application #:
13680507
Filing Dt:
11/19/2012
Publication #:
Pub Dt:
05/22/2014
Title:
DATA REFRESH IN NON-VOLATILE MEMORY
87
Patent #:
Issue Dt:
09/23/2014
Application #:
13685331
Filing Dt:
11/26/2012
Publication #:
Pub Dt:
05/29/2014
Title:
METHOD FOR IMPROVING DATA RETENTION IN A 2T/2C FERROELECTRIC MEMORY
88
Patent #:
Issue Dt:
05/08/2018
Application #:
13715185
Filing Dt:
12/14/2012
Publication #:
Pub Dt:
06/19/2014
Title:
Charge Trapping Split Gate Device and Method of Fabricating Same
89
Patent #:
Issue Dt:
09/16/2014
Application #:
13715565
Filing Dt:
12/14/2012
Publication #:
Pub Dt:
06/19/2014
Title:
INTEGRATED CIRCUITS WITH NON-VOLATILE MEMORY AND METHODS FOR MANUFACTURE
90
Patent #:
Issue Dt:
06/14/2016
Application #:
13715577
Filing Dt:
12/14/2012
Publication #:
Pub Dt:
06/19/2014
Title:
MEMORY FIRST PROCESS FLOW AND DEVICE
91
Patent #:
Issue Dt:
08/26/2014
Application #:
13715705
Filing Dt:
12/14/2012
Publication #:
Pub Dt:
06/19/2014
Title:
Process Charging Protection for Split Gate Charge Trapping Flash
92
Patent #:
Issue Dt:
09/03/2013
Application #:
13717637
Filing Dt:
12/17/2012
Title:
MEMORY DEVICE DATA LATENCY CIRCUITS AND METHODS
93
Patent #:
Issue Dt:
04/05/2016
Application #:
13725415
Filing Dt:
12/21/2012
Publication #:
Pub Dt:
06/26/2014
Title:
Memory Device with Internal Combination Logic
94
Patent #:
Issue Dt:
04/22/2014
Application #:
13727505
Filing Dt:
12/26/2012
Publication #:
Pub Dt:
02/27/2014
Title:
ACCESS METHODS AND CIRCUITS FOR MEMORY DEVICES HAVING MULTIPLE BANKS
95
Patent #:
Issue Dt:
02/24/2015
Application #:
13729153
Filing Dt:
12/28/2012
Publication #:
Pub Dt:
07/03/2014
Title:
DESIGN FOR TEST (DFT) READ SPEED THROUGH TRANSITION DETECTOR IN BUILT-IN SELF-TEST (BIST) SORT
96
Patent #:
Issue Dt:
04/19/2016
Application #:
13735156
Filing Dt:
01/07/2013
Publication #:
Pub Dt:
07/10/2014
Title:
BURIED HARD MASK FOR EMBEDDED SEMICONDUCTOR DEVICE PATTERNING
97
Patent #:
Issue Dt:
05/26/2015
Application #:
13737321
Filing Dt:
01/09/2013
Publication #:
Pub Dt:
07/10/2014
Title:
PROGRAMMABLE AND FLEXIBLE REFERENCE CELL SELECTION METHOD FOR MEMORY DEVICES
98
Patent #:
Issue Dt:
12/29/2015
Application #:
13749246
Filing Dt:
01/24/2013
Publication #:
Pub Dt:
05/30/2013
Title:
SEMICONDUCTOR MEMORY READ AND WRITE ACCESS
99
Patent #:
Issue Dt:
10/21/2014
Application #:
13753676
Filing Dt:
01/30/2013
Publication #:
Pub Dt:
07/31/2014
Title:
NON-VOLATILE MEMORY WITH SILICIDED BIT LINE CONTACTS
100
Patent #:
Issue Dt:
06/28/2016
Application #:
13761217
Filing Dt:
02/07/2013
Publication #:
Pub Dt:
08/07/2014
Title:
NON-VOLATILE MEMORY DEVICE WITH AN EPLI COMPARATOR
Assignor
1
Exec Dt:
03/15/2020
Assignee
1
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134

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