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Reel/Frame:059721/0467   Pages: 54
Recorded: 04/15/2022
Attorney Dkt #:CYPRESS TO IFXLLC
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 668
Page 6 of 7
Pages: 1 2 3 4 5 6 7
1
Patent #:
Issue Dt:
06/24/2014
Application #:
13769398
Filing Dt:
02/18/2013
Title:
MEMORY DEVICE WITH SOURCE-SIDE SENSING
2
Patent #:
Issue Dt:
04/15/2014
Application #:
13771043
Filing Dt:
02/19/2013
Publication #:
Pub Dt:
07/04/2013
Title:
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
3
Patent #:
Issue Dt:
12/17/2013
Application #:
13776310
Filing Dt:
02/25/2013
Publication #:
Pub Dt:
07/11/2013
Title:
FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS
4
Patent #:
Issue Dt:
03/11/2014
Application #:
13776337
Filing Dt:
02/25/2013
Publication #:
Pub Dt:
06/27/2013
Title:
FABRICATING METHOD OF MIRROR BIT MEMORY DEVICE HAVING SPLIT ONO FILM WITH TOP OXIDE FILM FORMED BY OXIDATION PROCESS
5
Patent #:
Issue Dt:
06/10/2014
Application #:
13786216
Filing Dt:
03/05/2013
Publication #:
Pub Dt:
08/01/2013
Title:
A CHARGE STORAGE DEVICE FOR DETECTING ALPHA PARTICLES
6
Patent #:
Issue Dt:
09/22/2015
Application #:
13790979
Filing Dt:
03/08/2013
Publication #:
Pub Dt:
09/11/2014
Title:
PIPELINING IN A MEMORY
7
Patent #:
Issue Dt:
11/25/2014
Application #:
13795036
Filing Dt:
03/12/2013
Title:
NONVOLATILE MEMORY CELLS AND METHODS OF MAKING SUCH CELLS
8
Patent #:
Issue Dt:
10/28/2014
Application #:
13795134
Filing Dt:
03/12/2013
Title:
DATA FORWARDING CIRCUITS AND METHODS FOR MEMORY DEVICES WITH WRITE LATENCY
9
Patent #:
Issue Dt:
09/20/2016
Application #:
13856313
Filing Dt:
04/03/2013
Publication #:
Pub Dt:
10/09/2014
Title:
MODIFIED LOCAL SEGMENTED SELF-BOOSTING OF MEMORY CELL CHANNELS
10
Patent #:
Issue Dt:
09/30/2014
Application #:
13856816
Filing Dt:
04/04/2013
Title:
Erase verification circuitry for simultaneously and consecutively verifying a plurality of odd and even-numbered flash memory transistors and method thereof
11
Patent #:
Issue Dt:
12/16/2014
Application #:
13865714
Filing Dt:
04/18/2013
Publication #:
Pub Dt:
10/23/2014
Title:
Die Seal Layout for VFTL Dual Damascene in a Semiconductor Device
12
Patent #:
Issue Dt:
04/04/2017
Application #:
13867618
Filing Dt:
04/22/2013
Publication #:
Pub Dt:
10/23/2014
Title:
CHARGE-TRAP NOR WITH SILICON-RICH NITRIDE AS A CHARGE TRAP LAYER
13
Patent #:
Issue Dt:
10/25/2016
Application #:
13913909
Filing Dt:
06/10/2013
Publication #:
Pub Dt:
12/11/2014
Title:
Programmable Latency Count to Achieve Higher Memory Bandwidth
14
Patent #:
Issue Dt:
09/22/2015
Application #:
13917141
Filing Dt:
06/13/2013
Publication #:
Pub Dt:
12/18/2014
Title:
Screening for Reference Cells in a Memory
15
Patent #:
Issue Dt:
06/10/2014
Application #:
13920742
Filing Dt:
06/18/2013
Publication #:
Pub Dt:
10/24/2013
Title:
FLASH MEMORY DEVICES AND METHODS FOR FABRICATING SAME
16
Patent #:
Issue Dt:
05/13/2014
Application #:
13921056
Filing Dt:
06/18/2013
Title:
NVSRAM WITH INVERTED RECALL
17
Patent #:
Issue Dt:
01/19/2016
Application #:
13924292
Filing Dt:
06/21/2013
Title:
METHOD MINIMIZING IMPRINT THROUGH PACKAGING OF F-RAM
18
Patent #:
Issue Dt:
09/16/2014
Application #:
13949116
Filing Dt:
07/23/2013
Publication #:
Pub Dt:
04/10/2014
Title:
MEMORY CELL ARRAY LATCHUP PREVENTION
19
Patent #:
Issue Dt:
01/21/2014
Application #:
13964958
Filing Dt:
08/12/2013
Publication #:
Pub Dt:
02/06/2014
Title:
APPARATUS AND METHOD FOR A METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SOURCE SIDE PUNCH-THROUGH PROTECTION IMPLANT
20
Patent #:
Issue Dt:
05/20/2014
Application #:
14010134
Filing Dt:
08/26/2013
Publication #:
Pub Dt:
03/27/2014
Title:
METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERRORELECTRIC RANDOM ACCESS MEMORY (F-RAM) WITH SIMULTANEOUS FORMATION OF SIDEWALL FERROELECTRIC CAPACITORS
21
Patent #:
Issue Dt:
04/19/2016
Application #:
14010174
Filing Dt:
08/26/2013
Publication #:
Pub Dt:
04/03/2014
Title:
METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERRORELECTRIC RANDOM ACCESS MEMORY (F-RAM) HAVING A FERROELECTRIC CAPACITOR ALIGNED WITH A THREE DIMENSIONAL TRANSISTOR STRUCTURE
22
Patent #:
Issue Dt:
07/09/2019
Application #:
14026118
Filing Dt:
09/13/2013
Title:
METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERRORELECTRIC RANDOM ACCESS MEMORY (F-RAM) DEVICE STRUCTURE EMPLOYING REDUCED PROCESSING STEPS
23
Patent #:
Issue Dt:
10/04/2016
Application #:
14033170
Filing Dt:
09/20/2013
Publication #:
Pub Dt:
01/23/2014
Title:
DUAL STORAGE NODE MEMORY
24
Patent #:
Issue Dt:
02/24/2015
Application #:
14040616
Filing Dt:
09/27/2013
Title:
FERROELECTRIC MEMORIES WITH A STRESS BUFFER
25
Patent #:
Issue Dt:
11/03/2015
Application #:
14048076
Filing Dt:
10/08/2013
Publication #:
Pub Dt:
04/09/2015
Title:
METHODS CIRCUITS APPARATUSES AND SYSTEMS FOR PROVIDING CURRENT TO A NON-VOLATILE MEMORY ARRAY AND NON-VOLATILE MEMORY DEVICES PRODUCED ACCORDINGLY
26
Patent #:
Issue Dt:
09/06/2016
Application #:
14048863
Filing Dt:
10/08/2013
Publication #:
Pub Dt:
04/09/2015
Title:
SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS
27
Patent #:
Issue Dt:
03/31/2015
Application #:
14050490
Filing Dt:
10/10/2013
Publication #:
Pub Dt:
04/16/2015
Title:
MULTI-PASS SOFT PROGRAMMING
28
Patent #:
Issue Dt:
10/11/2016
Application #:
14051828
Filing Dt:
10/11/2013
Publication #:
Pub Dt:
04/16/2015
Title:
SPACER FORMATION WITH STRAIGHT SIDEWALL
29
Patent #:
Issue Dt:
08/15/2017
Application #:
14051859
Filing Dt:
10/11/2013
Publication #:
Pub Dt:
04/16/2015
Title:
ION IMPLANTATION-ASSISTED ETCH-BACK PROCESS FOR IMPROVING SPACER SHAPE AND SPACER WIDTH CONTROL
30
Patent #:
Issue Dt:
09/27/2016
Application #:
14054265
Filing Dt:
10/15/2013
Publication #:
Pub Dt:
04/16/2015
Title:
METHOD FOR PROVIDING READ DATA FLOW CONTROL OR ERROR REPORTING USING A READ DATA STROBE
31
Patent #:
Issue Dt:
08/30/2016
Application #:
14054880
Filing Dt:
10/16/2013
Publication #:
Pub Dt:
04/16/2015
Title:
MEMORY PROGRAM UPON SYSTEM FAILURE
32
Patent #:
Issue Dt:
08/15/2017
Application #:
14056547
Filing Dt:
10/17/2013
Publication #:
Pub Dt:
04/23/2015
Title:
MULTIPLE PHASE-SHIFT PHOTOMASK AND SEMICONDUCTOR MANUFACTURING METHOD
33
Patent #:
Issue Dt:
12/24/2019
Application #:
14059077
Filing Dt:
10/21/2013
Publication #:
Pub Dt:
02/13/2014
Title:
CONTACTS FOR SEMICONDUCTOR DEVICES
34
Patent #:
Issue Dt:
01/03/2017
Application #:
14073031
Filing Dt:
11/06/2013
Publication #:
Pub Dt:
05/07/2015
Title:
METHODS, CIRCUITS, SYSTEMS AND COMPUTER EXECUTABLE INSTRUCTION SETS FOR PROVIDING ERROR CORRECTION OF STORED DATA AND DATA STORAGE DEVICES UTILIZING SAME
35
Patent #:
Issue Dt:
03/31/2015
Application #:
14073914
Filing Dt:
11/07/2013
Title:
METHODS CIRCUITS APPARATUSES AND SYSTEMS FOR SENSING A LOGICAL STATE OF A NON-VOLATILE MEMORY CELL AND NON-VOLATILE MEMORY DEVICES PRODUCED ACCORDINGLY
36
Patent #:
Issue Dt:
05/03/2016
Application #:
14077971
Filing Dt:
11/12/2013
Title:
AUTHENTICATING FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) DEVICE AND METHOD
37
Patent #:
Issue Dt:
03/31/2015
Application #:
14081987
Filing Dt:
11/15/2013
Publication #:
Pub Dt:
07/31/2014
Title:
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
38
Patent #:
Issue Dt:
06/21/2016
Application #:
14092554
Filing Dt:
11/27/2013
Publication #:
Pub Dt:
05/28/2015
Title:
AUTO RESUME OF IRREGULAR ERASE STOPPAGE OF A MEMORY SECTOR
39
Patent #:
Issue Dt:
05/19/2015
Application #:
14099340
Filing Dt:
12/06/2013
Publication #:
Pub Dt:
04/03/2014
Title:
METHOD AND APPARATUS FOR STAGGERED START-UP OF A PREDEFINED, RANDOM OR DYNAMIC NUMBER OF FLASH MEMORY DEVICES
40
Patent #:
Issue Dt:
01/17/2017
Application #:
14109045
Filing Dt:
12/17/2013
Publication #:
Pub Dt:
01/01/2015
Title:
METHODS OF FABRICATING AN F-RAM
41
Patent #:
Issue Dt:
09/27/2016
Application #:
14109157
Filing Dt:
12/17/2013
Publication #:
Pub Dt:
06/19/2014
Title:
HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE
42
Patent #:
Issue Dt:
11/15/2016
Application #:
14132422
Filing Dt:
12/18/2013
Publication #:
Pub Dt:
06/18/2015
Title:
INCREASING LITHOGRAPHIC DEPTH OF FOCUS WINDOW USING WAFER TOPOGRAPHY
43
Patent #:
Issue Dt:
06/07/2016
Application #:
14135863
Filing Dt:
12/20/2013
Publication #:
Pub Dt:
06/25/2015
Title:
CT-NOR DIFFERENTIAL BITLINE SENSING ARCHITECTURE
44
Patent #:
Issue Dt:
06/14/2016
Application #:
14136358
Filing Dt:
12/20/2013
Publication #:
Pub Dt:
06/25/2015
Title:
GATE FORMATION MEMORY BY PLANARIZATION
45
Patent #:
Issue Dt:
02/02/2016
Application #:
14143317
Filing Dt:
12/30/2013
Publication #:
Pub Dt:
07/02/2015
Title:
Formation of Gate Sidewall Structure
46
Patent #:
Issue Dt:
09/22/2015
Application #:
14149484
Filing Dt:
01/07/2014
Publication #:
Pub Dt:
05/01/2014
Title:
DATA WRITING METHOD AND SYSTEM
47
Patent #:
Issue Dt:
08/23/2016
Application #:
14153900
Filing Dt:
01/13/2014
Publication #:
Pub Dt:
05/08/2014
Title:
ELECTRICALLY PROGRAMMABLE AND ERASEABLE MEMORY DEVICE
48
Patent #:
Issue Dt:
10/17/2017
Application #:
14188048
Filing Dt:
02/24/2014
Publication #:
Pub Dt:
08/27/2015
Title:
MEMORY SUBSYSTEM WITH WRAPPED-TO-CONTINUOUS READ
49
Patent #:
Issue Dt:
03/07/2017
Application #:
14199837
Filing Dt:
03/06/2014
Publication #:
Pub Dt:
09/10/2015
Title:
Memory Access Bases on Erase Cycle Time
50
Patent #:
Issue Dt:
02/02/2016
Application #:
14207303
Filing Dt:
03/12/2014
Publication #:
Pub Dt:
09/17/2015
Title:
BURIED TRENCH ISOLATION IN INTEGRATED CIRCUITS
51
Patent #:
Issue Dt:
10/18/2016
Application #:
14222399
Filing Dt:
03/21/2014
Publication #:
Pub Dt:
01/01/2015
Title:
SYSTEM WITH MEMORY HAVING VOLTAGE APPLYING UNIT
52
Patent #:
Issue Dt:
08/18/2015
Application #:
14222904
Filing Dt:
03/24/2014
Publication #:
Pub Dt:
03/12/2015
Title:
METHOD OF FABRICATING A FERROELECTRIC CAPACITOR
53
Patent #:
Issue Dt:
05/28/2019
Application #:
14228384
Filing Dt:
03/28/2014
Publication #:
Pub Dt:
07/31/2014
Title:
VARIABLE READ LATENCY ON A SERIAL MEMORY BUS
54
Patent #:
Issue Dt:
06/07/2016
Application #:
14228899
Filing Dt:
03/28/2014
Publication #:
Pub Dt:
04/30/2015
Title:
MULTI-CHANNEL, MULTI-BANK MEMORY WITH WIDE DATA INPUT/OUTPUT
55
Patent #:
Issue Dt:
12/29/2015
Application #:
14229765
Filing Dt:
03/28/2014
Publication #:
Pub Dt:
04/30/2015
Title:
MULTI-CHANNEL PHYSICAL INTERFACES AND METHODS FOR STATIC RANDOM ACCESS MEMORY DEVICES
56
Patent #:
Issue Dt:
12/12/2017
Application #:
14229908
Filing Dt:
03/29/2014
Publication #:
Pub Dt:
07/31/2014
Title:
MEMORY CELL ARRAY LATCHUP PREVENTION
57
Patent #:
Issue Dt:
03/13/2018
Application #:
14254237
Filing Dt:
04/16/2014
Publication #:
Pub Dt:
08/14/2014
Title:
FLASH MEMORY CELLS HAVING TRENCHED STORAGE ELEMENTS
58
Patent #:
Issue Dt:
05/30/2017
Application #:
14258950
Filing Dt:
04/22/2014
Publication #:
Pub Dt:
11/20/2014
Title:
ACCESS METHODS AND CIRCUITS FOR MEMORY DEVICES HAVING MULTIPLE BANKS
59
Patent #:
Issue Dt:
10/25/2016
Application #:
14284812
Filing Dt:
05/22/2014
Publication #:
Pub Dt:
11/26/2015
Title:
METHODS, CIRCUITS, DEVICES AND SYSTEMS FOR INTEGRATED CIRCUIT VOLTAGE LEVEL SHIFTING
60
Patent #:
Issue Dt:
04/14/2015
Application #:
14303014
Filing Dt:
06/12/2014
Publication #:
Pub Dt:
03/12/2015
Title:
ELIMINATING SHORTING BETWEEN FERROELECTRIC CAPACITORS AND METAL CONTACTS DURING FERROELECTRIC RANDOM ACCESS MEMORY FABRICATION
61
Patent #:
Issue Dt:
07/10/2018
Application #:
14319079
Filing Dt:
06/30/2014
Publication #:
Pub Dt:
12/31/2015
Title:
BOOTING AN APPLICATION FROM MULTIPLE MEMORIES
62
Patent #:
Issue Dt:
03/07/2017
Application #:
14450727
Filing Dt:
08/04/2014
Publication #:
Pub Dt:
02/04/2016
Title:
SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE
63
Patent #:
Issue Dt:
05/17/2016
Application #:
14458542
Filing Dt:
08/13/2014
Publication #:
Pub Dt:
02/18/2016
Title:
INTEGRATION OF SEMICONDUCTOR MEMORY CELLS AND LOGIC CELLS
64
Patent #:
Issue Dt:
02/02/2016
Application #:
14472043
Filing Dt:
08/28/2014
Title:
TEST CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME
65
Patent #:
Issue Dt:
06/14/2016
Application #:
14484417
Filing Dt:
09/12/2014
Publication #:
Pub Dt:
01/29/2015
Title:
INTEGRATED CIRCUITS WITH NON-VOLATILE MEMORY AND METHODS FOR MANUFACTURE
66
Patent #:
Issue Dt:
02/02/2016
Application #:
14501536
Filing Dt:
09/30/2014
Publication #:
Pub Dt:
01/15/2015
Title:
NON-VOLATILE MEMORY WITH SILICIDED BIT LINE CONTACTS
67
Patent #:
Issue Dt:
02/14/2017
Application #:
14512647
Filing Dt:
10/13/2014
Title:
HIGH RELIABILITY NON-VOLATILE STATIC RANDOM ACCESS MEMORY DEVICES, METHODS AND SYSTEMS
68
Patent #:
Issue Dt:
03/14/2017
Application #:
14514008
Filing Dt:
10/14/2014
Publication #:
Pub Dt:
04/30/2015
Title:
ENHANCED HYDROGEN BARRIER ENCAPSULATION METHOD FOR THE CONTROL OF HYDROGEN INDUCED DEGRADATION OF FERROELECTRIC CAPACITORS IN AN F-RAM PROCESS
69
Patent #:
Issue Dt:
05/10/2016
Application #:
14517201
Filing Dt:
10/17/2014
Publication #:
Pub Dt:
04/21/2016
Title:
Simultaneous Programming of Many Bits in Flash Memory
70
Patent #:
Issue Dt:
06/14/2016
Application #:
14517470
Filing Dt:
10/17/2014
Publication #:
Pub Dt:
02/19/2015
Title:
LINE-EDGE ROUGHNESS IMPROVEMENT FOR SMALL PITCHES
71
Patent #:
Issue Dt:
06/05/2018
Application #:
14518560
Filing Dt:
10/20/2014
Publication #:
Pub Dt:
04/21/2016
Title:
OVERLAID ERASE BLOCK MAPPING
72
Patent #:
Issue Dt:
04/25/2017
Application #:
14562789
Filing Dt:
12/08/2014
Publication #:
Pub Dt:
06/09/2016
Title:
METHODS, CIRCUITS, DEVICES, SYSTEMS AND MACHINE EXECUTABLE CODE FOR READING FROM A NON-VOLATILE MEMORY ARRAY
73
Patent #:
Issue Dt:
09/12/2017
Application #:
14570801
Filing Dt:
12/15/2014
Title:
CONTROLLING THE LATCHUP EFFECT
74
Patent #:
Issue Dt:
12/20/2016
Application #:
14630238
Filing Dt:
02/24/2015
Publication #:
Pub Dt:
06/18/2015
Title:
FRACTURED ERASE SYSTEM AND METHOD
75
Patent #:
Issue Dt:
03/27/2018
Application #:
14716719
Filing Dt:
05/19/2015
Title:
METHOD AND APPARATUS FOR STAGGERED START-UP OF A PREDEFINED, RANDOM, OR DYNAMIC NUMBER OF FLASH MEMORY DEVICES
76
Patent #:
Issue Dt:
04/05/2016
Application #:
14738492
Filing Dt:
06/12/2015
Title:
METHODS OF FABRICATING AN F-RAM
77
Patent #:
Issue Dt:
03/07/2017
Application #:
14742201
Filing Dt:
06/17/2015
Publication #:
Pub Dt:
10/08/2015
Title:
USE DISPOSABLE GATE CAP TO FORM TRANSISTORS, AND SPLIT GATE CHARGE TRAPPING MEMORY CELLS
78
Patent #:
Issue Dt:
09/27/2016
Application #:
14822085
Filing Dt:
08/10/2015
Title:
POWER MANAGEMENT SYSTEM FOR HIGH TRAFFIC INTEGRATED CIRCUIT
79
Patent #:
Issue Dt:
08/01/2017
Application #:
14860035
Filing Dt:
09/21/2015
Publication #:
Pub Dt:
07/21/2016
Title:
DATA WRITING METHOD AND SYSTEM
80
Patent #:
Issue Dt:
12/06/2016
Application #:
14864594
Filing Dt:
09/24/2015
Publication #:
Pub Dt:
12/15/2016
Title:
Non-Volatile Static RAM and Method of Operation Thereof
81
Patent #:
Issue Dt:
05/02/2017
Application #:
14866260
Filing Dt:
09/25/2015
Title:
ACCESS METHODS AND CIRCUITS FOR MEMORY DEVICES HAVING MULTIPLE CHANNELS AND MULTIPLE BANKS
82
Patent #:
Issue Dt:
05/09/2017
Application #:
14886663
Filing Dt:
10/19/2015
Publication #:
Pub Dt:
04/21/2016
Title:
10-TRANSISTOR NON-VOLATILE STATIC RANDOM-ACCESS MEMORY USING A SINGLE NON-VOLATILE MEMORY ELEMENT AND METHOD OF OPERATION THEREOF
83
Patent #:
Issue Dt:
02/13/2018
Application #:
14929428
Filing Dt:
11/02/2015
Publication #:
Pub Dt:
08/11/2016
Title:
POWER SUPPLY INCLUDING REGULATING TRANSISTOR FOR PROVIDING CURRENT TO A LOAD AND NON-VOLATILE MEMORY DEVICES PRODUCED ACCORDINGLY
84
Patent #:
Issue Dt:
12/06/2016
Application #:
14930484
Filing Dt:
11/02/2015
Publication #:
Pub Dt:
04/07/2016
Title:
Supply Power Dependent Controllable Write Throughput for Memory Applications
85
Patent #:
Issue Dt:
05/09/2017
Application #:
14970063
Filing Dt:
12/15/2015
Publication #:
Pub Dt:
12/01/2016
Title:
FERROELECTRIC RANDOM-ACCESS MEMORY WITH PRE-PATTERNED OXYGEN BARRIER
86
Patent #:
Issue Dt:
03/20/2018
Application #:
14971531
Filing Dt:
12/16/2015
Publication #:
Pub Dt:
04/21/2016
Title:
CHARGE TRAPPING SPLIT GATE EMBEDDED FLASH MEMORY AND ASSOCIATED METHODS
87
Patent #:
Issue Dt:
05/30/2017
Application #:
15006288
Filing Dt:
01/26/2016
Publication #:
Pub Dt:
07/21/2016
Title:
NON-VOLATILE MEMORY WITH SILICIDED BIT LINE CONTACTS
88
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04/14/2020
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15048886
Filing Dt:
02/19/2016
Publication #:
Pub Dt:
07/14/2016
Title:
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Issue Dt:
05/09/2017
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Filing Dt:
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Pub Dt:
10/20/2016
Title:
Memory Device with Internal Combination Logic
90
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Issue Dt:
11/27/2018
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15060249
Filing Dt:
03/03/2016
Title:
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91
Patent #:
Issue Dt:
12/06/2016
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15065410
Filing Dt:
03/09/2016
Title:
METHOD FOR FABRICATING FERROELECTRIC RANDOM-ACCESS MEMORY ON PRE-PATTERNED BOTTOM ELECTRODE AND OXIDATION BARRIER
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Issue Dt:
03/28/2017
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15079462
Filing Dt:
03/24/2016
Title:
MULTI-BIT NON-VOLATILE RANDOM-ACCESS MEMORY CELLS
93
Patent #:
Issue Dt:
04/18/2017
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15088557
Filing Dt:
04/01/2016
Title:
Hydrogen Barriers in a Copper Interconnect Process
94
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06/06/2017
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Filing Dt:
04/19/2016
Publication #:
Pub Dt:
10/13/2016
Title:
BURIED HARD MASK FOR EMBEDDED SEMICONDUCTOR DEVICE PATTERNING
95
Patent #:
Issue Dt:
12/06/2016
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Filing Dt:
06/10/2016
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Issue Dt:
03/13/2018
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Filing Dt:
06/13/2016
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Pub Dt:
10/06/2016
Title:
Memory First Process Flow and Device
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11/28/2017
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Filing Dt:
06/24/2016
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Patent #:
Issue Dt:
07/23/2019
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15198235
Filing Dt:
06/30/2016
Publication #:
Pub Dt:
10/20/2016
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Issue Dt:
11/06/2018
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Filing Dt:
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Publication #:
Pub Dt:
03/30/2017
Title:
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Patent #:
Issue Dt:
09/11/2018
Application #:
15279194
Filing Dt:
09/28/2016
Publication #:
Pub Dt:
12/14/2017
Title:
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Assignor
1
Exec Dt:
03/15/2020
Assignee
1
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT
SAN JOSE, CA 95134

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