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Reel/Frame:060885/0001   Pages: 253
Recorded: 04/15/2022
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1129
Page 11 of 12
Pages: 1 2 3 4 5 6 7 8 9 10 11 12
1
Patent #:
Issue Dt:
08/29/2006
Application #:
11075195
Filing Dt:
03/07/2005
Title:
OPTICAL ERROR MINIMIZATION IN A SEMICONDUCTOR MANUFACTURING APPARATUS
2
Patent #:
Issue Dt:
12/25/2007
Application #:
11090107
Filing Dt:
03/24/2005
Publication #:
Pub Dt:
08/25/2005
Title:
DUAL DAMASCENE INTERCONNECT STRUCTURE WITH IMPROVED ELECTRO MIGRATION LIFETIMES
3
Patent #:
Issue Dt:
02/12/2008
Application #:
11094975
Filing Dt:
03/31/2005
Publication #:
Pub Dt:
10/12/2006
Title:
SEMICONDUCTOR STRUCTURE FORMED USING A SACRIFICIAL STRUCTURE
4
Patent #:
Issue Dt:
10/31/2006
Application #:
11098290
Filing Dt:
04/04/2005
Publication #:
Pub Dt:
08/04/2005
Title:
ION RECOIL IMPLANTATION AND ENHANCED CARRIER MOBILITY IN CMOS DEVICE
5
Patent #:
Issue Dt:
08/29/2006
Application #:
11104050
Filing Dt:
04/11/2005
Title:
SEMICONDUCTOR CHIP WITH BORDERLESS CONTACT THAT AVOIDS WELL LEAKAGE
6
Patent #:
Issue Dt:
11/20/2007
Application #:
11116903
Filing Dt:
04/28/2005
Publication #:
Pub Dt:
09/01/2005
Title:
METAL-OXIDE-SEMICONDUCTOR DEVICE INCLUDING A BURIED LIGHTLY-DOPED DRAIN REGION
7
Patent #:
Issue Dt:
07/15/2008
Application #:
11124307
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
11/09/2006
Title:
METHODS AND APPARATUS FOR DETERMINING LOCATION-BASED ON-CHIP VARIATION FACTOR
8
Patent #:
Issue Dt:
09/23/2008
Application #:
11131003
Filing Dt:
05/16/2005
Publication #:
Pub Dt:
09/22/2005
Title:
DIELECTRIC BARRIER FILMS FOR USE AS COPPER BARRIER LAYERS IN SEMICONDUCTOR TRENCH AND VIA STRUCTURES
9
Patent #:
Issue Dt:
01/29/2008
Application #:
11131705
Filing Dt:
05/18/2005
Publication #:
Pub Dt:
10/13/2005
Title:
VOLTAGE CONTRAST MONITOR FOR INTEGRATED CIRCUIT DEFECTS
10
Patent #:
Issue Dt:
11/07/2006
Application #:
11138152
Filing Dt:
05/26/2005
Publication #:
Pub Dt:
02/02/2006
Title:
METHOD OF ELECTRICAL TESTING
11
Patent #:
Issue Dt:
09/12/2006
Application #:
11140142
Filing Dt:
05/27/2005
Title:
METHOD AND SYSTEM FOR AREA EFFICIENT CHARGE-BASED CAPACITANCE MEASUREMENT
12
Patent #:
NONE
Issue Dt:
Application #:
11158450
Filing Dt:
06/21/2005
Publication #:
Pub Dt:
08/24/2006
Title:
Systems and methods for wafer polishing
13
Patent #:
Issue Dt:
10/12/2010
Application #:
11167772
Filing Dt:
06/27/2005
Publication #:
Pub Dt:
12/22/2005
Title:
SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE THEREFOR
14
Patent #:
Issue Dt:
11/02/2010
Application #:
11182615
Filing Dt:
07/15/2005
Publication #:
Pub Dt:
01/18/2007
Title:
DIGITALLY OBTAINING CONTOURS OF FABRICATED POLYGONS
15
Patent #:
NONE
Issue Dt:
Application #:
11189625
Filing Dt:
07/25/2005
Publication #:
Pub Dt:
11/24/2005
Title:
Memory device having an electron trapping layer in a high-K dielectric gate stack
16
Patent #:
Issue Dt:
04/15/2008
Application #:
11225310
Filing Dt:
09/12/2005
Title:
METHOD OF FORMING A LOW K POLYMER E-BEAM PRINTABLE MECHANICAL SUPPORT
17
Patent #:
Issue Dt:
09/11/2007
Application #:
11232074
Filing Dt:
09/21/2005
Publication #:
Pub Dt:
03/22/2007
Title:
CONTROLLING OVERSPRAY COATING IN SEMICONDUCTOR DEVICES
18
Patent #:
Issue Dt:
10/16/2007
Application #:
11247517
Filing Dt:
10/11/2005
Publication #:
Pub Dt:
10/12/2006
Title:
DEFECT ANALYSIS USING A YIELD VEHICLE
19
Patent #:
Issue Dt:
09/01/2009
Application #:
11258253
Filing Dt:
10/25/2005
Publication #:
Pub Dt:
02/16/2006
Title:
I/O AND POWER ESD PROTECTION CIRCUITS BY ENHANCING SUBSTRATE-BIAS IN DEEP-SUBMICRON CMOS PROCESS
20
Patent #:
Issue Dt:
03/27/2007
Application #:
11259965
Filing Dt:
10/26/2005
Title:
METHOD AND STRUCTURE FOR CREATING ULTRA LOW RESISTANCE DAMASCENE COPPER WIRING
21
Patent #:
Issue Dt:
11/17/2009
Application #:
11262173
Filing Dt:
10/28/2005
Title:
SHALLOW TRENCH ISOLATION STRUCTURE WITH LOW TRENCH PARASITIC CAPACITANCE
22
Patent #:
Issue Dt:
12/22/2009
Application #:
11265062
Filing Dt:
11/02/2005
Publication #:
Pub Dt:
03/16/2006
Title:
INTERDIGITADED CAPACITORS
23
Patent #:
Issue Dt:
12/13/2011
Application #:
11269275
Filing Dt:
11/08/2005
Publication #:
Pub Dt:
05/10/2007
Title:
REDUCTION OF MACRO LEVEL STRESSES IN COPPER/LOW-K WAFERS
24
Patent #:
Issue Dt:
02/24/2009
Application #:
11286546
Filing Dt:
11/23/2005
Publication #:
Pub Dt:
05/24/2007
Title:
PROGRAMMABLE NANOTUBE INTERCONNECT
25
Patent #:
Issue Dt:
12/07/2010
Application #:
11286558
Filing Dt:
11/23/2005
Publication #:
Pub Dt:
06/07/2007
Title:
CONFIGURABLE POWER SEGMENTATION USING A NANOTUBE STRUCTURE
26
Patent #:
NONE
Issue Dt:
Application #:
11314649
Filing Dt:
12/21/2005
Publication #:
Pub Dt:
05/04/2006
Title:
Variable mask field exposure
27
Patent #:
Issue Dt:
04/07/2009
Application #:
11321206
Filing Dt:
12/29/2005
Publication #:
Pub Dt:
07/05/2007
Title:
ROBUST SHALLOW TRENCH ISOLATION STRUCTURES AND A METHOD FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURES
28
Patent #:
Issue Dt:
05/04/2010
Application #:
11322103
Filing Dt:
12/29/2005
Publication #:
Pub Dt:
07/19/2007
Title:
AREA-EFFICIENT POWER SWITCHING CELL
29
Patent #:
Issue Dt:
04/22/2008
Application #:
11323400
Filing Dt:
12/29/2005
Publication #:
Pub Dt:
07/05/2007
Title:
METHOD AND APPARATUS FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRATED CIRCUIT DESIGN
30
Patent #:
Issue Dt:
09/30/2008
Application #:
11323405
Filing Dt:
12/29/2005
Publication #:
Pub Dt:
07/05/2007
Title:
METHOD AND SAMPLE FOR RADIATION MICROSCOPY INCLUDING A PARTICLE BEAM CHANNEL FORMED IN THE SAMPLE SOURCE
31
Patent #:
Issue Dt:
05/22/2007
Application #:
11337460
Filing Dt:
01/23/2006
Publication #:
Pub Dt:
06/08/2006
Title:
PLANARIZATION WITH REDUCED DISHING
32
Patent #:
Issue Dt:
10/21/2008
Application #:
11361430
Filing Dt:
02/24/2006
Publication #:
Pub Dt:
08/30/2007
Title:
THERMALLY STABLE BICMOS FABRICATION METHOD AND BIPOLAR JUNCTION TRANSISTORS FORMED ACCORDING TO THE METHOD
33
Patent #:
Issue Dt:
01/13/2009
Application #:
11368780
Filing Dt:
03/06/2006
Publication #:
Pub Dt:
10/12/2006
Title:
SELECTIVE ISOTROPIC ETCH FOR TITANIUM-BASED MATERIALS
34
Patent #:
NONE
Issue Dt:
Application #:
11381409
Filing Dt:
05/03/2006
Publication #:
Pub Dt:
08/24/2006
Title:
Adjustable Transmission Phase Shift Mask
35
Patent #:
Issue Dt:
10/16/2007
Application #:
11385156
Filing Dt:
03/21/2006
Publication #:
Pub Dt:
07/27/2006
Title:
PHASE-SHIFTING MASK AND SEMICONDUCTOR DEVICE
36
Patent #:
Issue Dt:
12/25/2007
Application #:
11389643
Filing Dt:
03/23/2006
Publication #:
Pub Dt:
07/27/2006
Title:
INCORPORATING DOPANTS TO ENHANCE THE DIELECTRIC PROPERTIES OF METAL SILICATES
37
Patent #:
NONE
Issue Dt:
Application #:
11392375
Filing Dt:
03/29/2006
Publication #:
Pub Dt:
07/27/2006
Title:
High-density inter-die interconnect structure
38
Patent #:
Issue Dt:
11/08/2011
Application #:
11397252
Filing Dt:
04/03/2006
Publication #:
Pub Dt:
10/04/2007
Title:
INTERDIGITATED MESH TO PROVIDE DISTRIBUTED, HIGH QUALITY FACTOR CAPACITIVE COUPLING
39
Patent #:
Issue Dt:
04/10/2007
Application #:
11403137
Filing Dt:
04/11/2006
Publication #:
Pub Dt:
08/17/2006
Title:
WAFER CHUCKING APPARATUS FOR SPIN PROCESSOR
40
Patent #:
NONE
Issue Dt:
Application #:
11409377
Filing Dt:
04/21/2006
Publication #:
Pub Dt:
08/24/2006
Title:
Method to improve the control of electro-polishing by use of a plating electrode in an electrolyte bath
41
Patent #:
Issue Dt:
06/02/2009
Application #:
11414902
Filing Dt:
05/01/2006
Publication #:
Pub Dt:
08/31/2006
Title:
INDUCTOR FORMED IN AN INTEGRATED CIRCUIT
42
Patent #:
Issue Dt:
07/01/2008
Application #:
11418873
Filing Dt:
05/04/2006
Publication #:
Pub Dt:
09/14/2006
Title:
DUAL LAYER BARRIER FILM TECHNIQUES TO PREVENT RESIST POISONING
43
Patent #:
Issue Dt:
06/03/2008
Application #:
11419252
Filing Dt:
05/19/2006
Publication #:
Pub Dt:
05/17/2007
Title:
A METHOD OF FORMING A SPIRAL INDUCTOR IN A SEMICONDUCTOR SUBSTRATE
44
Patent #:
Issue Dt:
08/21/2007
Application #:
11419356
Filing Dt:
05/19/2006
Publication #:
Pub Dt:
05/17/2007
Title:
A VERTICAL REPLACEMENT-GATE SILICON-ON-INSULATOR TRANSISTOR
45
Patent #:
Issue Dt:
11/11/2008
Application #:
11458270
Filing Dt:
07/18/2006
Publication #:
Pub Dt:
11/09/2006
Title:
METHOD FOR FORMING MULTIPLE DOPING LEVEL BIPOLAR JUNCTIONS TRANSISTORS
46
Patent #:
Issue Dt:
01/20/2009
Application #:
11469032
Filing Dt:
08/31/2006
Publication #:
Pub Dt:
03/06/2008
Title:
METHOD TO IMPROVE PERFORMANCE OF A BIPOLAR DEVICE USING AN AMORPHIZING IMPLANT
47
Patent #:
Issue Dt:
11/20/2007
Application #:
11473627
Filing Dt:
06/22/2006
Publication #:
Pub Dt:
10/26/2006
Title:
OPTICAL ERROR MINIMIZATION IN A SEMICONDUCTOR MANUFACTURING APPARATUS
48
Patent #:
Issue Dt:
12/16/2008
Application #:
11494221
Filing Dt:
07/27/2006
Publication #:
Pub Dt:
11/23/2006
Title:
INTEGRATED CIRCUIT WITH SUBSTANTIALLY PERPENDICULAR WIRE BONDS
49
Patent #:
Issue Dt:
08/05/2008
Application #:
11524107
Filing Dt:
09/20/2006
Publication #:
Pub Dt:
01/18/2007
Title:
APPARATUS AND METHOD OF MANUFACTURE FOR INTEGRATED CIRCUIT AND CMOS DEVICE INCLUDING EPITAXIALLY GROWN DIELECTRIC ON SILICON CARBIDE
50
Patent #:
Issue Dt:
09/18/2007
Application #:
11530550
Filing Dt:
09/11/2006
Title:
SYSTEMS AND METHODS FOR DISTRIBUTING I/O IN A SEMICONDUCTOR DEVICE
51
Patent #:
Issue Dt:
02/23/2010
Application #:
11531477
Filing Dt:
09/13/2006
Publication #:
Pub Dt:
03/13/2008
Title:
BIPOLAR DEVICE HAVING IMPROVED CAPACITANCE
52
Patent #:
Issue Dt:
05/19/2009
Application #:
11534340
Filing Dt:
09/22/2006
Publication #:
Pub Dt:
03/27/2008
Title:
LOW MUTUAL INDUCTANCE MATCHED INDUCTORS
53
Patent #:
Issue Dt:
07/03/2007
Application #:
11540056
Filing Dt:
09/29/2006
Publication #:
Pub Dt:
02/01/2007
Title:
METHOD OF ELECTRICAL TESTING OF AN INTERGRATED CIRCUIT WITH AN ELECTRICAL PROBE
54
Patent #:
Issue Dt:
02/19/2008
Application #:
11542864
Filing Dt:
10/04/2006
Publication #:
Pub Dt:
02/01/2007
Title:
PROTRUDING SPACERS FOR SELF-ALIGNED CONTACTS
55
Patent #:
Issue Dt:
10/20/2009
Application #:
11609509
Filing Dt:
12/12/2006
Publication #:
Pub Dt:
06/12/2008
Title:
METHOD AND APPARATUS FOR PERFORMING METALIZATION IN AN INTEGRATED CIRCUIT PROCESS
56
Patent #:
Issue Dt:
05/26/2009
Application #:
11641507
Filing Dt:
12/19/2006
Publication #:
Pub Dt:
05/03/2007
Title:
III-V POWER FIELD EFFECT TRANSISTORS
57
Patent #:
Issue Dt:
03/02/2010
Application #:
11649197
Filing Dt:
01/03/2007
Publication #:
Pub Dt:
12/20/2007
Title:
PROCESS FOR MAKING AN ON-CHIP VACUUM TUBE DEVICE
58
Patent #:
Issue Dt:
07/07/2009
Application #:
11673645
Filing Dt:
02/12/2007
Publication #:
Pub Dt:
08/14/2008
Title:
METHOD TO IMPROVE WRITER LEAKAGE IN A SIGE BIPOLAR DEVICE
59
Patent #:
Issue Dt:
05/04/2010
Application #:
11684674
Filing Dt:
03/12/2007
Publication #:
Pub Dt:
03/13/2008
Title:
SYSTEMS AND METHODS FOR SUPPORTING A SUBSET OF MULTIPLE INTERFACE TYPES IN A SEMICONDUCTOR DEVICE
60
Patent #:
Issue Dt:
11/25/2008
Application #:
11694021
Filing Dt:
03/30/2007
Publication #:
Pub Dt:
10/02/2008
Title:
METHOD TO REDUCE BORON PENETRATION IN A SIGE BIPOLAR DEVICE
61
Patent #:
NONE
Issue Dt:
Application #:
11695169
Filing Dt:
04/02/2007
Publication #:
Pub Dt:
07/19/2007
Title:
Planarization with reduced dishing
62
Patent #:
Issue Dt:
08/19/2008
Application #:
11733673
Filing Dt:
04/10/2007
Publication #:
Pub Dt:
08/02/2007
Title:
MULTI-STEP PROCESS FOR FORMING A BARRIER FILM FOR USE IN COPPER LAYER FORMATION
63
Patent #:
Issue Dt:
03/09/2010
Application #:
11738050
Filing Dt:
04/20/2007
Publication #:
Pub Dt:
08/16/2007
Title:
DEVICE AND METHOD TO ELIMINATE SHORTING INDUCED BY VIA TO METAL MISALIGNMENT
64
Patent #:
Issue Dt:
08/05/2008
Application #:
11748569
Filing Dt:
05/15/2007
Publication #:
Pub Dt:
09/13/2007
Title:
GUARD RING FOR IMPROVED MATCHING
65
Patent #:
Issue Dt:
02/17/2009
Application #:
11768725
Filing Dt:
06/26/2007
Publication #:
Pub Dt:
10/25/2007
Title:
MULTI-LAYER REGISTRATION AND DIMENSIONAL TEST MARK FOR SCATTEROMETRICAL MEASUREMENT
66
Patent #:
Issue Dt:
12/15/2009
Application #:
11809686
Filing Dt:
05/31/2007
Publication #:
Pub Dt:
10/04/2007
Title:
STRUCTURE AND FABRICATION METHOD FOR CAPACITORS INTEGRATIBLE WITH VERTICAL REPLACEMENT GATE TRANSISTORS
67
Patent #:
Issue Dt:
02/17/2009
Application #:
11809873
Filing Dt:
06/01/2007
Publication #:
Pub Dt:
10/11/2007
Title:
FABRICATION METHOD
68
Patent #:
Issue Dt:
06/10/2008
Application #:
11811519
Filing Dt:
06/11/2007
Publication #:
Pub Dt:
11/01/2007
Title:
INTEGRATED CIRCUIT WITH INDUCTOR HAVING HORIZONTAL MAGNETIC FLUX LINES
69
Patent #:
Issue Dt:
09/21/2010
Application #:
11821396
Filing Dt:
06/22/2007
Publication #:
Pub Dt:
11/01/2007
Title:
INTEGRATED CIRCUIT WITH METAL SILICIDE REGIONS
70
Patent #:
Issue Dt:
12/15/2009
Application #:
11827807
Filing Dt:
07/13/2007
Publication #:
Pub Dt:
11/29/2007
Title:
REAL-TIME GATE ETCH CRITICAL DIMENSION CONTROL BY OXYGEN MONITORING
71
Patent #:
Issue Dt:
08/10/2010
Application #:
11832711
Filing Dt:
08/02/2007
Publication #:
Pub Dt:
11/22/2007
Title:
CONTROLLING OVERSPRAY COATING IN SEMICONDUCTOR DEVICES
72
Patent #:
Issue Dt:
03/13/2012
Application #:
11838546
Filing Dt:
08/14/2007
Publication #:
Pub Dt:
02/28/2008
Title:
CIRCUITS AND METHODS FOR IMPROVED FET MATCHING
73
Patent #:
Issue Dt:
01/21/2014
Application #:
11906196
Filing Dt:
10/01/2007
Publication #:
Pub Dt:
02/07/2008
Title:
Method of isolation for acoustic resonator device
74
Patent #:
Issue Dt:
08/25/2009
Application #:
11927950
Filing Dt:
10/30/2007
Publication #:
Pub Dt:
03/06/2008
Title:
DUAL-GATE METAL-OXIDE-SEMICONDUCTOR DEVICE
75
Patent #:
Issue Dt:
06/22/2010
Application #:
11927978
Filing Dt:
10/30/2007
Publication #:
Pub Dt:
03/06/2008
Title:
SEMICONDUCTOR STRUCTURE FORMED USING A SACRIFICIAL STRUCTURE
76
Patent #:
Issue Dt:
07/14/2009
Application #:
11937199
Filing Dt:
11/08/2007
Publication #:
Pub Dt:
03/13/2008
Title:
VOLTAGE CONTRAST MONITOR FOR INTEGRATED CIRCUIT DEFECTS
77
Patent #:
Issue Dt:
03/02/2010
Application #:
11939482
Filing Dt:
11/13/2007
Title:
METHOD OF TREATING METAL AND METAL SALTS TO ENABLE THIN LAYER DEPOSITION IN SEMICONDUCTOR PROCESSING
78
Patent #:
Issue Dt:
06/07/2011
Application #:
11960554
Filing Dt:
12/19/2007
Publication #:
Pub Dt:
05/01/2008
Title:
SPACER-LESS TRANSISTOR INTEGRATION SCHEME FOR HIGH-K GATE DIELECTRICS AND SMALL GATE-TO-GATE SPACES APPLICABLE TO SI, SIGE AND STRAINED SILICON SCHEMES
79
Patent #:
Issue Dt:
03/03/2009
Application #:
11968693
Filing Dt:
01/03/2008
Publication #:
Pub Dt:
05/01/2008
Title:
STRUCTURE AND METHOD FOR IMPROVED HEAT CONDUCTION FOR SEMICONDUCTOR DEVICES
80
Patent #:
Issue Dt:
05/05/2009
Application #:
11968930
Filing Dt:
01/03/2008
Publication #:
Pub Dt:
05/01/2008
Title:
SYSTEM OF USING OFFSET GAGE FOR CMP POLISHING PAD ALIGNMENT AND ADJUSTMENT
81
Patent #:
Issue Dt:
04/10/2012
Application #:
11999168
Filing Dt:
12/04/2007
Publication #:
Pub Dt:
04/24/2008
Title:
METAL-OXIDE-SEMICONDUCTOR DEVICE HAVING TRENCHED DIFFUSION REGION AND METHOD OF FORMING SAME
82
Patent #:
Issue Dt:
09/01/2009
Application #:
12018849
Filing Dt:
01/24/2008
Publication #:
Pub Dt:
06/05/2008
Title:
METHOD FOR REDIRECTING VOID DIFFUSION AWAY FROM VIAS IN AN INTEGRATED CIRCUIT DESIGN
83
Patent #:
Issue Dt:
07/12/2011
Application #:
12112076
Filing Dt:
04/30/2008
Publication #:
Pub Dt:
11/05/2009
Title:
HIGH VOLTAGE TOLERANT METAL-OXIDE-SEMICONDUCTOR DEVICE
84
Patent #:
NONE
Issue Dt:
Application #:
12114589
Filing Dt:
05/02/2008
Publication #:
Pub Dt:
11/13/2008
Title:
TRANSISTOR FABRICATION METHOD
85
Patent #:
Issue Dt:
04/19/2011
Application #:
12117379
Filing Dt:
05/08/2008
Publication #:
Pub Dt:
09/04/2008
Title:
YIELD PROFILE MANIPULATOR
86
Patent #:
Issue Dt:
02/26/2013
Application #:
12140773
Filing Dt:
06/17/2008
Publication #:
Pub Dt:
12/18/2008
Title:
APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW
87
Patent #:
Issue Dt:
09/06/2011
Application #:
12156281
Filing Dt:
05/30/2008
Publication #:
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11/18/2010
Title:
ELECTRONIC PRESSURE-SENSING DEVICE
Assignor
1
Exec Dt:
04/01/2022
Assignees
1
401 N. MICHIGAN AVE.
SUITE 1630
CHICAGO, ILLINOIS 60611
2
401 N. MICHIGAN AVE.
SUITE 1630
CHICAGO, ILLINOIS 60611
3
401 N. MICHIGAN AVE.
SUITE 1630
CHICAGO, ILLINOIS 60611
Correspondence name and address
JOSHUA GAMMON
401 N. MICHIGAN AVE.
SUITE 1630
CHICAGO, IL 60611

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