Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 061108/0808 | |
| Pages: | 4 |
| | Recorded: | 09/15/2022 | | |
Attorney Dkt #: | ST-21-IND-0848US01 |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
Total properties:
1
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2024
|
Application #:
|
17945576
|
Filing Dt:
|
09/15/2022
|
Title:
|
DEBUG AND TRACE CIRCUIT IN LOCKSTEP ARCHITECTURES, ASSOCIATED METHOD, PROCESSING SYSTEM, AND APPARATUS
|
|
Assignee
|
|
|
39, CHEMIN DU CHAMP-DES-FILLES, PLAN-LES-OUATES |
GENEVA, SWITZERLAND 1228 |
|
Correspondence name and address
|
|
SLATER MATSIL, LLP
|
|
17950 PRESTON ROAD, SUITE 1000
|
|
DALLAS, TX 75252
|
Search Results as of:
05/22/2024 08:17 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|