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12/26/2006
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12/05/2001
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03/06/2003
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04/26/2005
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10/21/2002
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04/22/2004
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01/03/2006
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05/06/2004
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05/29/2007
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10/31/2002
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05/06/2004
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12/26/2006
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10285389
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10/31/2002
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05/06/2004
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Title:
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09/06/2005
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10285401
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10/31/2002
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08/19/2004
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Title:
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11/07/2006
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01/14/2003
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05/06/2004
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12/07/2004
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10413810
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04/14/2003
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01/08/2004
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12/04/2007
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05/02/2003
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11/04/2004
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04/18/2006
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12/18/2003
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09/16/2004
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02/14/2006
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05/24/2004
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10/28/2004
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12/12/2006
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06/16/2004
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12/23/2004
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02/17/2009
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03/18/2005
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06/15/2006
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04/18/2006
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08/06/2004
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01/13/2005
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09/11/2007
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11/15/2004
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05/12/2005
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12/25/2007
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08/18/2005
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11/14/2006
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03/09/2006
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11/20/2007
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11/14/2005
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03/08/2007
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04/23/2013
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07/06/2006
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11/19/2013
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01/10/2008
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03/02/2010
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07/05/2007
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10/09/2008
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08/30/2011
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12/10/2009
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06/23/2016
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Title:
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CONTAINER MANAGER
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Patent #:
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Issue Dt:
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06/13/2017
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Application #:
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14715375
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Filing Dt:
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05/18/2015
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Publication #:
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Pub Dt:
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01/14/2016
| | | | |
Title:
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PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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12/27/2016
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Application #:
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14834273
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Filing Dt:
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08/24/2015
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Publication #:
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Pub Dt:
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12/17/2015
| | | | |
Title:
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SYSTEM AND METHOD FOR RETAINING DRAM DATA WHEN REPROGRAMMING RECONFIGURABLE DEVICES WITH DRAM MEMORY CONTROLLERS INCORPORATING A DATA MAINTENANCE BLOCK COLOCATED WITH A MEMORY MODULE OR SUBSYSTEM
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Patent #:
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Issue Dt:
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08/08/2017
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Application #:
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15389650
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Filing Dt:
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12/23/2016
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Publication #:
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Pub Dt:
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04/13/2017
| | | | |
Title:
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SYSTEM AND METHOD FOR RETAINING DRAM DATA WHEN REPROGRAMMING RECONFIGURABLE DEVICES WITH DRAM MEMORY CONTROLLERS INCORPORATING A DATA MAINTENANCE BLOCK COLOCATED WITH A MEMORY MODULE OR SUBSYSTEM
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Patent #:
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Issue Dt:
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05/28/2019
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Application #:
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15985590
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Filing Dt:
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05/21/2018
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Publication #:
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Pub Dt:
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09/27/2018
| | | | |
Title:
|
PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS
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|
|
Patent #:
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|
Issue Dt:
|
05/03/2022
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Application #:
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16450987
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Filing Dt:
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06/24/2019
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Publication #:
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Pub Dt:
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10/10/2019
| | | | |
Title:
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SYSTEM AND METHOD FOR RETAINING DRAM DATA WHEN REPROGRAMMING RECONFIGUREABLE DEVICES WITH DRAM MEMORY CONTROLLERS INCORPORATING A DATA MAINTENANCE BLOCK
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|
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Patent #:
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NONE
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Issue Dt:
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Application #:
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17218128
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Filing Dt:
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03/30/2021
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Publication #:
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Pub Dt:
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09/30/2021
| | | | |
Title:
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APPLICATION LOGIC ARCHITECTURE DEFINING SEPARATE PROCESSING PLANES
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|
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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17218132
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Filing Dt:
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03/30/2021
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Publication #:
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Pub Dt:
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09/30/2021
| | | | |
Title:
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SECURE HETEROGENOUS COMPUTING PLATFORM
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|