Total properties:
80
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Patent #:
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Issue Dt:
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05/24/2011
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Application #:
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11163558
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Filing Dt:
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10/22/2005
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Publication #:
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Pub Dt:
|
04/26/2007
| | | | |
Title:
|
THIN PACKAGE SYSTEM WITH EXTERNAL TERMINALS
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Patent #:
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Issue Dt:
|
06/28/2011
|
Application #:
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11164336
|
Filing Dt:
|
11/18/2005
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Publication #:
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Pub Dt:
|
08/03/2006
| | | | |
Title:
|
SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE
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Patent #:
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|
Issue Dt:
|
01/25/2011
|
Application #:
|
11255740
|
Filing Dt:
|
10/21/2005
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Publication #:
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|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
STACKED INTEGRATED CIRCUIT AND PACKAGE SYSTEM
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Patent #:
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Issue Dt:
|
05/10/2011
|
Application #:
|
11276611
|
Filing Dt:
|
03/07/2006
|
Publication #:
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Pub Dt:
|
09/13/2007
| | | | |
Title:
|
WAFER LEVEL CHIP SCALE PACKAGE SYSTEM WITH A THERMAL DISSIPATION STRUCTURE
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Patent #:
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Issue Dt:
|
01/04/2011
|
Application #:
|
11278414
|
Filing Dt:
|
04/01/2006
|
Publication #:
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Pub Dt:
|
10/11/2007
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE BOND PATTERN
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Patent #:
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Issue Dt:
|
05/24/2011
|
Application #:
|
11307383
|
Filing Dt:
|
02/04/2006
|
Publication #:
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|
Pub Dt:
|
08/09/2007
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM INCLUDING A NON-LEADED PACKAGE
|
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Patent #:
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|
Issue Dt:
|
03/08/2011
|
Application #:
|
11464726
|
Filing Dt:
|
08/15/2006
|
Publication #:
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|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
STRUCTURE FOR BUMPED WAFER TEST
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Patent #:
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Issue Dt:
|
05/03/2011
|
Application #:
|
11466748
|
Filing Dt:
|
08/23/2006
|
Publication #:
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|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERLOCK
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Patent #:
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Issue Dt:
|
05/31/2011
|
Application #:
|
11536242
|
Filing Dt:
|
09/28/2006
|
Publication #:
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Pub Dt:
|
04/03/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PAD TO PAD BONDING
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Patent #:
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|
Issue Dt:
|
05/03/2011
|
Application #:
|
11558387
|
Filing Dt:
|
11/09/2006
|
Publication #:
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|
Pub Dt:
|
05/24/2007
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD STRUCTURES INCLUDING A DUMMY TIE BAR
|
|
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Patent #:
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|
Issue Dt:
|
04/19/2011
|
Application #:
|
11558589
|
Filing Dt:
|
11/10/2006
|
Publication #:
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|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM
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Patent #:
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Issue Dt:
|
02/08/2011
|
Application #:
|
11768640
|
Filing Dt:
|
06/26/2007
|
Publication #:
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Pub Dt:
|
01/01/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL SIDE CONNECTION
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Patent #:
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|
Issue Dt:
|
01/04/2011
|
Application #:
|
11833646
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Filing Dt:
|
08/03/2007
|
Publication #:
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Pub Dt:
|
02/07/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLDING VENTS
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Patent #:
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|
Issue Dt:
|
04/05/2011
|
Application #:
|
11833898
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Filing Dt:
|
08/03/2007
|
Publication #:
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Pub Dt:
|
02/05/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DEVICES
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|
Patent #:
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|
Issue Dt:
|
01/11/2011
|
Application #:
|
11839020
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Filing Dt:
|
08/15/2007
|
Publication #:
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|
Pub Dt:
|
11/29/2007
| | | | |
Title:
|
WIRE BONDING STRUCTURE AND METHOD THAT ELIMINATES SPECIAL WIRE BONDABLE FINISH AND REDUCES BONDING PITCH ON SUBSTRATES
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Patent #:
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Issue Dt:
|
02/22/2011
|
Application #:
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11852771
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Filing Dt:
|
09/10/2007
|
Publication #:
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|
Pub Dt:
|
03/12/2009
| | | | |
Title:
|
METHOD FOR DIRECTIONAL GRINDING ON BACKSIDE OF A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
|
01/11/2011
|
Application #:
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11854934
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Filing Dt:
|
09/13/2007
|
Publication #:
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Pub Dt:
|
03/19/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH LEADS
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Patent #:
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|
Issue Dt:
|
02/22/2011
|
Application #:
|
11858554
|
Filing Dt:
|
09/20/2007
|
Publication #:
|
|
Pub Dt:
|
03/26/2009
| | | | |
Title:
|
METHOD OF MANUFACTURING INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WARP-FREE CHIP
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Patent #:
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|
Issue Dt:
|
03/08/2011
|
Application #:
|
11861251
|
Filing Dt:
|
09/25/2007
|
Publication #:
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|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
SEMICONDUCTOR DIE WITH THROUGH-HOLE VIA ON SAW STREETS AND THROUGH-HOLE VIA IN ACTIVE AREA OF DIE
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|
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Patent #:
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Issue Dt:
|
03/29/2011
|
Application #:
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11862406
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Filing Dt:
|
09/27/2007
|
Publication #:
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|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFRAME ARRAY
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Patent #:
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Issue Dt:
|
03/29/2011
|
Application #:
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11864826
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Filing Dt:
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09/28/2007
|
Publication #:
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Pub Dt:
|
04/02/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BASE STRUCTURE DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
03/08/2011
|
Application #:
|
11952951
|
Filing Dt:
|
12/07/2007
|
Publication #:
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Pub Dt:
|
06/11/2009
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM FOR ELECTROMAGNETIC ISOLATION
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Patent #:
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Issue Dt:
|
05/24/2011
|
Application #:
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11964501
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Filing Dt:
|
12/26/2007
|
Publication #:
|
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Pub Dt:
|
07/02/2009
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD LOCKING STRUCTURE
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Patent #:
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Issue Dt:
|
03/22/2011
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Application #:
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11965621
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Filing Dt:
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12/27/2007
|
Publication #:
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Pub Dt:
|
07/02/2009
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGE WITH IMPROVED CONNECTIONS
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Patent #:
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Issue Dt:
|
02/22/2011
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Application #:
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12042903
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Filing Dt:
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03/05/2008
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Publication #:
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Pub Dt:
|
09/10/2009
| | | | |
Title:
|
SEMICONDUCTOR PACKAGE WITH STACKED SEMICONDUCTOR DIE EACH HAVING IPD AND METHOD OF REDUCING MUTUAL INDUCTIVE COUPLING BY PROVIDING SELECTABLE VERTICAL AND LATERAL SEPARATION BETWEEN IPD
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Patent #:
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Issue Dt:
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01/25/2011
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Application #:
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12045646
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Filing Dt:
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03/10/2008
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Publication #:
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Pub Dt:
|
09/10/2009
| | | | |
Title:
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INTEGRATED CIRCUIT WITH STEP MOLDED INNER STACKING MODULE PACKAGE IN PACKAGE SYSTEM
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Patent #:
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Issue Dt:
|
01/04/2011
|
Application #:
|
12050400
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Filing Dt:
|
03/18/2008
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Publication #:
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Pub Dt:
|
09/24/2009
| | | | |
Title:
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BALL GRID ARRAY PACKAGE SYSTEM
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Patent #:
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Issue Dt:
|
03/08/2011
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Application #:
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12051280
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Filing Dt:
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03/19/2008
|
Publication #:
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Pub Dt:
|
09/24/2009
| | | | |
Title:
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PACKAGE-ON-PACKAGE SYSTEM WITH INTERNAL STACKING MODULE INTERPOSER
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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12051625
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Filing Dt:
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03/19/2008
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Publication #:
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Pub Dt:
|
09/24/2009
| | | | |
Title:
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PACKAGE-ON-PACKAGE SYSTEM WITH VIA Z-INTERCONNECTIONS
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Patent #:
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Issue Dt:
|
04/05/2011
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Application #:
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12052910
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Filing Dt:
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03/21/2008
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Publication #:
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Pub Dt:
|
09/24/2009
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES
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Patent #:
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Issue Dt:
|
02/01/2011
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Application #:
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12055171
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Filing Dt:
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03/25/2008
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Publication #:
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Pub Dt:
|
10/01/2009
| | | | |
Title:
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WAFER INTEGRATED WITH PERMANENT CARRIER AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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01/18/2011
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Application #:
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12055642
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Filing Dt:
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03/26/2008
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Publication #:
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Pub Dt:
|
10/01/2009
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH RIGID LOCKING LEAD
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Patent #:
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Issue Dt:
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04/12/2011
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Application #:
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12121752
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Filing Dt:
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05/15/2008
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Publication #:
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Pub Dt:
|
05/21/2009
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULANT
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Patent #:
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Issue Dt:
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06/21/2011
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Application #:
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12126548
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Filing Dt:
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05/23/2008
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Publication #:
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Pub Dt:
|
11/26/2009
| | | | |
Title:
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WIREBONDLESS WAFER LEVEL PACKAGE WITH PLATED BUMPS AND INTERCONNECTS
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Patent #:
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Issue Dt:
|
03/15/2011
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Application #:
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12128116
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Filing Dt:
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05/28/2008
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Publication #:
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Pub Dt:
|
12/03/2009
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING HOLES IN SUBSTRATE TO INTERCONNECT TOP SHIELD AND GROUND SHIELD
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Patent #:
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Issue Dt:
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06/07/2011
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Application #:
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12146135
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Filing Dt:
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06/25/2008
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Publication #:
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Pub Dt:
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12/31/2009
| | | | |
Title:
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STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
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Patent #:
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Issue Dt:
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01/18/2011
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Application #:
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12146411
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Filing Dt:
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06/25/2008
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Publication #:
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Pub Dt:
|
12/31/2009
| | | | |
Title:
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STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTRA-STACK ENCAPSULATION
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Patent #:
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Issue Dt:
|
03/15/2011
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Application #:
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12167039
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Filing Dt:
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07/02/2008
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Publication #:
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Pub Dt:
|
01/07/2010
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF SHUNT TEST MEASUREMENT FOR PASSIVE CIRCUITS
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Patent #:
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Issue Dt:
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03/01/2011
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Application #:
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12171890
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Filing Dt:
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07/11/2008
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Publication #:
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Pub Dt:
|
01/14/2010
| | | | |
Title:
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PACKAGE STACKING SYSTEM WITH MOLD CONTAMINATION PREVENTION
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Patent #:
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Issue Dt:
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04/26/2011
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Application #:
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12185058
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Filing Dt:
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08/01/2008
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Publication #:
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Pub Dt:
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02/04/2010
| | | | |
Title:
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A METHOD FOR FORMING AN ETCHED RECESS PACKAGE ON PACKAGE SYSTEM
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Patent #:
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Issue Dt:
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01/18/2011
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Application #:
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12201896
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Filing Dt:
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08/29/2008
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Publication #:
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Pub Dt:
|
03/05/2009
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION
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Patent #:
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Issue Dt:
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01/18/2011
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Application #:
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12206383
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Filing Dt:
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09/08/2008
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Publication #:
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Pub Dt:
|
03/11/2010
| | | | |
Title:
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BALL GRID ARRAY PACKAGE STACKING SYSTEM
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Patent #:
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Issue Dt:
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03/01/2011
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Application #:
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12207986
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Filing Dt:
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09/10/2008
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Publication #:
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Pub Dt:
|
03/11/2010
| | | | |
Title:
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METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
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Patent #:
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Issue Dt:
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02/15/2011
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Application #:
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12235000
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Filing Dt:
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09/22/2008
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Publication #:
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Pub Dt:
|
03/25/2010
| | | | |
Title:
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METHOD OF FORMING A WAFER LEVEL PACKAGE WITH RDL [[BUMP]] INTERCONNECTION OVER ENCAPSULANT BETWEEN BUMP AND SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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03/22/2011
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Application #:
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12235144
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Filing Dt:
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09/22/2008
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Publication #:
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Pub Dt:
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03/25/2010
| | | | |
Title:
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SEMICONDUCTOR PACKAGE SYSTEM WITH DIE SUPPORT PAD
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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12237276
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Filing Dt:
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09/24/2008
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Publication #:
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Pub Dt:
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01/15/2009
| | | | |
Title:
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MULTICHIP MODULE PACKAGE AND FABRICATION METHOD
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Patent #:
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Issue Dt:
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01/18/2011
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Application #:
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12237291
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Filing Dt:
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09/24/2008
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Publication #:
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Pub Dt:
|
01/15/2009
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE MOLDING
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Patent #:
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Issue Dt:
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03/22/2011
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Application #:
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12238153
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Filing Dt:
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09/25/2008
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Publication #:
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Pub Dt:
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03/25/2010
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING PLANAR INTERCONNECT
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Patent #:
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Issue Dt:
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05/31/2011
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Application #:
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12325193
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Filing Dt:
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11/29/2008
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Publication #:
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Pub Dt:
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06/03/2010
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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05/31/2011
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Application #:
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12331347
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Filing Dt:
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12/09/2008
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Publication #:
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Pub Dt:
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06/10/2010
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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04/05/2011
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Application #:
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12331416
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Filing Dt:
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12/09/2008
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Publication #:
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Pub Dt:
|
06/10/2010
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED TERMINAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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05/03/2011
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Application #:
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12331698
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Filing Dt:
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12/10/2008
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Publication #:
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Pub Dt:
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06/10/2010
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING INTEGRATED PASSIVE DEVICES INTO THE PACKAGE ELECTRICALLY INTERCONNECTED USING CONDUCTIVE PILLARS
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Patent #:
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Issue Dt:
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02/08/2011
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Application #:
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12360644
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Filing Dt:
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01/27/2009
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Publication #:
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Pub Dt:
|
05/28/2009
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CARRIER AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
03/22/2011
|
Application #:
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12391807
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Filing Dt:
|
02/24/2009
|
Publication #:
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Pub Dt:
|
06/18/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER
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Patent #:
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Issue Dt:
|
06/14/2011
|
Application #:
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12398806
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Filing Dt:
|
03/05/2009
|
Publication #:
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Pub Dt:
|
07/02/2009
| | | | |
Title:
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LEADFRAME DESIGN FOR QFN PACKAGE WITH TOP TERMINAL LEADS
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Patent #:
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Issue Dt:
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06/21/2011
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Application #:
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12409489
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Filing Dt:
|
03/24/2009
|
Publication #:
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|
Pub Dt:
|
07/16/2009
| | | | |
Title:
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STACKED SEMICONDUCTOR PACKAGE ASSEMBLY HAVING HOLLOWED SUBSTRATE
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Patent #:
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Issue Dt:
|
04/12/2011
|
Application #:
|
12413302
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Filing Dt:
|
03/27/2009
|
Publication #:
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|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
04/26/2011
|
Application #:
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12433852
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Filing Dt:
|
04/30/2009
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Publication #:
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|
Pub Dt:
|
09/03/2009
| | | | |
Title:
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MULTIPACKAGE MODULE HAVING STACKED PACKAGES WITH ASYMMETRICALLY ARRANGED DIE AND MOLDING
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Patent #:
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Issue Dt:
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06/07/2011
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Application #:
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12467908
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Filing Dt:
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05/18/2009
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Publication #:
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Pub Dt:
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11/18/2010
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING A 3D INDUCTOR FROM PREFABRICATED PILLAR FRAME
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Patent #:
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Issue Dt:
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05/31/2011
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Application #:
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12472170
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Filing Dt:
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05/26/2009
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Publication #:
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Pub Dt:
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12/02/2010
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING IPD STRUCTURE USING SMOOTH CONDUCTIVE LAYER AND BOTTOM-SIDE CONDUCTIVE LAYER
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Patent #:
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Issue Dt:
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03/08/2011
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Application #:
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12472236
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Filing Dt:
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05/26/2009
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Publication #:
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Pub Dt:
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09/17/2009
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Title:
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BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
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Patent #:
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Issue Dt:
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02/15/2011
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Application #:
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12473233
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Filing Dt:
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05/27/2009
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Publication #:
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Pub Dt:
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12/24/2009
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CIRCUITRY AND POST, AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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03/08/2011
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Application #:
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12484131
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Filing Dt:
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06/12/2009
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Publication #:
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Pub Dt:
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10/08/2009
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERCONNECTION SUPPORT AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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12488089
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Filing Dt:
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06/19/2009
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Publication #:
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Pub Dt:
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12/23/2010
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INWARD AND OUTWARD INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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06/14/2011
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Application #:
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12496046
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Filing Dt:
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07/01/2009
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Publication #:
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Pub Dt:
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10/29/2009
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Title:
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THROUGH-HOLE VIA ON SAW STREETS
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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12538098
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Filing Dt:
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08/07/2009
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A TIERED SUBSTRATE PACKAGE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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04/12/2011
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Application #:
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12557481
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Filing Dt:
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09/10/2009
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Publication #:
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Pub Dt:
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03/10/2011
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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01/11/2011
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Application #:
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12562702
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Filing Dt:
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09/18/2009
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Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH THROUGH SEMICONDUCTOR VIAS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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04/05/2011
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Application #:
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12562722
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Filing Dt:
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09/18/2009
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Publication #:
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Pub Dt:
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03/24/2011
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CIRCUITRY STACKING AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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01/25/2011
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Application #:
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12571234
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Filing Dt:
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09/30/2009
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Publication #:
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Pub Dt:
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01/28/2010
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Title:
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STANDOFF HEIGHT IMPROVEMENT FOR BUMPING TECHNOLOGY USING SOLDER RESIST
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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12572568
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Filing Dt:
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10/02/2009
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Publication #:
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Pub Dt:
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01/28/2010
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING ALONG A PROFILE DISPOSED IN PERIPHERAL REGION AROUND THE DEVICE
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Patent #:
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Issue Dt:
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03/29/2011
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Application #:
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12615195
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Filing Dt:
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11/09/2009
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Publication #:
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Pub Dt:
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03/04/2010
| | | | |
Title:
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STACKABLE MULTI-CHIP PACKAGE SYSTEM WITH SUPPORT STRUCTURE
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Patent #:
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Issue Dt:
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04/12/2011
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Application #:
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12615428
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Filing Dt:
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11/10/2009
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Publication #:
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Pub Dt:
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03/04/2010
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE DEVICE USING SACRIFICIAL CARRIER
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Patent #:
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Issue Dt:
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06/14/2011
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Application #:
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12635536
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Filing Dt:
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12/10/2009
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Publication #:
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Pub Dt:
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04/08/2010
| | | | |
Title:
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BONDING TOOL FOR MOUNTING SEMICONDUCTOR CHIPS
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Patent #:
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Issue Dt:
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04/05/2011
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Application #:
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12690092
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Filing Dt:
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01/19/2010
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Publication #:
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Pub Dt:
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05/13/2010
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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|
Issue Dt:
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04/19/2011
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Application #:
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12722759
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Filing Dt:
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03/12/2010
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Title:
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INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-TIER CONDUCTIVE INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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01/11/2011
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Application #:
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12730171
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Filing Dt:
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03/23/2010
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Publication #:
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Pub Dt:
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07/15/2010
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
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Patent #:
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Issue Dt:
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04/12/2011
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Application #:
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12762602
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Filing Dt:
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04/19/2010
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Publication #:
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Pub Dt:
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08/12/2010
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING SHIELD
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|
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Patent #:
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|
Issue Dt:
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03/22/2011
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Application #:
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12767670
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Filing Dt:
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04/26/2010
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Publication #:
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Pub Dt:
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08/12/2010
| | | | |
Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE WITH FINE PITCH LEAD FINGERS
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|
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Patent #:
|
|
Issue Dt:
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03/29/2011
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Application #:
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12784434
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Filing Dt:
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05/20/2010
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Publication #:
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Pub Dt:
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09/23/2010
| | | | |
Title:
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METHOD FOR MAKING A STACKED PACKAGE SEMICONDUCTOR MODULE HAVING PACKAGES STACKED IN A CAVITY IN THE MODULE SUBSTRATE
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