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Reel/Frame:065015/0917   Pages: 17
Recorded: 09/22/2023
Attorney Dkt #:392739-00007
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 064783 FRAME 0896. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE CHANGE OF NAME.
Total properties: 80
1
Patent #:
7947535
Issue Dt:
05/24/2011
Application #:
11163558
Filing Dt:
10/22/2005
Publication #:
US20070090495
Pub Dt:
04/26/2007
Title:
THIN PACKAGE SYSTEM WITH EXTERNAL TERMINALS
2
Patent #:
7968371
Issue Dt:
06/28/2011
Application #:
11164336
Filing Dt:
11/18/2005
Publication #:
US20060170092
Pub Dt:
08/03/2006
Title:
SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE
3
Patent #:
7875966
Issue Dt:
01/25/2011
Application #:
11255740
Filing Dt:
10/21/2005
Publication #:
US20060180911
Pub Dt:
08/17/2006
Title:
STACKED INTEGRATED CIRCUIT AND PACKAGE SYSTEM
4
Patent #:
7939368
Issue Dt:
05/10/2011
Application #:
11276611
Filing Dt:
03/07/2006
Publication #:
US20070212812
Pub Dt:
09/13/2007
Title:
WAFER LEVEL CHIP SCALE PACKAGE SYSTEM WITH A THERMAL DISSIPATION STRUCTURE
5
Patent #:
7863737
Issue Dt:
01/04/2011
Application #:
11278414
Filing Dt:
04/01/2006
Publication #:
US20070235869
Pub Dt:
10/11/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE BOND PATTERN
6
Patent #:
7947534
Issue Dt:
05/24/2011
Application #:
11307383
Filing Dt:
02/04/2006
Publication #:
US20070182024
Pub Dt:
08/09/2007
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM INCLUDING A NON-LEADED PACKAGE
7
Patent #:
7901956
Issue Dt:
03/08/2011
Application #:
11464726
Filing Dt:
08/15/2006
Publication #:
US20080042275
Pub Dt:
02/21/2008
Title:
STRUCTURE FOR BUMPED WAFER TEST
8
Patent #:
7936055
Issue Dt:
05/03/2011
Application #:
11466748
Filing Dt:
08/23/2006
Publication #:
US20080054421
Pub Dt:
03/06/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERLOCK
9
Patent #:
7952209
Issue Dt:
05/31/2011
Application #:
11536242
Filing Dt:
09/28/2006
Publication #:
US20080079173
Pub Dt:
04/03/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PAD TO PAD BONDING
10
Patent #:
7936053
Issue Dt:
05/03/2011
Application #:
11558387
Filing Dt:
11/09/2006
Publication #:
US20070114645
Pub Dt:
05/24/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD STRUCTURES INCLUDING A DUMMY TIE BAR
11
Patent #:
7928540
Issue Dt:
04/19/2011
Application #:
11558589
Filing Dt:
11/10/2006
Publication #:
US20080111215
Pub Dt:
05/15/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
12
Patent #:
7884457
Issue Dt:
02/08/2011
Application #:
11768640
Filing Dt:
06/26/2007
Publication #:
US20090001612
Pub Dt:
01/01/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DUAL SIDE CONNECTION
13
Patent #:
7863761
Issue Dt:
01/04/2011
Application #:
11833646
Filing Dt:
08/03/2007
Publication #:
US20080029873
Pub Dt:
02/07/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOLDING VENTS
14
Patent #:
7919848
Issue Dt:
04/05/2011
Application #:
11833898
Filing Dt:
08/03/2007
Publication #:
US20090032918
Pub Dt:
02/05/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE DEVICES
15
Patent #:
7868468
Issue Dt:
01/11/2011
Application #:
11839020
Filing Dt:
08/15/2007
Publication #:
US20070273043
Pub Dt:
11/29/2007
Title:
WIRE BONDING STRUCTURE AND METHOD THAT ELIMINATES SPECIAL WIRE BONDABLE FINISH AND REDUCES BONDING PITCH ON SUBSTRATES
16
Patent #:
7892072
Issue Dt:
02/22/2011
Application #:
11852771
Filing Dt:
09/10/2007
Publication #:
US20090068933
Pub Dt:
03/12/2009
Title:
METHOD FOR DIRECTIONAL GRINDING ON BACKSIDE OF A SEMICONDUCTOR WAFER
17
Patent #:
7868471
Issue Dt:
01/11/2011
Application #:
11854934
Filing Dt:
09/13/2007
Publication #:
US20090072363
Pub Dt:
03/19/2009
Title:
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH LEADS
18
Patent #:
7892894
Issue Dt:
02/22/2011
Application #:
11858554
Filing Dt:
09/20/2007
Publication #:
US20090079049
Pub Dt:
03/26/2009
Title:
METHOD OF MANUFACTURING INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WARP-FREE CHIP
19
Patent #:
7902638
Issue Dt:
03/08/2011
Application #:
11861251
Filing Dt:
09/25/2007
Publication #:
US20080272465
Pub Dt:
11/06/2008
Title:
SEMICONDUCTOR DIE WITH THROUGH-HOLE VIA ON SAW STREETS AND THROUGH-HOLE VIA IN ACTIVE AREA OF DIE
20
Patent #:
7915716
Issue Dt:
03/29/2011
Application #:
11862406
Filing Dt:
09/27/2007
Publication #:
US20090085177
Pub Dt:
04/02/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEADFRAME ARRAY
21
Patent #:
7915724
Issue Dt:
03/29/2011
Application #:
11864826
Filing Dt:
09/28/2007
Publication #:
US20090085178
Pub Dt:
04/02/2009
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BASE STRUCTURE DEVICE
22
Patent #:
7902644
Issue Dt:
03/08/2011
Application #:
11952951
Filing Dt:
12/07/2007
Publication #:
US20090146268
Pub Dt:
06/11/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR ELECTROMAGNETIC ISOLATION
23
Patent #:
7948066
Issue Dt:
05/24/2011
Application #:
11964501
Filing Dt:
12/26/2007
Publication #:
US20090166823
Pub Dt:
07/02/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD LOCKING STRUCTURE
24
Patent #:
7911040
Issue Dt:
03/22/2011
Application #:
11965621
Filing Dt:
12/27/2007
Publication #:
US20090166885
Pub Dt:
07/02/2009
Title:
INTEGRATED CIRCUIT PACKAGE WITH IMPROVED CONNECTIONS
25
Patent #:
7892858
Issue Dt:
02/22/2011
Application #:
12042903
Filing Dt:
03/05/2008
Publication #:
US20090224361
Pub Dt:
09/10/2009
Title:
SEMICONDUCTOR PACKAGE WITH STACKED SEMICONDUCTOR DIE EACH HAVING IPD AND METHOD OF REDUCING MUTUAL INDUCTIVE COUPLING BY PROVIDING SELECTABLE VERTICAL AND LATERAL SEPARATION BETWEEN IPD
26
Patent #:
7875967
Issue Dt:
01/25/2011
Application #:
12045646
Filing Dt:
03/10/2008
Publication #:
US20090224390
Pub Dt:
09/10/2009
Title:
INTEGRATED CIRCUIT WITH STEP MOLDED INNER STACKING MODULE PACKAGE IN PACKAGE SYSTEM
27
Patent #:
7863732
Issue Dt:
01/04/2011
Application #:
12050400
Filing Dt:
03/18/2008
Publication #:
US20090236733
Pub Dt:
09/24/2009
Title:
BALL GRID ARRAY PACKAGE SYSTEM
28
Patent #:
7901987
Issue Dt:
03/08/2011
Application #:
12051280
Filing Dt:
03/19/2008
Publication #:
US20090236718
Pub Dt:
09/24/2009
Title:
PACKAGE-ON-PACKAGE SYSTEM WITH INTERNAL STACKING MODULE INTERPOSER
29
Patent #:
7863755
Issue Dt:
01/04/2011
Application #:
12051625
Filing Dt:
03/19/2008
Publication #:
US20090236752
Pub Dt:
09/24/2009
Title:
PACKAGE-ON-PACKAGE SYSTEM WITH VIA Z-INTERCONNECTIONS
30
Patent #:
7919871
Issue Dt:
04/05/2011
Application #:
12052910
Filing Dt:
03/21/2008
Publication #:
US20090236753
Pub Dt:
09/24/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES
31
Patent #:
7880293
Issue Dt:
02/01/2011
Application #:
12055171
Filing Dt:
03/25/2008
Publication #:
US20090243083
Pub Dt:
10/01/2009
Title:
WAFER INTEGRATED WITH PERMANENT CARRIER AND METHOD THEREFOR
32
Patent #:
7872345
Issue Dt:
01/18/2011
Application #:
12055642
Filing Dt:
03/26/2008
Publication #:
US20090243077
Pub Dt:
10/01/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH RIGID LOCKING LEAD
33
Patent #:
7923846
Issue Dt:
04/12/2011
Application #:
12121752
Filing Dt:
05/15/2008
Publication #:
US20090127680
Pub Dt:
05/21/2009
Title:
INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULANT
34
Patent #:
7964450
Issue Dt:
06/21/2011
Application #:
12126548
Filing Dt:
05/23/2008
Publication #:
US20090289356
Pub Dt:
11/26/2009
Title:
WIREBONDLESS WAFER LEVEL PACKAGE WITH PLATED BUMPS AND INTERCONNECTS
35
Patent #:
7906371
Issue Dt:
03/15/2011
Application #:
12128116
Filing Dt:
05/28/2008
Publication #:
US20090294928
Pub Dt:
12/03/2009
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING HOLES IN SUBSTRATE TO INTERCONNECT TOP SHIELD AND GROUND SHIELD
36
Patent #:
7956449
Issue Dt:
06/07/2011
Application #:
12146135
Filing Dt:
06/25/2008
Publication #:
US20090321907
Pub Dt:
12/31/2009
Title:
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM
37
Patent #:
7871861
Issue Dt:
01/18/2011
Application #:
12146411
Filing Dt:
06/25/2008
Publication #:
US20090321908
Pub Dt:
12/31/2009
Title:
STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTRA-STACK ENCAPSULATION
38
Patent #:
7906839
Issue Dt:
03/15/2011
Application #:
12167039
Filing Dt:
07/02/2008
Publication #:
US20100001268
Pub Dt:
01/07/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF SHUNT TEST MEASUREMENT FOR PASSIVE CIRCUITS
39
Patent #:
7898072
Issue Dt:
03/01/2011
Application #:
12171890
Filing Dt:
07/11/2008
Publication #:
US20100007000
Pub Dt:
01/14/2010
Title:
PACKAGE STACKING SYSTEM WITH MOLD CONTAMINATION PREVENTION
40
Patent #:
7932130
Issue Dt:
04/26/2011
Application #:
12185058
Filing Dt:
08/01/2008
Publication #:
US20100025830
Pub Dt:
02/04/2010
Title:
A METHOD FOR FORMING AN ETCHED RECESS PACKAGE ON PACKAGE SYSTEM
41
Patent #:
7872340
Issue Dt:
01/18/2011
Application #:
12201896
Filing Dt:
08/29/2008
Publication #:
US20090057864
Pub Dt:
03/05/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION
42
Patent #:
7871862
Issue Dt:
01/18/2011
Application #:
12206383
Filing Dt:
09/08/2008
Publication #:
US20100059873
Pub Dt:
03/11/2010
Title:
BALL GRID ARRAY PACKAGE STACKING SYSTEM
43
Patent #:
7897502
Issue Dt:
03/01/2011
Application #:
12207986
Filing Dt:
09/10/2008
Publication #:
US20100059866
Pub Dt:
03/11/2010
Title:
METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECTS ON RECESSED AND RAISED BOND FINGERS
44
Patent #:
7888181
Issue Dt:
02/15/2011
Application #:
12235000
Filing Dt:
09/22/2008
Publication #:
US20100072618
Pub Dt:
03/25/2010
Title:
METHOD OF FORMING A WAFER LEVEL PACKAGE WITH RDL [[BUMP]] INTERCONNECTION OVER ENCAPSULANT BETWEEN BUMP AND SEMICONDUCTOR DIE
45
Patent #:
7911067
Issue Dt:
03/22/2011
Application #:
12235144
Filing Dt:
09/22/2008
Publication #:
US20100072589
Pub Dt:
03/25/2010
Title:
SEMICONDUCTOR PACKAGE SYSTEM WITH DIE SUPPORT PAD
46
Patent #:
7928564
Issue Dt:
04/19/2011
Application #:
12237276
Filing Dt:
09/24/2008
Publication #:
US20090014866
Pub Dt:
01/15/2009
Title:
MULTICHIP MODULE PACKAGE AND FABRICATION METHOD
47
Patent #:
7871863
Issue Dt:
01/18/2011
Application #:
12237291
Filing Dt:
09/24/2008
Publication #:
US20090014849
Pub Dt:
01/15/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MULTIPLE MOLDING
48
Patent #:
7911070
Issue Dt:
03/22/2011
Application #:
12238153
Filing Dt:
09/25/2008
Publication #:
US20100072596
Pub Dt:
03/25/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING PLANAR INTERCONNECT
49
Patent #:
7951643
Issue Dt:
05/31/2011
Application #:
12325193
Filing Dt:
11/29/2008
Publication #:
US20100133665
Pub Dt:
06/03/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME AND METHOD OF MANUFACTURE THEREOF
50
Patent #:
7952176
Issue Dt:
05/31/2011
Application #:
12331347
Filing Dt:
12/09/2008
Publication #:
US20100140813
Pub Dt:
06/10/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
51
Patent #:
7919850
Issue Dt:
04/05/2011
Application #:
12331416
Filing Dt:
12/09/2008
Publication #:
US20100140789
Pub Dt:
06/10/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EXPOSED TERMINAL INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
52
Patent #:
7935570
Issue Dt:
05/03/2011
Application #:
12331698
Filing Dt:
12/10/2008
Publication #:
US20100140736
Pub Dt:
06/10/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING INTEGRATED PASSIVE DEVICES INTO THE PACKAGE ELECTRICALLY INTERCONNECTED USING CONDUCTIVE PILLARS
53
Patent #:
7884460
Issue Dt:
02/08/2011
Application #:
12360644
Filing Dt:
01/27/2009
Publication #:
US20090134509
Pub Dt:
05/28/2009
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CARRIER AND METHOD OF MANUFACTURE THEREOF
54
Patent #:
7911046
Issue Dt:
03/22/2011
Application #:
12391807
Filing Dt:
02/24/2009
Publication #:
US20090152704
Pub Dt:
06/18/2009
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER
55
Patent #:
7960815
Issue Dt:
06/14/2011
Application #:
12398806
Filing Dt:
03/05/2009
Publication #:
US20090166821
Pub Dt:
07/02/2009
Title:
LEADFRAME DESIGN FOR QFN PACKAGE WITH TOP TERMINAL LEADS
56
Patent #:
7964952
Issue Dt:
06/21/2011
Application #:
12409489
Filing Dt:
03/24/2009
Publication #:
US20090179319
Pub Dt:
07/16/2009
Title:
STACKED SEMICONDUCTOR PACKAGE ASSEMBLY HAVING HOLLOWED SUBSTRATE
57
Patent #:
7923290
Issue Dt:
04/12/2011
Application #:
12413302
Filing Dt:
03/27/2009
Publication #:
US20100244221
Pub Dt:
09/30/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF
58
Patent #:
7932593
Issue Dt:
04/26/2011
Application #:
12433852
Filing Dt:
04/30/2009
Publication #:
US20090218675
Pub Dt:
09/03/2009
Title:
MULTIPACKAGE MODULE HAVING STACKED PACKAGES WITH ASYMMETRICALLY ARRANGED DIE AND MOLDING
59
Patent #:
7955942
Issue Dt:
06/07/2011
Application #:
12467908
Filing Dt:
05/18/2009
Publication #:
US20100289126
Pub Dt:
11/18/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A 3D INDUCTOR FROM PREFABRICATED PILLAR FRAME
60
Patent #:
7951663
Issue Dt:
05/31/2011
Application #:
12472170
Filing Dt:
05/26/2009
Publication #:
US20100301450
Pub Dt:
12/02/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING IPD STRUCTURE USING SMOOTH CONDUCTIVE LAYER AND BOTTOM-SIDE CONDUCTIVE LAYER
61
Patent #:
7901983
Issue Dt:
03/08/2011
Application #:
12472236
Filing Dt:
05/26/2009
Publication #:
US20090230552
Pub Dt:
09/17/2009
Title:
BUMP-ON-LEAD FLIP CHIP INTERCONNECTION
62
Patent #:
7888184
Issue Dt:
02/15/2011
Application #:
12473233
Filing Dt:
05/27/2009
Publication #:
US20090315170
Pub Dt:
12/24/2009
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CIRCUITRY AND POST, AND METHOD OF MANUFACTURE THEREOF
63
Patent #:
7901996
Issue Dt:
03/08/2011
Application #:
12484131
Filing Dt:
06/12/2009
Publication #:
US20090250798
Pub Dt:
10/08/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERCONNECTION SUPPORT AND METHOD OF MANUFACTURE THEREOF
64
Patent #:
7927917
Issue Dt:
04/19/2011
Application #:
12488089
Filing Dt:
06/19/2009
Publication #:
US20100320582
Pub Dt:
12/23/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INWARD AND OUTWARD INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
65
Patent #:
7960841
Issue Dt:
06/14/2011
Application #:
12496046
Filing Dt:
07/01/2009
Publication #:
US20090267236
Pub Dt:
10/29/2009
Title:
THROUGH-HOLE VIA ON SAW STREETS
66
Patent #:
7863735
Issue Dt:
01/04/2011
Application #:
12538098
Filing Dt:
08/07/2009
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A TIERED SUBSTRATE PACKAGE AND METHOD OF MANUFACTURE THEREOF
67
Patent #:
7923304
Issue Dt:
04/12/2011
Application #:
12557481
Filing Dt:
09/10/2009
Publication #:
US20110057308
Pub Dt:
03/10/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF
68
Patent #:
7867821
Issue Dt:
01/11/2011
Application #:
12562702
Filing Dt:
09/18/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH THROUGH SEMICONDUCTOR VIAS AND METHOD OF MANUFACTURE THEREOF
69
Patent #:
7919360
Issue Dt:
04/05/2011
Application #:
12562722
Filing Dt:
09/18/2009
Publication #:
US20110068447
Pub Dt:
03/24/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CIRCUITRY STACKING AND METHOD OF MANUFACTURE THEREOF
70
Patent #:
7875495
Issue Dt:
01/25/2011
Application #:
12571234
Filing Dt:
09/30/2009
Publication #:
US20100022050
Pub Dt:
01/28/2010
Title:
STANDOFF HEIGHT IMPROVEMENT FOR BUMPING TECHNOLOGY USING SOLDER RESIST
71
Patent #:
7880275
Issue Dt:
02/01/2011
Application #:
12572568
Filing Dt:
10/02/2009
Publication #:
US20100019359
Pub Dt:
01/28/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING ALONG A PROFILE DISPOSED IN PERIPHERAL REGION AROUND THE DEVICE
72
Patent #:
7915738
Issue Dt:
03/29/2011
Application #:
12615195
Filing Dt:
11/09/2009
Publication #:
US20100052117
Pub Dt:
03/04/2010
Title:
STACKABLE MULTI-CHIP PACKAGE SYSTEM WITH SUPPORT STRUCTURE
73
Patent #:
7923295
Issue Dt:
04/12/2011
Application #:
12615428
Filing Dt:
11/10/2009
Publication #:
US20100052135
Pub Dt:
03/04/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE DEVICE USING SACRIFICIAL CARRIER
74
Patent #:
7958628
Issue Dt:
06/14/2011
Application #:
12635536
Filing Dt:
12/10/2009
Publication #:
US20100083494
Pub Dt:
04/08/2010
Title:
BONDING TOOL FOR MOUNTING SEMICONDUCTOR CHIPS
75
Patent #:
7919838
Issue Dt:
04/05/2011
Application #:
12690092
Filing Dt:
01/19/2010
Publication #:
US20100117205
Pub Dt:
05/13/2010
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATION LOCK AND METHOD OF MANUFACTURE THEREOF
76
Patent #:
7928552
Issue Dt:
04/19/2011
Application #:
12722759
Filing Dt:
03/12/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-TIER CONDUCTIVE INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF
77
Patent #:
7868434
Issue Dt:
01/11/2011
Application #:
12730171
Filing Dt:
03/23/2010
Publication #:
US20100176497
Pub Dt:
07/15/2010
Title:
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE STACKING SYSTEM
78
Patent #:
7923822
Issue Dt:
04/12/2011
Application #:
12762602
Filing Dt:
04/19/2010
Publication #:
US20100200967
Pub Dt:
08/12/2010
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING SHIELD
79
Patent #:
7909233
Issue Dt:
03/22/2011
Application #:
12767670
Filing Dt:
04/26/2010
Publication #:
US20100203683
Pub Dt:
08/12/2010
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE WITH FINE PITCH LEAD FINGERS
80
Patent #:
7915084
Issue Dt:
03/29/2011
Application #:
12784434
Filing Dt:
05/20/2010
Publication #:
US20100240175
Pub Dt:
09/23/2010
Title:
METHOD FOR MAKING A STACKED PACKAGE SEMICONDUCTOR MODULE HAVING PACKAGES STACKED IN A CAVITY IN THE MODULE SUBSTRATE
Assignor
1
STATS CHIPPAC LTD.
Exec Dt:
03/29/2016
Assignee
1
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23
SINGAPORE, SINGAPORE
Correspondence name and address
KATTEN MUCHIN ROSENMAN LLP
1919 PENNSYLVANIA AVE., N.W. - SUITE 800
WASHINGTON, DC 20006

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