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Reel/Frame:065239/0786   Pages: 12
Recorded: 08/31/2023
Attorney Dkt #:392739-00007
Conveyance: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON THE COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0244. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME.
Total properties: 76
1
Patent #:
8399968
Issue Dt:
03/19/2013
Application #:
11164335
Filing Dt:
11/18/2005
Publication #:
US20070114650
Pub Dt:
05/24/2007
Title:
NON-LEADED INTEGRATED CIRCUIT PACKAGE SYSTEM
2
Patent #:
8367465
Issue Dt:
02/05/2013
Application #:
11276942
Filing Dt:
03/17/2006
Publication #:
US20070216006
Pub Dt:
09/20/2007
Title:
INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM
3
Patent #:
8395254
Issue Dt:
03/12/2013
Application #:
11278008
Filing Dt:
03/30/2006
Publication #:
US20070235859
Pub Dt:
10/11/2007
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEATSPREADER
4
Patent #:
8410594
Issue Dt:
04/02/2013
Application #:
11330930
Filing Dt:
01/11/2006
Publication #:
US20070158858
Pub Dt:
07/12/2007
Title:
INTER-STACKING MODULE SYSTEM
5
Patent #:
8395251
Issue Dt:
03/12/2013
Application #:
11382983
Filing Dt:
05/12/2006
Publication #:
US20070108568
Pub Dt:
05/17/2007
Title:
INTEGRATED CIRCUIT PACKAGE TO PACKAGE STACKING SYSTEM
6
Patent #:
8395053
Issue Dt:
03/12/2013
Application #:
11769296
Filing Dt:
06/27/2007
Publication #:
US20090004504
Pub Dt:
01/01/2009
Title:
CIRCUIT SYSTEM WITH CIRCUIT ELEMENT AND REFERENCE PLANE
7
Patent #:
8409970
Issue Dt:
04/02/2013
Application #:
11949255
Filing Dt:
12/03/2007
Publication #:
US20090140421
Pub Dt:
06/04/2009
Title:
SEMICONDUCTOR DEVICE AND METHOD OF MAKING INTEGRATED PASSIVE DEVICES
8
Patent #:
8409920
Issue Dt:
04/02/2013
Application #:
12057360
Filing Dt:
03/27/2008
Publication #:
US20080258289
Pub Dt:
10/23/2008
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR PACKAGE STACKING AND METHOD OF MANUFACTURE THEREFOR
9
Patent #:
8410596
Issue Dt:
04/02/2013
Application #:
12059077
Filing Dt:
03/31/2008
Publication #:
US20080179733
Pub Dt:
07/31/2008
Title:
SEMICONDUCTOR MULTI-PACKAGE MODULE INCLUDING TAPE SUBSTRATE LAND GRID ARRAY PACKAGE STACKED OVER BALL GRID ARRAY PACKAGE
10
Patent #:
8354742
Issue Dt:
01/15/2013
Application #:
12060115
Filing Dt:
03/31/2008
Publication #:
US20090243064
Pub Dt:
10/01/2009
Title:
METHOD AND APPARATUS FOR A PACKAGE HAVING MULTIPLE STACKED DIE
11
Patent #:
8362601
Issue Dt:
01/29/2013
Application #:
12328764
Filing Dt:
12/04/2008
Publication #:
US20100140764
Pub Dt:
06/10/2010
Title:
WIRE-ON-LEAD PACKAGE SYSTEM HAVING LEADFINGERS POSITIONED BETWEEN PADDLE EXTENSIONS AND METHOD OF MANUFACTURE THEREOF
12
Patent #:
8354304
Issue Dt:
01/15/2013
Application #:
12329430
Filing Dt:
12/05/2008
Publication #:
US20100144101
Pub Dt:
06/10/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS EMBEDDED IN PHOTOSENSITIVE ENCAPSULANT
13
Patent #:
8406004
Issue Dt:
03/26/2013
Application #:
12331341
Filing Dt:
12/09/2008
Publication #:
US20100142174
Pub Dt:
06/10/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
14
Patent #:
8405197
Issue Dt:
03/26/2013
Application #:
12410983
Filing Dt:
03/25/2009
Publication #:
US20100244217
Pub Dt:
09/30/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED CONFIGURATION AND METHOD OF MANUFACTURE THEREOF
15
Patent #:
8405228
Issue Dt:
03/26/2013
Application #:
12411154
Filing Dt:
03/25/2009
Publication #:
US20100244277
Pub Dt:
09/30/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE UNDERFILL AND METHOD OF MANUFACTURE THEREOF
16
Patent #:
8378383
Issue Dt:
02/19/2013
Application #:
12411310
Filing Dt:
03/25/2009
Publication #:
US20100244208
Pub Dt:
09/30/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SHIELDING LAYER BETWEEN STACKED SEMICONDUCTOR DIE
17
Patent #:
8415204
Issue Dt:
04/09/2013
Application #:
12412315
Filing Dt:
03/26/2009
Publication #:
US20100244236
Pub Dt:
09/30/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SPREADER AND METHOD OF MANUFACTURE THEREOF
18
Patent #:
8367470
Issue Dt:
02/05/2013
Application #:
12537824
Filing Dt:
08/07/2009
Publication #:
US20110031634
Pub Dt:
02/10/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CAVITY IN BUILD-UP INTERCONNECT STRUCTURE FOR SHORT SIGNAL PATH BETWEEN DIE
19
Patent #:
8410587
Issue Dt:
04/02/2013
Application #:
12544578
Filing Dt:
08/20/2009
Publication #:
US20090309198
Pub Dt:
12/17/2009
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM
20
Patent #:
8358179
Issue Dt:
01/22/2013
Application #:
12557382
Filing Dt:
09/10/2009
Publication #:
US20110057742
Pub Dt:
03/10/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DIRECTIONAL RF COUPLER WITH IPD FOR ADDITIONAL RF SIGNAL PROCESSING
21
Patent #:
8390110
Issue Dt:
03/05/2013
Application #:
12582582
Filing Dt:
10/20/2009
Publication #:
US20110089554
Pub Dt:
04/21/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CAVITY AND METHOD OF MANUFACTURE THEREOF
22
Patent #:
8404518
Issue Dt:
03/26/2013
Application #:
12636779
Filing Dt:
12/13/2009
Publication #:
US20110140258
Pub Dt:
06/16/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
23
Patent #:
8390108
Issue Dt:
03/05/2013
Application #:
12639984
Filing Dt:
12/16/2009
Publication #:
US20110140259
Pub Dt:
06/16/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKING INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
24
Patent #:
8368187
Issue Dt:
02/05/2013
Application #:
12699431
Filing Dt:
02/03/2010
Publication #:
US20110186973
Pub Dt:
08/04/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING AIR GAP ADJACENT TO STRESS SENSITIVE REGION OF THE DIE
25
Patent #:
8409926
Issue Dt:
04/02/2013
Application #:
12720057
Filing Dt:
03/09/2010
Publication #:
US20110221041
Pub Dt:
09/15/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER AROUND SEMICONDUCTOR DIE
26
Patent #:
8420508
Issue Dt:
04/16/2013
Application #:
12726342
Filing Dt:
03/17/2010
Publication #:
US20110227211
Pub Dt:
09/22/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BUMP CONTACT ON PACKAGE LEADS AND METHOD OF MANUFACTURE THEREOF
27
Patent #:
8378476
Issue Dt:
02/19/2013
Application #:
12731870
Filing Dt:
03/25/2010
Publication #:
US20110233747
Pub Dt:
09/29/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKING OPTION AND METHOD OF MANUFACTURE THEREOF
28
Patent #:
8367467
Issue Dt:
02/05/2013
Application #:
12764805
Filing Dt:
04/21/2010
Publication #:
US20110260316
Pub Dt:
10/27/2011
Title:
SEMICONDUCTOR METHOD OF FORMING BUMP ON SUBSTRATE TO PREVENT ELK ILD DELAMINATION DURING REFLOW PROCESS
29
Patent #:
8399300
Issue Dt:
03/19/2013
Application #:
12768177
Filing Dt:
04/27/2010
Publication #:
US20110260338
Pub Dt:
10/27/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADJACENT CHANNEL AND DAM MATERIAL AROUND DIE ATTACH AREA OF SUBSTRATE TO CONTROL OUTWARD FLOW OF UNDERFILL MATERIAL
30
Patent #:
8357564
Issue Dt:
01/22/2013
Application #:
12781751
Filing Dt:
05/17/2010
Publication #:
US20110278707
Pub Dt:
11/17/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED MULTI-DIE LEADFRAME FOR ELECTRICAL INTERCONNECT OF STACKED SEMICONDUCTOR DIE
31
Patent #:
8349658
Issue Dt:
01/08/2013
Application #:
12787973
Filing Dt:
05/26/2010
Publication #:
US20110291249
Pub Dt:
12/01/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE POSTS AND HEAT SINK OVER SEMICONDUCTOR DIE USING LEADFRAME
32
Patent #:
8409978
Issue Dt:
04/02/2013
Application #:
12822504
Filing Dt:
06/24/2010
Publication #:
US20110316132
Pub Dt:
12/29/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICALLY OFFSET BOND ON TRACE INTERCONNECT STRUCTURE ON LEADFRAME
33
Patent #:
8389330
Issue Dt:
03/05/2013
Application #:
12822659
Filing Dt:
06/24/2010
Publication #:
US20110316133
Pub Dt:
12/29/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE STAND-OFF AND METHOD OF MANUFACTURE THEREOF
34
Patent #:
8409921
Issue Dt:
04/02/2013
Application #:
12834176
Filing Dt:
07/12/2010
Publication #:
US20100279504
Pub Dt:
11/04/2010
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HONEYCOMB MOLDING
35
Patent #:
8399991
Issue Dt:
03/19/2013
Application #:
12858602
Filing Dt:
08/18/2010
Publication #:
US20100308459
Pub Dt:
12/09/2010
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THROUGH HOLE VIAS IN DIE EXTENSION REGION AROUND PERIPHERY OF DIE
36
Patent #:
8383457
Issue Dt:
02/26/2013
Application #:
12875981
Filing Dt:
09/03/2010
Publication #:
US20120056329
Pub Dt:
03/08/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME OVER SEMICONDUCTOR DIE TO PROVIDE VERTICAL INTERCONNECT
37
Patent #:
8409918
Issue Dt:
04/02/2013
Application #:
12875998
Filing Dt:
09/03/2010
Publication #:
US20120056334
Pub Dt:
03/08/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SUBSTRATE TO REDUCE WARPAGE DURING DIE MOUNTING
38
Patent #:
8354297
Issue Dt:
01/15/2013
Application #:
12876013
Filing Dt:
09/03/2010
Publication #:
US20120056316
Pub Dt:
03/08/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DIFFERENT HEIGHT CONDUCTIVE PILLARS TO ELECTRICALLY INTERCONNECT STACKED LATERALLY OFFSET SEMICONDUCTOR DIE
39
Patent #:
8378477
Issue Dt:
02/19/2013
Application #:
12882067
Filing Dt:
09/14/2010
Publication #:
US20120061855
Pub Dt:
03/15/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
40
Patent #:
8409922
Issue Dt:
04/02/2013
Application #:
12882110
Filing Dt:
09/14/2010
Publication #:
US20120061814
Pub Dt:
03/15/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING LEADFRAME INTERPOSER OVER SEMICONDUCTOR DIE AND TSV SUBSTRATE FOR VERTICAL ELECTRICAL INTERCONNECT
41
Patent #:
8404524
Issue Dt:
03/26/2013
Application #:
12884073
Filing Dt:
09/16/2010
Publication #:
US20120068318
Pub Dt:
03/22/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADDLE MOLDING AND METHOD OF MANUFACTURE THEREOF
42
Patent #:
8399305
Issue Dt:
03/19/2013
Application #:
12885831
Filing Dt:
09/20/2010
Publication #:
US20120068353
Pub Dt:
03/22/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING DAM MATERIAL WITH OPENINGS AROUND SEMICONDUCTOR DIE FOR MOLD UNDERFILL USING DISPENSER AND VACUUM ASSIST
43
Patent #:
8349735
Issue Dt:
01/08/2013
Application #:
12887811
Filing Dt:
09/22/2010
Publication #:
US20120068313
Pub Dt:
03/22/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE TSV WITH INSULATING ANNULAR RING
44
Patent #:
8368188
Issue Dt:
02/05/2013
Application #:
12912728
Filing Dt:
10/26/2010
Publication #:
US20110037152
Pub Dt:
02/17/2011
Title:
DROP-MOLD CONFORMABLE MATERIAL AS AN ENCAPSULATION FOR AN INTEGRATED CIRCUIT PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF
45
Patent #:
8378502
Issue Dt:
02/19/2013
Application #:
12912730
Filing Dt:
10/26/2010
Publication #:
US20110037136
Pub Dt:
02/17/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH IMAGE SENSOR SYSTEM
46
Patent #:
8384227
Issue Dt:
02/26/2013
Application #:
12947442
Filing Dt:
11/16/2010
Publication #:
US20120119388
Pub Dt:
05/17/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME ELECTRICALLY CONNECTED TO EMBEDDED SEMICONDUCTOR DIE
47
Patent #:
8372695
Issue Dt:
02/12/2013
Application #:
12950631
Filing Dt:
11/19/2010
Publication #:
US20120126428
Pub Dt:
05/24/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK INTERCONNECT AND METHOD OF MANUFACTURE THEREOF
48
Patent #:
8349721
Issue Dt:
01/08/2013
Application #:
12961202
Filing Dt:
12/06/2010
Publication #:
US20110074026
Pub Dt:
03/31/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER ON CONDUCTIVE TRACES FOR ELECTRICAL ISOLATION IN FINE PITCH BONDING
49
Patent #:
8415205
Issue Dt:
04/09/2013
Application #:
12961494
Filing Dt:
12/06/2010
Publication #:
US20110169151
Pub Dt:
07/14/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD INTERLOCKING MECHANISMS AND METHOD OF MANUFACTURE THEREOF
50
Patent #:
8350384
Issue Dt:
01/08/2013
Application #:
12963934
Filing Dt:
12/09/2010
Publication #:
US20110121464
Pub Dt:
05/26/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING ELECTRICAL INTERCONNECT WITH STRESS RELIEF VOID
51
Patent #:
8368199
Issue Dt:
02/05/2013
Application #:
12964644
Filing Dt:
12/09/2010
Publication #:
US20110079891
Pub Dt:
04/07/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES AND METHOD FOR MANUFACTURING THEREOF
52
Patent #:
8377750
Issue Dt:
02/19/2013
Application #:
12968266
Filing Dt:
12/14/2010
Publication #:
US20120146203
Pub Dt:
06/14/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTIPLE ROW LEADS AND METHOD OF MANUFACTURE THEREOF
53
Patent #:
8383458
Issue Dt:
02/26/2013
Application #:
12974265
Filing Dt:
12/21/2010
Publication #:
US20110084373
Pub Dt:
04/14/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION AND METHOD FOR MANUFACTURING THEREOF
54
Patent #:
8405230
Issue Dt:
03/26/2013
Application #:
13006697
Filing Dt:
01/14/2011
Publication #:
US20110108970
Pub Dt:
05/12/2011
Title:
SEMICONDUCTOR FLIP CHIP PACKAGE HAVING SUBSTANTIALLY NON-COLLAPSIBLE SPACER AND METHOD OF MANUFACTURE THEREOF
55
Patent #:
8409917
Issue Dt:
04/02/2013
Application #:
13053719
Filing Dt:
03/22/2011
Publication #:
US20120241925
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
56
Patent #:
8420447
Issue Dt:
04/16/2013
Application #:
13070291
Filing Dt:
03/23/2011
Publication #:
US20120241928
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FLIPCHIP LEADFRAME AND METHOD OF MANUFACTURE THEREOF
57
Patent #:
8415206
Issue Dt:
04/09/2013
Application #:
13070899
Filing Dt:
03/24/2011
Publication #:
US20120241962
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME ETCHING AND METHOD OF MANUFACTURE THEREOF
58
Patent #:
8420448
Issue Dt:
04/16/2013
Application #:
13071449
Filing Dt:
03/24/2011
Publication #:
US20120241948
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PADS AND METHOD OF MANUFACTURE THEREOF
59
Patent #:
8399306
Issue Dt:
03/19/2013
Application #:
13071760
Filing Dt:
03/25/2011
Publication #:
US20120241927
Pub Dt:
09/27/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSPARENT ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF
60
Patent #:
8389333
Issue Dt:
03/05/2013
Application #:
13116328
Filing Dt:
05/26/2011
Publication #:
US20120299191
Pub Dt:
11/29/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING EWLB PACKAGE CONTAINING STACKED SEMICONDUCTOR DIE ELECTRICALLY CONNECTED THROUGH CONDUCTIVE VIAS FORMED IN ENCAPSULANT AROUND DIE
61
Patent #:
8389329
Issue Dt:
03/05/2013
Application #:
13118955
Filing Dt:
05/31/2011
Publication #:
US20120306102
Pub Dt:
12/06/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF
62
Patent #:
8409979
Issue Dt:
04/02/2013
Application #:
13149669
Filing Dt:
05/31/2011
Publication #:
US20120306104
Pub Dt:
12/06/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES
63
Patent #:
8415810
Issue Dt:
04/09/2013
Application #:
13160799
Filing Dt:
06/15/2011
Publication #:
US20110241223
Pub Dt:
10/06/2011
Title:
INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE-IN-FILM ISOLATION BARRIER AND METHOD FOR MANUFACTURING THEREOF
64
Patent #:
8375576
Issue Dt:
02/19/2013
Application #:
13161008
Filing Dt:
06/15/2011
Publication #:
US20110239459
Pub Dt:
10/06/2011
Title:
METHOD FOR MANUFACTURING WAFER SCALE HEAT SLUG SYSTEM
65
Patent #:
8409923
Issue Dt:
04/02/2013
Application #:
13161368
Filing Dt:
06/15/2011
Publication #:
US20120319300
Pub Dt:
12/20/2012
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF
66
Patent #:
8354746
Issue Dt:
01/15/2013
Application #:
13174033
Filing Dt:
06/30/2011
Publication #:
US20110254157
Pub Dt:
10/20/2011
Title:
Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant
67
Patent #:
8389332
Issue Dt:
03/05/2013
Application #:
13197122
Filing Dt:
08/03/2011
Publication #:
US20110284999
Pub Dt:
11/24/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ISOLATED PADS AND METHOD OF MANUFACTURE THEREOF
68
Patent #:
8350368
Issue Dt:
01/08/2013
Application #:
13209620
Filing Dt:
08/15/2011
Publication #:
US20110298105
Pub Dt:
12/08/2011
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER AFTER ENCAPSULATION AND GROUNDED THROUGH INTERCONNECT STRUCTURE
69
Patent #:
8368200
Issue Dt:
02/05/2013
Application #:
13211698
Filing Dt:
08/17/2011
Publication #:
US20110298107
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Pub Dt:
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Title:
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Assignor
1
STATS CHIPPAC LTD.
Exec Dt:
03/29/2016
Assignee
1
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET
SINGAPORE, SINGAPORE
Correspondence name and address
SEAN WOODEN
1919 PENNSYLVANIA AVE., NW - SUITE 800
WASHINGTON, DC 20006

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