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Reel/Frame:065404/0650   Pages: 5
Recorded: 10/31/2023
Attorney Dkt #:TSMP20211114US01
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
NONE
Issue Dt:
Application #:
17837686
Filing Dt:
06/10/2022
Publication #:
Pub Dt:
08/17/2023
Title:
INTEGRATED CIRCUIT PACKAGE AND METHOD
Assignors
1
Exec Dt:
08/28/2022
2
Exec Dt:
06/01/2022
3
Exec Dt:
10/27/2023
Assignee
1
8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK
HSINCHU, TAIWAN 300-78
Correspondence name and address
SLATER MATSIL, LLP - TSMC
17950 PRESTON ROAD, SUITE 1000
DALLAS, TX 75252

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