Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 067150/0051 | |
| Pages: | 5 |
| | Recorded: | 04/18/2024 | | |
| Attorney Dkt #: | 3771-0019-C8 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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06/06/2017
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Application #:
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15191369
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Filing Dt:
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06/23/2016
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Publication #:
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Pub Dt:
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10/20/2016
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Title:
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STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER
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Patent #:
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Issue Dt:
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09/25/2018
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Application #:
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15594436
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Filing Dt:
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05/12/2017
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Publication #:
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Pub Dt:
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08/31/2017
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Title:
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STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER
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Patent #:
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Issue Dt:
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03/03/2020
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Application #:
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16105277
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Filing Dt:
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08/20/2018
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Publication #:
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Pub Dt:
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01/03/2019
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Title:
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STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER
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Patent #:
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Issue Dt:
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03/16/2021
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Application #:
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16781260
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Filing Dt:
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02/04/2020
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Publication #:
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Pub Dt:
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06/04/2020
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Title:
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STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER
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Patent #:
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Issue Dt:
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10/18/2022
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Application #:
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17201728
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Filing Dt:
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03/15/2021
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Publication #:
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Pub Dt:
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07/01/2021
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Title:
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STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER
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Patent #:
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Issue Dt:
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05/07/2024
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Application #:
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17935515
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Filing Dt:
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09/26/2022
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Publication #:
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Pub Dt:
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01/19/2023
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Title:
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STRAINED SEMICONDUCTOR USING ELASTIC EDGE RELAXATION OF A STRESSOR COMBINED WITH BURIED INSULATING LAYER
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Assignee
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| 330 WILSHIRE BLVD., 2ND FLOOR |
| SANTA MONICA, CALIFORNIA 90401 |
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Correspondence name and address
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TAREK N. FAHMI
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2150 N. FIRST STREET, SUITE 420
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SAN JOSE, CA 95131
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05/15/2024 01:19 PM
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