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Patent #:
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Issue Dt:
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10/10/2000
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Application #:
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09010081
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Filing Dt:
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01/21/1998
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Title:
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INSITU DOPED METAL POLICIDE
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Patent #:
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Issue Dt:
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05/02/2000
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Application #:
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09014431
|
Filing Dt:
|
01/27/1998
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Title:
|
LOW TEMPERATURE REFLOW DIELECTRIC-FLUORINATED BPSG
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2000
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Application #:
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09014805
|
Filing Dt:
|
01/28/1998
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Title:
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HIGH SELECTIVITY COLLAR OXIDE ETCH PROCESSES
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Patent #:
|
|
Issue Dt:
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10/19/1999
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Application #:
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09017019
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Filing Dt:
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02/02/1998
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Title:
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REPAIRABLE SEMICONDUCTOR INTEGRATED CIRCUIT MEMORY BY SELECTIVE ASSIGNMENT OF GROUPS OF REDUNDANCY ELEMENTS TO DOMAINS `
|
|
|
Patent #:
|
|
Issue Dt:
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12/28/1999
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Application #:
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09031995
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Filing Dt:
|
02/27/1998
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Title:
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METHOD FOR FORMING TRENCH CAPACITORS IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2000
|
Application #:
|
09034519
|
Filing Dt:
|
03/04/1998
|
Title:
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MEMORY CELL STRUCTURE AND FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
09036319
|
Filing Dt:
|
03/06/1998
|
Title:
|
SIGNALING IMPROVEMENT USING EXTENDED TRANSMISSION LINES ON HIGH SPEED DIMMS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
09036478
|
Filing Dt:
|
03/06/1998
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Title:
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METHODS AND APPARATUS FOR CHEMICAL MECHANICAL PLANARIZATION (CMP) OF A SEMICONDUCTOR WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2004
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Application #:
|
09037287
|
Filing Dt:
|
03/09/1998
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Title:
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SELF ALIGNED BURIED PLATE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09047581
|
Filing Dt:
|
03/25/1998
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Title:
|
SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTOR AND BURIED WORD LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
09052683
|
Filing Dt:
|
03/31/1998
|
Title:
|
IMPROVED CONTROLLABILITY OF A BURIED DEVICE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/1999
|
Application #:
|
09052799
|
Filing Dt:
|
03/31/1998
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Title:
|
DYNAMIC RANDOM ACCESS MEMORY CIRCUIT AND METHODS THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09056119
|
Filing Dt:
|
04/06/1998
|
Title:
|
TRENCH CAPACITOR WITH EPI BURIED LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
09061565
|
Filing Dt:
|
04/16/1998
|
Title:
|
REMOVAL OF POST-RIE POLYMER ON A1/CU METAL LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2000
|
Application #:
|
09074882
|
Filing Dt:
|
05/08/1998
|
Title:
|
METHOD OF FORMING STACK CAPACITOR WITH IMPROVED PLUG CONDUCTIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2000
|
Application #:
|
09093796
|
Filing Dt:
|
06/09/1998
|
Title:
|
SEMICONDUCTORS HAVING DEFECT DENUDED ZONES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09093801
|
Filing Dt:
|
06/09/1998
|
Title:
|
METHOD OF FORMING DEEP TRENCH CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09093802
|
Filing Dt:
|
06/09/1998
|
Title:
|
CLOCK LATENCY COMPENSATION CIRCUIT FOR DDR TIMING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09095793
|
Filing Dt:
|
06/11/1998
|
Title:
|
VERTICAL DEVICE FORMED ADJACENT TO A WORLDLINE SIDEWALL AND METHOD FOR SEMICONDUCTOR CHIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
09097545
|
Filing Dt:
|
06/15/1998
|
Title:
|
MEMORY WITH REDUCED WIRE CONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
09097783
|
Filing Dt:
|
06/15/1998
|
Title:
|
TRENCH CAPACITOR WITH ISOLATION COLLAR AND CORRESPONDING MANUFACTURING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2000
|
Application #:
|
09097784
|
Filing Dt:
|
06/15/1998
|
Title:
|
OVERLAY MEASUREMENT TECHNIQUE USING MOIRE PATTERNS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
09097872
|
Filing Dt:
|
06/15/1998
|
Title:
|
HIGH DENSITY PLASMA CVD PROCESS FOR MAKING DIELECTRIC ANTI-REFLECTIVE COATINGS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
09098203
|
Filing Dt:
|
06/16/1998
|
Title:
|
A METHOD FOR FORMING ELECTRICAL ISOLATION FOR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2000
|
Application #:
|
09098785
|
Filing Dt:
|
06/17/1998
|
Title:
|
PHASE SHIFT MASK HAVING MULTIPLE ALIGNMENT INDICATIONS AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09099093
|
Filing Dt:
|
06/17/1998
|
Title:
|
SEMICONDUCTOR METALIZATION SYSTEM AND METHOD BACKGROUND OF THE INVENTION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
09102471
|
Filing Dt:
|
06/22/1998
|
Title:
|
LOW-RESISTANCE SALICIDE FILL FOR TRENCH CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2000
|
Application #:
|
09103871
|
Filing Dt:
|
06/24/1998
|
Title:
|
LOCK ARRANGEMENT FOR A CALABRATED DDL IN DDR SDRAM APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09105107
|
Filing Dt:
|
06/24/1998
|
Title:
|
METHOD FOR FORMING A SEMINCONDUCTOR FUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09105226
|
Filing Dt:
|
06/25/1998
|
Title:
|
SELF-ALIGNED FORMATION AND METHOD FOR SEMICONDUCTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2000
|
Application #:
|
09105580
|
Filing Dt:
|
06/26/1998
|
Title:
|
BOTTLE-SHAPED TRENCH CAPACITOR WITH EPI BURIED LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09105632
|
Filing Dt:
|
06/26/1998
|
Title:
|
SYSTEM AND METHOD FOR OPTICALLY MEASURING DIELECTRIC THICKNESS IN SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09105633
|
Filing Dt:
|
06/26/1998
|
Title:
|
LOW LEAKAGE, LOW CAPACITANCE ISOLATION MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2000
|
Application #:
|
09105647
|
Filing Dt:
|
06/26/1998
|
Title:
|
SEMICONDUCTOR STRUCTURE INCLUDING A CONDUCTIVE FUSE AND PROCESS FOR FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
09105945
|
Filing Dt:
|
06/26/1998
|
Title:
|
TRENCH CAPACITOR WITH EPI BURIED LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2000
|
Application #:
|
09107191
|
Filing Dt:
|
06/29/1998
|
Title:
|
INTERLEAVED SENSE AMPLIFIER WITH A SINGLE-SIDED PRECHARGE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09107672
|
Filing Dt:
|
06/30/1998
|
Title:
|
SEMICONDUCTOR MANUFACTURING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09107980
|
Filing Dt:
|
06/30/1998
|
Title:
|
METHOD FOR FORMING A HIGH SURFACE AREA TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
|
Application #:
|
09123298
|
Filing Dt:
|
07/28/1998
|
Title:
|
TAPERED ELECTRODE FOR STACKED CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
09127262
|
Filing Dt:
|
07/31/1998
|
Title:
|
APPARATUS AND METHOD FOR FORMING CONTROLLED DEEP TRENCH TOP ISOLATION LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2000
|
Application #:
|
09127740
|
Filing Dt:
|
08/03/1998
|
Title:
|
TIMING OF WORLDLINE ACTIVATION FOR DC BURN-IN OF A DRAM WITH THE SELF-REFRESH
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09130226
|
Filing Dt:
|
08/06/1998
|
Title:
|
METHODS TO CONTROL THE THRESHOLD VOLTAGE OF A DEEP TRENCH CORNER DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
09130324
|
Filing Dt:
|
08/06/1998
|
Title:
|
A METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURES INCLUDING A PAIR OF MOSFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09133203
|
Filing Dt:
|
08/13/1998
|
Title:
|
INTEGRATION SCHEME ENHANCING DEEP TRENCH CAPACITANCE IN SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
09135866
|
Filing Dt:
|
08/18/1998
|
Title:
|
A CMP PROCESS USING INDICATOR AREAS TO DETERMINE ENDPOINT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2000
|
Application #:
|
09136604
|
Filing Dt:
|
08/19/1998
|
Title:
|
METHOD FOR MAKING DRAM CAPACITOR STRAP
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09139514
|
Filing Dt:
|
08/25/1998
|
Title:
|
WORDLINE DRIVER CIRCUIT USING RING-SHAPED DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09144297
|
Filing Dt:
|
08/31/1998
|
Title:
|
RECOVERY OF ELECTRONIC PROPERTIES IN PROCESS-DAMAGED FERROELECTRICS BY VOLTAGE-CYCLING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09146870
|
Filing Dt:
|
09/03/1998
|
Title:
|
COMBINED PREANNEAL/OXIDATION STEP USING RAPID THERMAL PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2000
|
Application #:
|
09156071
|
Filing Dt:
|
09/17/1998
|
Title:
|
COMPOSITION AND METHOD FOR REDUCING DISHING IN PATTERNED METAL DURING CMP PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09161793
|
Filing Dt:
|
09/28/1998
|
Title:
|
METHOD OF ENHANCING SEMICONDUCTOR WAFER RELEASE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09161861
|
Filing Dt:
|
09/28/1998
|
Title:
|
STACKED CAPACITATOR MEMORY CELL AND METHOD OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
09162867
|
Filing Dt:
|
09/29/1998
|
Title:
|
MEMORY CELL WITH A STACKED CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09163670
|
Filing Dt:
|
09/30/1998
|
Title:
|
6 1/4 F2 DRAM CELL STRUCTURE WITH FOUR NODES PER BITLINE-STUD AND TWO TOPOLOGICAL WORDLINE LEVELS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2001
|
Application #:
|
09175267
|
Filing Dt:
|
10/20/1998
|
Title:
|
METHOD FOR FABRICATING TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
09181964
|
Filing Dt:
|
10/29/1998
|
Title:
|
DEEP DIVOT MASK FOR ENHANCED BURIED-CHANNEL PFET PERFORMANCE AND RELIABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09186515
|
Filing Dt:
|
11/05/1998
|
Title:
|
FUSE LAYOUT FOR IMPROVED FUSE BLOW PROCESS WINDOW
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09192698
|
Filing Dt:
|
11/16/1998
|
Title:
|
IN-SITU MEASUREMENT METHOD AND APPARATUS FOR SEMICONDUCTOR PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09193203
|
Filing Dt:
|
11/17/1998
|
Title:
|
METHOD OF FORMING A TRENCH CAPACITOR USING A RUTILE DIELECTRIC MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09200338
|
Filing Dt:
|
11/25/1998
|
Title:
|
DELAY LOCK LOOP
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09201205
|
Filing Dt:
|
11/30/1998
|
Title:
|
SLOTTED DAMASCENE LINES FOR LOW RESISTIVE WIRING LINES FOR INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2005
|
Application #:
|
09204706
|
Filing Dt:
|
12/03/1998
|
Publication #:
|
|
Pub Dt:
|
07/05/2001
| | | | |
Title:
|
REMOVAL OF POST-RIE POLYMER ON A1/CU METAL LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
09209198
|
Filing Dt:
|
12/10/1998
|
Title:
|
EXTENDED TRENCH FOR PREVENTING INTERACTION BETWEEN COMPONENTS OF STACKED CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2000
|
Application #:
|
09209199
|
Filing Dt:
|
12/10/1998
|
Title:
|
DISTRIBUTED BLOCK REDUNDANCY FOR MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2000
|
Application #:
|
09209413
|
Filing Dt:
|
12/10/1998
|
Title:
|
METHOD AND APPARATUS FOR PREVENTING FORMATION OF BLACK SILICON ON EDGES OF WAFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09213469
|
Filing Dt:
|
12/17/1998
|
Title:
|
METHODS FOR ENHANCING THE METAL REMOVAL RATE DURING THE CHEMICAL-MECHANICAL POLISHING PROCESS OF A SEMICONDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2000
|
Application #:
|
09218561
|
Filing Dt:
|
12/22/1998
|
Title:
|
A REPAIRABLE SEMICONDUCTOR MEMORY CIRCUIT HAVING PARALLEL REDUNDANCY REPLACEMENT WHEREIN REDUNDANCY ELEMENTS REPLACE FAILED ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09228178
|
Filing Dt:
|
01/11/1999
|
Publication #:
|
|
Pub Dt:
|
03/14/2002
| | | | |
Title:
|
SYSTEM AND METHOD FOR DETERMINING YIELD IMPACT FOR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
09234341
|
Filing Dt:
|
01/20/1999
|
Title:
|
METHOD OF MAKING A MICROELECTRONIC STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2000
|
Application #:
|
09299364
|
Filing Dt:
|
04/26/1999
|
Title:
|
RADIATION-SENSITIVE MIXTURE AND ITS USE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
09313424
|
Filing Dt:
|
05/17/1999
|
Title:
|
SOI SEMICONDUCTOR CONFIGURATION AND METHOD OF FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09317662
|
Filing Dt:
|
05/24/1999
|
Title:
|
MEMORY CELL STRUCTURE AND FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09333228
|
Filing Dt:
|
06/14/1999
|
Publication #:
|
|
Pub Dt:
|
11/29/2001
| | | | |
Title:
|
IMPROVED METHODS AND APPARATUS FOR CHEMICAL MECHANICAL PLANARIZATION (CMP) OF A SEMICONDUCTOR WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09390496
|
Filing Dt:
|
09/03/1999
|
Title:
|
METHOD FOR THE FABRICATION OF A DOPED SILICON LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
09391717
|
Filing Dt:
|
09/08/1999
|
Title:
|
INTEGRATED SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2002
|
Application #:
|
09391720
|
Filing Dt:
|
09/08/1999
|
Title:
|
LAYER CONFIGURATION WITH A MATERIAL LAYER AND A DIFFUSION BARRIER WHICH BLOCKS DIFFUSING MATERIAL COMPONENTS AND PROCESS FOR PRODUCING A DIFFUSION BARRIER
|
|
|
Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09394196
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Filing Dt:
|
09/10/1999
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Title:
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ELECTRONIC CIRCUIT CONFIGURATION
|
|
|
Patent #:
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Issue Dt:
|
05/08/2001
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Application #:
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09395005
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Filing Dt:
|
09/13/1999
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Title:
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INTEGRATED CIRCUIT WITH TWO OPERATING STATES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2001
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Application #:
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09395226
|
Filing Dt:
|
09/13/1999
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Title:
|
PRODUCTION METHOD FOR A TRENCH CAPACITOR WITH AN INSULATION COLLAR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
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Application #:
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09395316
|
Filing Dt:
|
09/13/1999
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Title:
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CAPACITOR WITH HIGH-E DIELECTRIC OR FERROELECTRIC MATERIAL BASED ON THE FIN STACK PRINCIPLE AND PRODUCTION PROCESS USING A NEGATIVE MOLD
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
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Application #:
|
09398695
|
Filing Dt:
|
09/20/1999
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Title:
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INTEGRATED CIRCUIT MEMORY HAVING A SENSE AMPLIFIER ACTIVATED BASED ON WORD LINE POTENTIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09401387
|
Filing Dt:
|
09/22/1999
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Title:
|
METHOD FOR DETERMINING THE DRIVE CAPABILITY OF A DRIVER CIRCUIT OF AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09401388
|
Filing Dt:
|
09/22/1999
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Title:
|
INTEGRATED MEMORY HAVING A SELF-REPAIR FUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2001
|
Application #:
|
09401390
|
Filing Dt:
|
09/22/1999
|
Title:
|
BURN-IN TEST DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2002
|
Application #:
|
09404494
|
Filing Dt:
|
09/23/1999
|
Title:
|
TRENCH CAPACITOR WITH INSULATION COLLAR AND CORRESPONDING FABRICATION METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09405916
|
Filing Dt:
|
09/24/1999
|
Title:
|
MEMORY CELL CONFIGURATION AND PRODUCTION PROCESS THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09407263
|
Filing Dt:
|
09/27/1999
|
Title:
|
METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
09408476
|
Filing Dt:
|
09/28/1999
|
Title:
|
INTEGRATED CIRCUIT HAVING A CONTACT-MAKING POINT FOR SELECTING AN OPERATING MODE OF THE INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09408479
|
Filing Dt:
|
09/28/1999
|
Title:
|
FERROELECTRIC MEMORY AND METHOD FOR PREVENTING AGING IN A MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09408677
|
Filing Dt:
|
09/30/1999
|
Title:
|
INTEGRATED CIRCUIT WITH A CONFIGURATION ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09408685
|
Filing Dt:
|
09/30/1999
|
Title:
|
INTEGRATED CIRCUIT HAVING ADJUSTABLE DELAY UNITS FOR CLOCK SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
09408687
|
Filing Dt:
|
09/30/1999
|
Title:
|
INTEGRATED CIRCUIT WITH ADJUSTABLE DELAY UNIT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
09408688
|
Filing Dt:
|
09/30/1999
|
Title:
|
VERTICAL FIELD EFFECT TRANSISTOR WITH INTERNAL ANNULAR GATE AND METHOD OF PRODUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09408689
|
Filing Dt:
|
09/30/1999
|
Title:
|
CIRCUIT FOR GENERATING OUTPUT SIGNALS AS A FUNCTION OF INPUT SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2003
|
Application #:
|
09423864
|
Filing Dt:
|
11/15/1999
|
Title:
|
INTEGRATED CMOS CIRCUIT CONFIGURATION, AND PRODUCTION OF SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2001
|
Application #:
|
09426420
|
Filing Dt:
|
10/25/1999
|
Title:
|
IMPLANTATION MASK FOR PRODUCING A MEMORY CELL CONFIGURATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
09428181
|
Filing Dt:
|
10/27/1999
|
Title:
|
METHOD FOR FABRICATING A CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
09431529
|
Filing Dt:
|
11/01/1999
|
Title:
|
READ/WRITE MEMORY WITH SELF-TEST DEVICE AND ASSOCIATED TEST METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2001
|
Application #:
|
09440721
|
Filing Dt:
|
11/15/1999
|
Title:
|
CIRCUIT CONFIGURATION WITH A TEMPERATURE-DEPENDENT SEMICONDUCTOR COMPONENT TEST AND REPAIR LOGIC CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2002
|
Application #:
|
09440803
|
Filing Dt:
|
11/15/1999
|
Title:
|
SEMICONDUCTOR MODULE FOR BURN-IN TEST CONFIGURATION
|
|