|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
13014828
|
Filing Dt:
|
01/27/2011
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
Title:
|
DESIGN STRUCTURE FOR A DUTY CYCLE CORRECTION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
13014995
|
Filing Dt:
|
01/27/2011
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
METHOD OF FABRICATING AN EMBEDDED POLYSILICON RESISTOR AND AN EMBEDDED EFUSE ISOLATED FROM A SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2012
|
Application #:
|
13015668
|
Filing Dt:
|
01/28/2011
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
Title:
|
MIXED LITHOGRAPHY WITH DUAL RESIST AND A SINGLE PATTERN TRANSFER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
13015767
|
Filing Dt:
|
01/28/2011
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
Title:
|
HEAT TRANSFER DEVICE IN A ROTATING STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
13015857
|
Filing Dt:
|
01/28/2011
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
METHODS OF MAKING FINS AND FIN FIELD EFFECT TRANSISTORS (FINFETS)
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
13015875
|
Filing Dt:
|
01/28/2011
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
Title:
|
STRUCTURE AND METHOD FOR MANUFACTURING DEVICE WITH A V-SHAPE CHANNEL NMOSFET
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2013
|
Application #:
|
13015936
|
Filing Dt:
|
01/28/2011
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
NANO-ELECTRO-MECHANICAL DRAM CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13016126
|
Filing Dt:
|
01/28/2011
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
13016340
|
Filing Dt:
|
01/28/2011
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
CONDUCTOR STRUCTURE INCLUDING MANGANESE OXIDE CAPPING LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
13016492
|
Filing Dt:
|
01/28/2011
|
Publication #:
|
|
Pub Dt:
|
06/02/2011
| | | | |
Title:
|
HIGH DENSITY DATA STORAGE MEDIUM, METHOD AND DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13016977
|
Filing Dt:
|
01/29/2011
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
CORRECTING MEMORY DEVICE AND MEMORY CHANNEL FAILURES IN THE PRESENCE OF KNOWN MEMORY DEVICE FAILURES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13017127
|
Filing Dt:
|
01/31/2011
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
REDUCED S/D CONTACT RESISTANCE OF III-V MOSFET USING LOW TEMPERATURE METAL-INDUCED CRYSTALLIZATION OF N+ GE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13017593
|
Filing Dt:
|
01/31/2011
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
DETERMINING MANUFACTURABILITY OF LITHOGRAPHIC MASK BASED ON MANUFACTURING SHAPE PENALTY OF ASPECT RATIO OF EDGE THAT TAKES INTO ACCOUNT PAIR OF CONNECTED EDGES OF THE EDGE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
13017809
|
Filing Dt:
|
01/31/2011
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
DEVICES AND METHODS TO OPTIMIZE MATERIALS AND PROPERTIES FOR REPLACEMENT METAL GATE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
13018751
|
Filing Dt:
|
02/01/2011
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
Title:
|
ELECTRICAL CONTACT METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13018963
|
Filing Dt:
|
02/01/2011
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
HIGH PERFORMANCE ON-CHIP VERTICAL COAXIAL CABLE, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2013
|
Application #:
|
13019130
|
Filing Dt:
|
02/01/2011
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
THREE-DIMENSIONAL INTEGRATED CIRCUITS AND TECHNIQUES FOR FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13019716
|
Filing Dt:
|
02/02/2011
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
SCHOTTKY BARRIER DIODE, A METHOD OF FORMING THE DIODE AND A DESIGN STRUCTURE FOR THE DIODE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2012
|
Application #:
|
13019949
|
Filing Dt:
|
02/02/2011
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
Title:
|
GATE EFFECTIVE-WORKFUNCTION MODIFICATION FOR CMOS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
|
Application #:
|
13020051
|
Filing Dt:
|
02/03/2011
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13020107
|
Filing Dt:
|
02/03/2011
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
SEALED AIR GAP FOR SEMICONDUCTOR CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13020222
|
Filing Dt:
|
02/03/2011
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
ADAPTIVE NEXT-EXECUTING-CYCLE TRACE SELECTION FOR TRACE-DRIVEN CODE OPTIMIZERS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13020223
|
Filing Dt:
|
02/03/2011
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
Title:
|
STRAINED ULTRA-THIN SOI TRANSISTOR FORMED BY REPLACEMENT GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13020846
|
Filing Dt:
|
02/04/2011
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
MANUFACTURING EXECUTION SYSTEM (MES) INCLUDING A WAFER SAMPLING ENGINE (WSE) FOR A SEMICONDUCTOR MANUFACTURING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2012
|
Application #:
|
13020925
|
Filing Dt:
|
02/04/2011
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
Title:
|
SPIN-CURRENT SWITCHABLE MAGNETIC MEMORY ELEMENT AND METHOD OF FABRICATING THE MEMORY ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13021558
|
Filing Dt:
|
02/25/2011
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
Title:
|
Photoacid Generators for Extreme Ultraviolet Lithography
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2012
|
Application #:
|
13021774
|
Filing Dt:
|
02/06/2011
|
Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
Title:
|
REVERSING TONE OF PATTERNS ON INTEGRATED CIRCUIT AND NANOSCALE FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
13021852
|
Filing Dt:
|
02/07/2011
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
Boundary Layer Formation and Resultant Structures
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2012
|
Application #:
|
13022474
|
Filing Dt:
|
02/07/2011
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
METHOD TO ENABLE THE PROCESS AND ENLARGE THE PROCESS WINDOW FOR SILICIDE, GERMANIDE OR GERMANOSILICIDE FORMATION IN STRUCTURES WITH EXTREMELY SMALL DIMENSIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13022647
|
Filing Dt:
|
02/08/2011
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
Autonomous, Scalable, Digital System For Emulation of Wired-Or Hardware Connection
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
|
Application #:
|
13022904
|
Filing Dt:
|
02/08/2011
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
PERFORMANCE MONITORING MECHANISM FOR USE IN A PATTERN MATCHING ACCELERATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
13023042
|
Filing Dt:
|
02/08/2011
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING HIGH FIELD REGIONS AND RELATED METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
13023047
|
Filing Dt:
|
02/08/2011
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
METHOD OF FORMING DEEP TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2015
|
Application #:
|
13023559
|
Filing Dt:
|
02/09/2011
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
METHOD FOR DYNAMICALLY SWITCHING ANALYSES AND FOR DYNAMICALLY SWITCHING MODELS IN CIRCUIT SIMULATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2012
|
Application #:
|
13023579
|
Filing Dt:
|
02/09/2011
|
Publication #:
|
|
Pub Dt:
|
06/02/2011
| | | | |
Title:
|
INTEGRATED BEOL THIN FILM RESISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
13023583
|
Filing Dt:
|
02/09/2011
|
Publication #:
|
|
Pub Dt:
|
06/02/2011
| | | | |
Title:
|
SYSTEM TO EXTEND THE SERVICE LIFE OF PORTABLE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
13023743
|
Filing Dt:
|
02/09/2011
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
ENHANCED ELECTROMIGRATION RESISTANCE IN TSV STRUCTURE AND DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2012
|
Application #:
|
13023959
|
Filing Dt:
|
02/09/2011
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS USING DIFFERENTIAL SIGNALING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13024711
|
Filing Dt:
|
02/10/2011
|
Publication #:
|
|
Pub Dt:
|
06/02/2011
| | | | |
Title:
|
PROCESSING FOR OVERCOMING EXTREME TOPOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2012
|
Application #:
|
13024724
|
Filing Dt:
|
02/10/2011
|
Publication #:
|
|
Pub Dt:
|
01/05/2012
| | | | |
Title:
|
GERMANIUM PHOTODETECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13024994
|
Filing Dt:
|
02/10/2011
|
Publication #:
|
|
Pub Dt:
|
02/09/2012
| | | | |
Title:
|
IN-PLANE SILICON HEAT SPREADER AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2015
|
Application #:
|
13025018
|
Filing Dt:
|
02/10/2011
|
Publication #:
|
|
Pub Dt:
|
06/02/2011
| | | | |
Title:
|
NONVOLATILE MEMORY DEVICE USING SEMICONDUCTOR NANOCRYSTALS AND METHOD OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2015
|
Application #:
|
13025322
|
Filing Dt:
|
02/11/2011
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
METHOD TO FABRICATE COPPER WIRING STRUCTURES AND STRUCTURES FORMED TEHREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
13025419
|
Filing Dt:
|
02/11/2011
|
Publication #:
|
|
Pub Dt:
|
06/02/2011
| | | | |
Title:
|
INJECTION MOLDED SOLDER METHOD FOR FORMING SOLDER BUMPS ON SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
13025474
|
Filing Dt:
|
02/11/2011
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
SILICON GERMANIUM FILM FORMATION METHOD AND STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2013
|
Application #:
|
13025501
|
Filing Dt:
|
02/11/2011
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
DUAL CONTACT TRENCH RESISTOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
13025681
|
Filing Dt:
|
02/11/2011
|
Publication #:
|
|
Pub Dt:
|
06/02/2011
| | | | |
Title:
|
DELAMINATION AND CRACK RESISTANT IMAGE SENSOR STRUCTURES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13026168
|
Filing Dt:
|
02/11/2011
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
POLY-OXYCARBOSILANE COMPOSITIONS FOR USE IN IMPRINT LITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
13026339
|
Filing Dt:
|
02/14/2011
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
Title:
|
MICROWAVE READOUT FOR FLUX-BIASED QUBITS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13026451
|
Filing Dt:
|
02/14/2011
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
ANALYSIS OF COMPENSATED LAYOUT SHAPES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2012
|
Application #:
|
13026472
|
Filing Dt:
|
02/14/2011
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
SOFT ERROR DETECTION FOR LATCHES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13027189
|
Filing Dt:
|
02/14/2011
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
TUNING ORDER CONFIGURATOR PERFORMANCE BY DYNAMIC INTEGRATION OF MANUFACTURING AND FIELD FEEDBACK
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13027342
|
Filing Dt:
|
02/15/2011
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
MAGNETIC TUNNEL JUNCTION WITH SPACER LAYER FOR SPIN TORQUE SWITCHED MRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2015
|
Application #:
|
13027375
|
Filing Dt:
|
02/15/2011
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
Methods and Systems Involving Soldering
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
13027797
|
Filing Dt:
|
02/15/2011
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
13028332
|
Filing Dt:
|
02/16/2011
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
DAMAGE PROPAGATION BARRIER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13029214
|
Filing Dt:
|
02/17/2011
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
ON-CHIP MEASUREMENT OF AC VARIABILITY IN INDIVIDUAL TRANSISTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2015
|
Application #:
|
13029657
|
Filing Dt:
|
02/17/2011
|
Publication #:
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Pub Dt:
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08/23/2012
| | | | |
Title:
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INTEGRATED ANTENNA FOR RFIC PACKAGE APPLICATIONS
|
|
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Patent #:
|
|
Issue Dt:
|
10/30/2012
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Application #:
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13029670
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Filing Dt:
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02/17/2011
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Publication #:
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Pub Dt:
|
08/23/2012
| | | | |
Title:
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PIXEL SENSOR CELL WITH A DUAL WORK FUNCTION GATE ELECTODE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
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Application #:
|
13030324
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Filing Dt:
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02/18/2011
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Publication #:
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Pub Dt:
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08/23/2012
| | | | |
Title:
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DETECTING COMBINED TOOL INCOMPATIBILITIES AND DEFECTS IN SEMICONDUCTOR MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
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Application #:
|
13030341
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Filing Dt:
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02/18/2011
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Publication #:
|
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Pub Dt:
|
08/23/2012
| | | | |
Title:
|
SYSTEMS AND METHODS FOR MEMORY DEVICE PRECHARGING
|
|
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Patent #:
|
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Issue Dt:
|
12/04/2012
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Application #:
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13030516
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Filing Dt:
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02/18/2011
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Publication #:
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Pub Dt:
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08/23/2012
| | | | |
Title:
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IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL
|
|
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Patent #:
|
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Issue Dt:
|
12/13/2011
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Application #:
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13031195
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Filing Dt:
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02/19/2011
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Publication #:
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Pub Dt:
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06/16/2011
| | | | |
Title:
|
STRUCTURE FOR INHIBITING BACK END OF LINE DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
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Application #:
|
13031392
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Filing Dt:
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02/21/2011
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Publication #:
|
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Pub Dt:
|
08/23/2012
| | | | |
Title:
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CAPACITOR STRUCTURE
|
|
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Patent #:
|
|
Issue Dt:
|
09/17/2013
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Application #:
|
13031693
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Filing Dt:
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02/22/2011
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Publication #:
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Pub Dt:
|
08/23/2012
| | | | |
Title:
|
METHOD AND SYSTEM FOR EXTRACTING COMPACT MODELS FOR CIRCUIT SIMULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
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Application #:
|
13031754
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Filing Dt:
|
02/22/2011
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Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
Title:
|
METHOD, SYSTEM, AND DESIGN STRUCTURE FOR MAKING VOLTAGE ENVIRONMENT CONSISTENT FOR REUSED SUB MODULES IN CHIP DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
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Application #:
|
13031953
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Filing Dt:
|
02/22/2011
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Publication #:
|
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Pub Dt:
|
02/23/2012
| | | | |
Title:
|
METHOD FOR ESTIMATING THE LATENCY TIME OF A CLOCK TREE IN AN ASIC DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
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Application #:
|
13032059
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Filing Dt:
|
02/22/2011
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Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
DETERMINING INTRA-DIE WIREBOND PAD PLACEMENT LOCATIONS IN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
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Application #:
|
13032361
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Filing Dt:
|
02/22/2011
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Publication #:
|
|
Pub Dt:
|
03/29/2012
| | | | |
Title:
|
MANAGING CONCURRENT ACCESSES TO A CACHE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2013
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Application #:
|
13034936
|
Filing Dt:
|
02/25/2011
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Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
Title:
|
WRITE BANDWIDTH IN A MEMORY CHARACTERIZED BY A VARIABLE WRITE TIME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
13035100
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Filing Dt:
|
02/25/2011
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
Title:
|
USE OF SYMMETRIC RESISTIVE MEMORY MATERIAL AS A DIODE TO DRIVE SYMMETRIC OR ASYMMETRIC RESISTIVE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
13035549
|
Filing Dt:
|
02/25/2011
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
DESIGN STRUCTURE AND METHOD FOR A SILICON CONTROLLED RECTIFIER (SCR) STRUCTURE FOR SOI TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13037420
|
Filing Dt:
|
03/01/2011
|
Publication #:
|
|
Pub Dt:
|
09/06/2012
| | | | |
Title:
|
AUTOMATIC IDENTIFICATION OF INFORMATION USEFUL FOR GENERATION-BASED FUNCTIONAL VERIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
13037485
|
Filing Dt:
|
03/01/2011
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
ASYMMETRIC JUNCTION FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2012
|
Application #:
|
13037608
|
Filing Dt:
|
03/01/2011
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
FORMATION OF IMPROVED SOI SUBSTRATES USING BULK SEMICONDUCTOR WAFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13037944
|
Filing Dt:
|
03/01/2011
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
GROWING COMPRESSIVELY STRAINED SILICON DIRECTLY ON SILICON AT LOW TEMPERATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
13038467
|
Filing Dt:
|
03/02/2011
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
Title:
|
METHODS FOR FORMING A BONDED SEMICONDUCTOR SUBSTRATE INCLUDING A COOLING MECHANISM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13038468
|
Filing Dt:
|
03/02/2011
|
Publication #:
|
|
Pub Dt:
|
09/06/2012
| | | | |
Title:
|
METHOD OF DETERMINING FET SOURCE/DRAIN WIRE, CONTACT, AND DIFFUSION RESISTANCES IN THE PRESENCE OF MULTIPLE CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2015
|
Application #:
|
13039003
|
Filing Dt:
|
03/02/2011
|
Publication #:
|
|
Pub Dt:
|
09/06/2012
| | | | |
Title:
|
OPTICAL INTERCONNECT USING OPTICAL TRANSMITTER PRE-DISTORTION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
13039475
|
Filing Dt:
|
03/03/2011
|
Publication #:
|
|
Pub Dt:
|
09/06/2012
| | | | |
Title:
|
MULTILAYER-INTERCONNECTION FIRST INTEGRATION SCHEME FOR GRAPHENE AND CARBON NANOTUBE TRANSISTOR BASED INTEGRATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13040304
|
Filing Dt:
|
03/04/2011
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
CHIP-BASED PROBER FOR HIGH FREQUENCY MEASUREMENTS AND METHODS OF MEASURING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
13040429
|
Filing Dt:
|
03/04/2011
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
PROGRAMMABLE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13040482
|
Filing Dt:
|
03/04/2011
|
Publication #:
|
|
Pub Dt:
|
09/06/2012
| | | | |
Title:
|
WEAR-FOCUSING OF NON-VOLATILE MEMORIES FOR IMPROVED ENDURANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13040531
|
Filing Dt:
|
03/04/2011
|
Publication #:
|
|
Pub Dt:
|
09/06/2012
| | | | |
Title:
|
BAD BLOCK MANAGEMENT FOR FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13041226
|
Filing Dt:
|
03/04/2011
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
SPIN-CURRENT SWITCHED MAGNETIC MEMORY ELEMENT SUITABLE FOR CIRCUIT INTEGRATION AND METHOD OF FABRICATING THE MEMORY ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13041248
|
Filing Dt:
|
03/04/2011
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
METHOD AND SYSTEM FOR PROVIDING AN IMPROVED STORE-IN CACHE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13041740
|
Filing Dt:
|
03/07/2011
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
Title:
|
SEMICONDUCTOR NANOSTRUCTURES, SEMICONDUCTOR DEVICES, AND METHODS OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
13041754
|
Filing Dt:
|
03/07/2011
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
SEMICONDUCTOR NANOSTRUCTURES, SEMICONDUCTOR DEVICES, AND METHODS OF MAKING SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13042618
|
Filing Dt:
|
03/08/2011
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
Title:
|
LARGE-GRAIN, LOW-RESISTIVITY TUNGSTEN ON A CONDUCTIVE COMPOUND
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13042881
|
Filing Dt:
|
03/08/2011
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
Title:
|
SELECTABLE REPAIR PASS MASKING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13042902
|
Filing Dt:
|
03/08/2011
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
Title:
|
METHODS OF FABRICATING A BIPOLAR JUNCTION TRANSISTOR WITH A SELF-ALIGNED EMITTER AND BASE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13042947
|
Filing Dt:
|
03/08/2011
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
BACK-END-OF-LINE RESISTIVE SEMICONDUCTOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13043749
|
Filing Dt:
|
03/09/2011
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
Title:
|
HIGH MEMORY DENSITY, HIGH INPUT/OUTPUT BANDWIDTH LOGIC-MEMORY STRUCTURE AND ARCHITECTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13043761
|
Filing Dt:
|
03/09/2011
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
Title:
|
SCHEMATIC-BASED LAYOUT MIGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
13044604
|
Filing Dt:
|
03/10/2011
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
TEST CIRCUIT FOR SERIAL LINK RECEIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13044660
|
Filing Dt:
|
03/10/2011
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
Title:
|
SEMICONDUCTOR INTERCONNECT STRUCTURE WITH MULTI-LAYERED SEED LAYER PROVIDING ENHANCED RELIABILITY AND MINIMIZING ELECTROMIGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
13045679
|
Filing Dt:
|
03/11/2011
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
13045756
|
Filing Dt:
|
03/11/2011
|
Publication #:
|
|
Pub Dt:
|
07/14/2011
| | | | |
Title:
|
SELECTIVE FLOATING BODY SRAM CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
13045784
|
Filing Dt:
|
03/11/2011
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
Title:
|
SELECTIVE FLOATING BODY SRAM CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2012
|
Application #:
|
13046084
|
Filing Dt:
|
03/11/2011
|
Title:
|
LOW CAPACITANCE HI-K DUAL WORK FUNCTION METAL GATE BODY-CONTACTED FIELD EFFECT TRANSISTOR
|
|