|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13046377
|
Filing Dt:
|
03/11/2011
|
Publication #:
|
|
Pub Dt:
|
07/28/2011
| | | | |
Title:
|
DRAIN-PUMPED SUB-HARMONIC MIXER FOR MILLIMETER WAVE APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13046902
|
Filing Dt:
|
03/14/2011
|
Publication #:
|
|
Pub Dt:
|
09/20/2012
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13047037
|
Filing Dt:
|
03/14/2011
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
Title:
|
LITHOGRAPHY FOR PRINTING CONSTANT LINE WIDTH FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
13047120
|
Filing Dt:
|
03/14/2011
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
Title:
|
PHOTOSENSITIVE SELF-ASSEMBLED MONOLAYER FOR SELECTIVE PLACEMENT OF HYDROPHILIC STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2015
|
Application #:
|
13047132
|
Filing Dt:
|
03/14/2011
|
Publication #:
|
|
Pub Dt:
|
09/20/2012
| | | | |
Title:
|
FIN FET DEVICE WITH INDEPENDENT CONTROL GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
13047172
|
Filing Dt:
|
03/14/2011
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
Title:
|
SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-K DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
13047492
|
Filing Dt:
|
03/14/2011
|
Publication #:
|
|
Pub Dt:
|
09/20/2012
| | | | |
Title:
|
ROUTING AND TIMING USING LAYER RANGES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
13048170
|
Filing Dt:
|
03/15/2011
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
HIGH-K METAL GATE CMOS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13048224
|
Filing Dt:
|
03/15/2011
|
Publication #:
|
|
Pub Dt:
|
09/20/2012
| | | | |
Title:
|
HIGH DENSITY SIX TRANSISTOR FINFET SRAM CELL LAYOUT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
13048342
|
Filing Dt:
|
03/15/2011
|
Publication #:
|
|
Pub Dt:
|
09/20/2012
| | | | |
Title:
|
HORIZONTAL POLYSILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13048366
|
Filing Dt:
|
03/15/2011
|
Publication #:
|
|
Pub Dt:
|
09/20/2012
| | | | |
Title:
|
VERTICAL POLYSILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
13048977
|
Filing Dt:
|
03/16/2011
|
Publication #:
|
|
Pub Dt:
|
09/20/2012
| | | | |
Title:
|
FULLY-DEPLETED SON
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13049491
|
Filing Dt:
|
03/16/2011
|
Publication #:
|
|
Pub Dt:
|
09/20/2012
| | | | |
Title:
|
HYBRID MOSFET STRUCTURE HAVING DRAIN SIDE SCHOTTKY JUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
13049933
|
Filing Dt:
|
03/17/2011
|
Title:
|
PROTECTING EXPOSED METAL GATE STRUCTURES FROM ETCHING PROCESSES IN INTEGRATED CIRCUIT MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
13050023
|
Filing Dt:
|
03/17/2011
|
Title:
|
INTEGRATION OF FIN-BASED DEVICES AND ETSOI DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
13050052
|
Filing Dt:
|
03/17/2011
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
Title:
|
STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13050101
|
Filing Dt:
|
03/17/2011
|
Publication #:
|
|
Pub Dt:
|
09/20/2012
| | | | |
Title:
|
FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13050519
|
Filing Dt:
|
03/17/2011
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
Title:
|
POLYMERIC MATERIAL, METHOD OF FORMING THE POLYMERIC MATERIAL, AND MEHTOD OF FORMING A THIN FILM USING THE POLYMERIC MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13051510
|
Filing Dt:
|
03/18/2011
|
Publication #:
|
|
Pub Dt:
|
09/20/2012
| | | | |
Title:
|
DAMASCENE METAL GATE AND SHIELD STRUCTURE, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
13051707
|
Filing Dt:
|
03/18/2011
|
Publication #:
|
|
Pub Dt:
|
09/20/2012
| | | | |
Title:
|
NITRIDE GATE DIELECTRIC FOR GRAPHENE MOSFET
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2014
|
Application #:
|
13052346
|
Filing Dt:
|
03/21/2011
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
Title:
|
PASSIVE RESONATOR, A SYSTEM INCORPORATING THE PASSIVE RESONATOR FOR REAL-TIME INTRA-PROCESS MONITORING AND CONTROL AND AN ASSOCIATED METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
13052662
|
Filing Dt:
|
03/21/2011
|
Publication #:
|
|
Pub Dt:
|
07/14/2011
| | | | |
Title:
|
DESIGN STRUCTURE FOR INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
13053803
|
Filing Dt:
|
03/22/2011
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
Title:
|
WAFER EDGE CONDITIONING FOR THINNED WAFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2015
|
Application #:
|
13069411
|
Filing Dt:
|
03/23/2011
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
Title:
|
LAYOUT DETERMINING FOR WIDE WIRE ON-CHIP INTERCONNECT LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13069653
|
Filing Dt:
|
03/23/2011
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
Title:
|
PHASE PROFILE GENERATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
13070568
|
Filing Dt:
|
03/24/2011
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
Title:
|
SELF-ALIGNED DUAL DEPTH ISOLATION AND METHOD OF FABRICATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13071029
|
Filing Dt:
|
03/24/2011
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
Title:
|
WAVEFORM-BASED DIGITAL GATE MODELING FOR TIMING ANALYSIS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13071043
|
Filing Dt:
|
03/24/2011
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
Title:
|
MAGNETIC TUNNEL JUNCTION WITH IRON DUSTING LAYER BETWEEN FREE LAYER AND TUNNEL BARRIER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
13071894
|
Filing Dt:
|
03/25/2011
|
Publication #:
|
|
Pub Dt:
|
07/14/2011
| | | | |
Title:
|
REWORKABLE ELECTRONIC DEVICE ASSEMBLY AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2013
|
Application #:
|
13071940
|
Filing Dt:
|
03/25/2011
|
Publication #:
|
|
Pub Dt:
|
08/11/2011
| | | | |
Title:
|
STRUCTURE AND METHOD TO ENHANCE BOTH NFET AND PFET PERFORMANCE USING DIFFERENT KINDS OF STRESSED LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
13072023
|
Filing Dt:
|
03/25/2011
|
Publication #:
|
|
Pub Dt:
|
07/14/2011
| | | | |
Title:
|
ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
13072859
|
Filing Dt:
|
03/28/2011
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
Title:
|
METHOD, A PROGRAM STORAGE DEVICE AND A COMPUTER SYSTEM FOR MODELING THE TOTAL CONTACT RESISTANCE OF A SEMICONDUCTOR DEVICE HAVING A MULTI-FINGER GATE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
13073103
|
Filing Dt:
|
03/28/2011
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
Title:
|
DRAM WITH SCHOTTKY BARRIER FET AND MIM TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2012
|
Application #:
|
13073110
|
Filing Dt:
|
03/28/2011
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
Title:
|
FABRICATION OF DEVICES HAVING DIFFERENT INTERFACIAL OXIDE THICKNESS VIA LATERAL OXIDATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
13073151
|
Filing Dt:
|
03/28/2011
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
Title:
|
FORMING BORDERLESS CONTACT FOR TRANSISTORS IN A REPLACEMENT METAL GATE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13073181
|
Filing Dt:
|
03/28/2011
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
Title:
|
SELECTIVE ELECTROMIGRATION IMPROVEMENT FOR HIGH CURRENT C4S
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
13074854
|
Filing Dt:
|
03/29/2011
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
Title:
|
SELF-ALIGNED III-V FIELD EFFECT TRANSISTOR (FET), INTEGRATED CIRCUIT (IC) CHIP WITH SELF-ALIGNED III-V FETS AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
13075271
|
Filing Dt:
|
03/30/2011
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
Title:
|
DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13075443
|
Filing Dt:
|
03/30/2011
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
Title:
|
STRUCTURE AND PROCESS FOR METAL FILL IN REPLACEMENT METAL GATE INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
13075552
|
Filing Dt:
|
03/30/2011
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
Title:
|
SOI BODY CONTACT USING E-DRAM TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
13075657
|
Filing Dt:
|
03/30/2011
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
Title:
|
LOW-TEMPERATURE IN-SITU REMOVAL OF OXIDE FROM A SILICON SURFACE DURING CMOS EPITAXIAL PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13076192
|
Filing Dt:
|
03/30/2011
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
Title:
|
METHOD AND APPARATUS FOR MANUFACTURING ELECTRONIC INTEGRATED CIRCUIT CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
13076781
|
Filing Dt:
|
03/31/2011
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
Title:
|
TUNABLE SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13077216
|
Filing Dt:
|
03/31/2011
|
Publication #:
|
|
Pub Dt:
|
07/28/2011
| | | | |
Title:
|
METHOD OF PLACING A SEMICONDUCTING NANOSTRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTING NANOSTRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
13077765
|
Filing Dt:
|
03/31/2011
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
Title:
|
MULTI-CORE FIBER OPTICAL COUPLING ELEMENTS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13078063
|
Filing Dt:
|
04/01/2011
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
Title:
|
NOISE REDUCTION USING FEEDBACK TO A WIRE SPREADER ROUTER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13078305
|
Filing Dt:
|
04/01/2011
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
Title:
|
MULTILAYERED LOW K CAP WITH CONFORMAL GAP FILL AND UV STABLE COMPRESSIVE STRESS PROPERTIES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13079842
|
Filing Dt:
|
04/05/2011
|
Publication #:
|
|
Pub Dt:
|
10/11/2012
| | | | |
Title:
|
Dynamically Tune Power Proxy Architectures
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
13080019
|
Filing Dt:
|
04/05/2011
|
Publication #:
|
|
Pub Dt:
|
10/11/2012
| | | | |
Title:
|
ELECTRICAL FUSE FORMED BY REPLACEMENT METAL GATE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
13080055
|
Filing Dt:
|
04/05/2011
|
Title:
|
DATA STRUCTURE FOR DESCRIBING MBIST ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13080084
|
Filing Dt:
|
04/05/2011
|
Publication #:
|
|
Pub Dt:
|
10/11/2012
| | | | |
Title:
|
Method of Removing High-K Dielectric Layer on Sidewalls of Gate Structure
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
13080105
|
Filing Dt:
|
04/05/2011
|
Publication #:
|
|
Pub Dt:
|
10/11/2012
| | | | |
Title:
|
SOLDER BALL CONTACT SUSCEPTIBLE TO LOWER STRESS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
13080326
|
Filing Dt:
|
04/05/2011
|
Publication #:
|
|
Pub Dt:
|
07/28/2011
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2013
|
Application #:
|
13080352
|
Filing Dt:
|
04/05/2011
|
Publication #:
|
|
Pub Dt:
|
07/28/2011
| | | | |
Title:
|
CARRIER MOBILITY ENHANCED CHANNEL DEVICES AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13080390
|
Filing Dt:
|
04/05/2011
|
Publication #:
|
|
Pub Dt:
|
10/11/2012
| | | | |
Title:
|
SEMICONDUCTOR NANOWIRE STRUCTURE REUSING SUSPENSION PADS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
13080690
|
Filing Dt:
|
04/06/2011
|
Publication #:
|
|
Pub Dt:
|
10/11/2012
| | | | |
Title:
|
JUNCTION FIELD EFFECT TRANSISTOR WITH AN EPITAXIALLY GROWN GATE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
13080716
|
Filing Dt:
|
04/06/2011
|
Publication #:
|
|
Pub Dt:
|
07/28/2011
| | | | |
Title:
|
METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13080773
|
Filing Dt:
|
04/06/2011
|
Publication #:
|
|
Pub Dt:
|
10/13/2011
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Title:
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PROCESSING EXECUTION REQUESTS WITHIN DIFFERENT COMPUTING ENVIRONMENTS
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Patent #:
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Issue Dt:
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09/24/2013
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Application #:
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13080799
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Filing Dt:
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04/06/2011
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Publication #:
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Pub Dt:
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10/11/2012
| | | | |
Title:
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MULTI-USE PHYSICAL ARCHITECTURE
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Patent #:
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Issue Dt:
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05/07/2013
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Application #:
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13080962
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Filing Dt:
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04/06/2011
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Publication #:
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Pub Dt:
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07/28/2011
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Title:
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DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13082066
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Filing Dt:
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04/07/2011
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Publication #:
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Pub Dt:
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10/11/2012
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Title:
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INTEGRATED CIRCUIT CHIP INCORPORATING A TEST CIRCUIT THAT ALLOWS FOR ON-CHIP STRESS TESTING IN ORDER TO MODEL OR MONITOR DEVICE PERFORMANCE DEGRADATION
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Patent #:
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Issue Dt:
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03/19/2013
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Application #:
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13082440
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Filing Dt:
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04/08/2011
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Publication #:
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Pub Dt:
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11/03/2011
| | | | |
Title:
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METHOD AND SYSTEM FOR COMPUTING FOURIER SERIES COEFFICIENTS FOR MASK LAYOUTS USING FFT
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Patent #:
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Issue Dt:
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02/19/2013
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Application #:
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13082786
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Filing Dt:
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04/08/2011
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Publication #:
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Pub Dt:
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10/11/2012
| | | | |
Title:
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REDUCTION OF ALERTS IN INFORMATION TECHNOLOGY SYSTEMS
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Patent #:
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Issue Dt:
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05/28/2013
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Application #:
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13082867
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Filing Dt:
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04/08/2011
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Publication #:
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Pub Dt:
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10/11/2012
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Title:
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STRUCTURE AND FABRICATION METHOD OF TUNNEL FIELD EFFECT TRANSISTOR WITH INCREASED DRIVE CURRENT AND REDUCED GATE INDUCED DRAIN LEAKAGE (GIDL)
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13083057
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Filing Dt:
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04/08/2011
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Publication #:
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Pub Dt:
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11/03/2011
| | | | |
Title:
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METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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10/22/2013
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Application #:
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13083631
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Filing Dt:
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04/11/2011
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Publication #:
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Pub Dt:
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10/11/2012
| | | | |
Title:
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INTEGRATED CIRCUIT STRUCTURE HAVING SUBSTANTIALLY PLANAR N-P STEP HEIGHT AND METHODS OF FORMING
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Patent #:
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Issue Dt:
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05/28/2013
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Application #:
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13083803
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Filing Dt:
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04/11/2011
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Publication #:
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Pub Dt:
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10/11/2012
| | | | |
Title:
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THERMAL EXPANSION CONTROL EMPLOYING PLATELET FILLERS
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Patent #:
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|
Issue Dt:
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03/25/2014
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Application #:
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13083879
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Filing Dt:
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04/11/2011
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Publication #:
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Pub Dt:
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10/11/2012
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SAME
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|
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Patent #:
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|
Issue Dt:
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11/10/2015
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Application #:
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13083893
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Filing Dt:
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04/11/2011
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Publication #:
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Pub Dt:
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10/11/2012
| | | | |
Title:
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SEMICONDUCTOR DEVICE EXHIBITING REDUCED PARASITICS AND METHOD FOR MAKING SAME
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Patent #:
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|
Issue Dt:
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12/11/2012
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Application #:
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13084088
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Filing Dt:
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04/11/2011
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Publication #:
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|
Pub Dt:
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08/04/2011
| | | | |
Title:
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PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR
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|
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Patent #:
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|
Issue Dt:
|
02/25/2014
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Application #:
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13084435
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Filing Dt:
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04/11/2011
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Publication #:
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|
Pub Dt:
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10/11/2012
| | | | |
Title:
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ROBOTIC DEVICE FOR SUBSTRATE TRANSFER APPLICATIONS
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|
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Patent #:
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|
Issue Dt:
|
09/16/2014
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Application #:
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13085511
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Filing Dt:
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04/13/2011
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Publication #:
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Pub Dt:
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10/18/2012
| | | | |
Title:
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Method And Structure For Compound Semiconductor Contact
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Patent #:
|
|
Issue Dt:
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02/19/2013
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Application #:
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13085632
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Filing Dt:
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04/13/2011
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Publication #:
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Pub Dt:
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08/04/2011
| | | | |
Title:
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ELECTRICALLY PROGRAMMABLE FUSE AND FABRICATION METHOD
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Patent #:
|
|
Issue Dt:
|
08/27/2013
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Application #:
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13085717
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Filing Dt:
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04/13/2011
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Publication #:
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|
Pub Dt:
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08/04/2011
| | | | |
Title:
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OPTICAL COUPLING METHOD
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|
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Patent #:
|
|
Issue Dt:
|
06/16/2015
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Application #:
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13085970
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Filing Dt:
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04/13/2011
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Publication #:
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Pub Dt:
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10/18/2012
| | | | |
Title:
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PASSIVE DEVICES FABRICATED ON GLASS SUBSTRATES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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|
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Patent #:
|
|
Issue Dt:
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07/29/2014
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Application #:
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13086428
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Filing Dt:
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04/14/2011
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Publication #:
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Pub Dt:
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10/18/2012
| | | | |
Title:
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PLACEMENT OF STRUCTURED NETS
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|
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Patent #:
|
|
Issue Dt:
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04/08/2014
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Application #:
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13086459
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Filing Dt:
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04/14/2011
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Publication #:
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Pub Dt:
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10/18/2012
| | | | |
Title:
|
MOSFET with Recessed channel FILM and Abrupt Junctions
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|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
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13087449
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Filing Dt:
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04/15/2011
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Publication #:
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Pub Dt:
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10/18/2012
| | | | |
Title:
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REINFORCED VIA FARM INTERCONNECT STRUCTURE, A METHOD OF FORMING A REINFORCED VIA FARM INTERCONNECT STRUCTURE AND A METHOD OF REDESIGNING AN INTEGRATED CIRCUIT CHIP TO INCLUDE SUCH A REINFORCED VIA FARM INTERCONNECT STRUCTURE
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|
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Patent #:
|
|
Issue Dt:
|
09/24/2013
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Application #:
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13087464
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Filing Dt:
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04/15/2011
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Publication #:
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|
Pub Dt:
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10/18/2012
| | | | |
Title:
|
BONDING CONTROLLER GUIDED ASSESSMENT AND OPTIMIZATIONFOR CHIP-TO-CHIP STACKING
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|
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
|
13087915
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Filing Dt:
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04/15/2011
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Publication #:
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|
Pub Dt:
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10/18/2012
| | | | |
Title:
|
METHOD OF MANUFACTURE OF VERTICAL SUBSTRATE DIODE
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|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
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Application #:
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13088054
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Filing Dt:
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04/15/2011
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Publication #:
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Pub Dt:
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10/18/2012
| | | | |
Title:
|
INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING ON-CHIP INTERCONNECT STRUCTURES BY IMAGE REVERSAL
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|
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Patent #:
|
|
Issue Dt:
|
12/02/2014
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Application #:
|
13088083
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Filing Dt:
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04/15/2011
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Publication #:
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Pub Dt:
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10/18/2012
| | | | |
Title:
|
METHOD FOR FORMING SELF-ALIGNED AIRGAP INTERCONNECT STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
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Application #:
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13088110
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Filing Dt:
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04/15/2011
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Publication #:
|
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Pub Dt:
|
10/18/2012
| | | | |
Title:
|
MIDDLE OF LINE STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
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Application #:
|
13088339
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Filing Dt:
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04/16/2011
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Publication #:
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|
Pub Dt:
|
08/11/2011
| | | | |
Title:
|
TECHNIQUES FOR THREE-DIMENSIONAL CIRCUIT INTEGRATION
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|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
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Application #:
|
13088376
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Filing Dt:
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04/17/2011
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Publication #:
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Pub Dt:
|
10/18/2012
| | | | |
Title:
|
SOI DEVICE WITH DTI AND STI
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
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Application #:
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13088663
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Filing Dt:
|
04/18/2011
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Publication #:
|
|
Pub Dt:
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10/18/2012
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES WITH DUAL TRENCH REGIONS AND METHODS OF MANUFACTURING THE SEMICONDUCTOR STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13088688
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Filing Dt:
|
04/18/2011
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Publication #:
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|
Pub Dt:
|
10/18/2012
| | | | |
Title:
|
DELAY MODEL CONSTRUCTION IN THE PRESENCE OF MULTIPLE INPUT SWITCHING EVENTS
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|
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Patent #:
|
|
Issue Dt:
|
03/20/2012
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Application #:
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13088727
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Filing Dt:
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04/18/2011
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Publication #:
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Pub Dt:
|
08/11/2011
| | | | |
Title:
|
MICRO-FLUIDIC INJECTION MOLDED SOLDER (IMS)
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|
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Patent #:
|
|
Issue Dt:
|
02/04/2014
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Application #:
|
13088766
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Filing Dt:
|
04/18/2011
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Publication #:
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|
Pub Dt:
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10/18/2012
| | | | |
Title:
|
GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SIC FINS OR NANOWIRE TEMPLATES
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13089234
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Filing Dt:
|
04/18/2011
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Publication #:
|
|
Pub Dt:
|
08/11/2011
| | | | |
Title:
|
Charge Carrier Barrier for Image Sensor
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13091275
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Filing Dt:
|
04/21/2011
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Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
Title:
|
INDEPENDENTLY VOLTAGE CONTROLLED VOLUME OF SILICON ON A SILICON ON INSULATOR CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13091292
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Filing Dt:
|
04/21/2011
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Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
Title:
|
EDRAM HAVING DYNAMIC RETENTION AND PERFORMANCE TRADEOFF
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13092247
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Filing Dt:
|
04/22/2011
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Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
Title:
|
RESONANCE NANOELECTROMECHANICAL SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
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Application #:
|
13092304
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Filing Dt:
|
04/22/2011
|
Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
Title:
|
Enhancing Redundancy Removal with Early Merging
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13092424
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Filing Dt:
|
04/22/2011
|
Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
Title:
|
SELF-SEALED FLUIDIC CHANNELS FOR NANOPORE ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13093034
|
Filing Dt:
|
04/25/2011
|
Publication #:
|
|
Pub Dt:
|
08/11/2011
| | | | |
Title:
|
SILICON-ON-INSULATOR SUBSTRATE WITH BUILT-IN SUBSTRATE JUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13095099
|
Filing Dt:
|
04/27/2011
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
INTEGRATED CIRCUIT DESIGN AND SIMULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2012
|
Application #:
|
13095577
|
Filing Dt:
|
04/27/2011
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
Title:
|
NONVOLATIVE MEMORY DEVICE USING SEMICONDUCTOR NANOCRYSTALS AND METHOD OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13095969
|
Filing Dt:
|
04/28/2011
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
Title:
|
SILICON CHICKLET PEDESTAL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13095973
|
Filing Dt:
|
04/28/2011
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
Title:
|
SILICON CHICKLET PEDESTAL
|
|