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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036779/0001   Pages: 985
Recorded: 10/05/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
02/19/2013
Application #:
13045784
Filing Dt:
03/11/2011
Publication #:
Pub Dt:
08/25/2011
Title:
SELECTIVE FLOATING BODY SRAM CELL
2
Patent #:
Issue Dt:
07/10/2012
Application #:
13046084
Filing Dt:
03/11/2011
Title:
LOW CAPACITANCE HI-K DUAL WORK FUNCTION METAL GATE BODY-CONTACTED FIELD EFFECT TRANSISTOR
3
Patent #:
Issue Dt:
11/26/2013
Application #:
13046377
Filing Dt:
03/11/2011
Publication #:
Pub Dt:
07/28/2011
Title:
DRAIN-PUMPED SUB-HARMONIC MIXER FOR MILLIMETER WAVE APPLICATIONS
4
Patent #:
Issue Dt:
09/16/2014
Application #:
13046902
Filing Dt:
03/14/2011
Publication #:
Pub Dt:
09/20/2012
Title:
FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF FORMING SAME
5
Patent #:
Issue Dt:
11/26/2013
Application #:
13047037
Filing Dt:
03/14/2011
Publication #:
Pub Dt:
07/07/2011
Title:
LITHOGRAPHY FOR PRINTING CONSTANT LINE WIDTH FEATURES
6
Patent #:
Issue Dt:
07/24/2012
Application #:
13047120
Filing Dt:
03/14/2011
Publication #:
Pub Dt:
07/07/2011
Title:
PHOTOSENSITIVE SELF-ASSEMBLED MONOLAYER FOR SELECTIVE PLACEMENT OF HYDROPHILIC STRUCTURES
7
Patent #:
Issue Dt:
12/15/2015
Application #:
13047132
Filing Dt:
03/14/2011
Publication #:
Pub Dt:
09/20/2012
Title:
FIN FET DEVICE WITH INDEPENDENT CONTROL GATE
8
Patent #:
Issue Dt:
06/05/2012
Application #:
13047172
Filing Dt:
03/14/2011
Publication #:
Pub Dt:
07/07/2011
Title:
SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-K DIELECTRICS
9
Patent #:
Issue Dt:
05/14/2013
Application #:
13047492
Filing Dt:
03/14/2011
Publication #:
Pub Dt:
09/20/2012
Title:
ROUTING AND TIMING USING LAYER RANGES
10
Patent #:
Issue Dt:
08/13/2013
Application #:
13048170
Filing Dt:
03/15/2011
Publication #:
Pub Dt:
06/30/2011
Title:
HIGH-K METAL GATE CMOS
11
Patent #:
Issue Dt:
05/21/2013
Application #:
13048224
Filing Dt:
03/15/2011
Publication #:
Pub Dt:
09/20/2012
Title:
HIGH DENSITY SIX TRANSISTOR FINFET SRAM CELL LAYOUT
12
Patent #:
Issue Dt:
05/14/2013
Application #:
13048342
Filing Dt:
03/15/2011
Publication #:
Pub Dt:
09/20/2012
Title:
HORIZONTAL POLYSILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR
13
Patent #:
Issue Dt:
07/23/2013
Application #:
13048366
Filing Dt:
03/15/2011
Publication #:
Pub Dt:
09/20/2012
Title:
VERTICAL POLYSILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR
14
Patent #:
Issue Dt:
06/04/2013
Application #:
13048977
Filing Dt:
03/16/2011
Publication #:
Pub Dt:
09/20/2012
Title:
FULLY-DEPLETED SON
15
Patent #:
Issue Dt:
12/17/2013
Application #:
13049491
Filing Dt:
03/16/2011
Publication #:
Pub Dt:
09/20/2012
Title:
HYBRID MOSFET STRUCTURE HAVING DRAIN SIDE SCHOTTKY JUNCTION
16
Patent #:
Issue Dt:
06/05/2012
Application #:
13049933
Filing Dt:
03/17/2011
Title:
PROTECTING EXPOSED METAL GATE STRUCTURES FROM ETCHING PROCESSES IN INTEGRATED CIRCUIT MANUFACTURING
17
Patent #:
Issue Dt:
08/07/2012
Application #:
13050023
Filing Dt:
03/17/2011
Title:
INTEGRATION OF FIN-BASED DEVICES AND ETSOI DEVICES
18
Patent #:
Issue Dt:
10/30/2012
Application #:
13050052
Filing Dt:
03/17/2011
Publication #:
Pub Dt:
07/07/2011
Title:
STRUCTURE AND METHOD FOR IMPROVING STORAGE LATCH SUSCEPTIBILITY TO SINGLE EVENT UPSETS
19
Patent #:
Issue Dt:
08/20/2013
Application #:
13050101
Filing Dt:
03/17/2011
Publication #:
Pub Dt:
09/20/2012
Title:
FIN FIELD EFFECT TRANSISTOR WITH VARIABLE CHANNEL THICKNESS FOR THRESHOLD VOLTAGE TUNING
20
Patent #:
Issue Dt:
11/19/2013
Application #:
13050519
Filing Dt:
03/17/2011
Publication #:
Pub Dt:
07/07/2011
Title:
POLYMERIC MATERIAL, METHOD OF FORMING THE POLYMERIC MATERIAL, AND MEHTOD OF FORMING A THIN FILM USING THE POLYMERIC MATERIAL
21
Patent #:
Issue Dt:
07/23/2013
Application #:
13051510
Filing Dt:
03/18/2011
Publication #:
Pub Dt:
09/20/2012
Title:
DAMASCENE METAL GATE AND SHIELD STRUCTURE, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
22
Patent #:
Issue Dt:
09/10/2013
Application #:
13051707
Filing Dt:
03/18/2011
Publication #:
Pub Dt:
09/20/2012
Title:
NITRIDE GATE DIELECTRIC FOR GRAPHENE MOSFET
23
Patent #:
Issue Dt:
04/15/2014
Application #:
13052346
Filing Dt:
03/21/2011
Publication #:
Pub Dt:
09/27/2012
Title:
PASSIVE RESONATOR, A SYSTEM INCORPORATING THE PASSIVE RESONATOR FOR REAL-TIME INTRA-PROCESS MONITORING AND CONTROL AND AN ASSOCIATED METHOD
24
Patent #:
Issue Dt:
07/31/2012
Application #:
13052662
Filing Dt:
03/21/2011
Publication #:
Pub Dt:
07/14/2011
Title:
DESIGN STRUCTURE FOR INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS
25
Patent #:
Issue Dt:
08/11/2015
Application #:
13053803
Filing Dt:
03/22/2011
Publication #:
Pub Dt:
09/27/2012
Title:
WAFER EDGE CONDITIONING FOR THINNED WAFERS
26
Patent #:
Issue Dt:
01/27/2015
Application #:
13069411
Filing Dt:
03/23/2011
Publication #:
Pub Dt:
07/21/2011
Title:
LAYOUT DETERMINING FOR WIDE WIRE ON-CHIP INTERCONNECT LINES
27
Patent #:
Issue Dt:
07/02/2013
Application #:
13069653
Filing Dt:
03/23/2011
Publication #:
Pub Dt:
09/27/2012
Title:
PHASE PROFILE GENERATOR
28
Patent #:
Issue Dt:
10/23/2012
Application #:
13070568
Filing Dt:
03/24/2011
Publication #:
Pub Dt:
09/27/2012
Title:
SELF-ALIGNED DUAL DEPTH ISOLATION AND METHOD OF FABRICATION
29
Patent #:
NONE
Issue Dt:
Application #:
13071029
Filing Dt:
03/24/2011
Publication #:
Pub Dt:
09/27/2012
Title:
WAVEFORM-BASED DIGITAL GATE MODELING FOR TIMING ANALYSIS
30
Patent #:
NONE
Issue Dt:
Application #:
13071043
Filing Dt:
03/24/2011
Publication #:
Pub Dt:
09/27/2012
Title:
MAGNETIC TUNNEL JUNCTION WITH IRON DUSTING LAYER BETWEEN FREE LAYER AND TUNNEL BARRIER
31
Patent #:
Issue Dt:
07/24/2012
Application #:
13071894
Filing Dt:
03/25/2011
Publication #:
Pub Dt:
07/14/2011
Title:
REWORKABLE ELECTRONIC DEVICE ASSEMBLY AND METHOD
32
Patent #:
Issue Dt:
07/30/2013
Application #:
13071940
Filing Dt:
03/25/2011
Publication #:
Pub Dt:
08/11/2011
Title:
STRUCTURE AND METHOD TO ENHANCE BOTH NFET AND PFET PERFORMANCE USING DIFFERENT KINDS OF STRESSED LAYERS
33
Patent #:
Issue Dt:
08/14/2012
Application #:
13072023
Filing Dt:
03/25/2011
Publication #:
Pub Dt:
07/14/2011
Title:
ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD
34
Patent #:
Issue Dt:
06/04/2013
Application #:
13072859
Filing Dt:
03/28/2011
Publication #:
Pub Dt:
10/04/2012
Title:
METHOD, A PROGRAM STORAGE DEVICE AND A COMPUTER SYSTEM FOR MODELING THE TOTAL CONTACT RESISTANCE OF A SEMICONDUCTOR DEVICE HAVING A MULTI-FINGER GATE STRUCTURE
35
Patent #:
Issue Dt:
01/01/2013
Application #:
13073103
Filing Dt:
03/28/2011
Publication #:
Pub Dt:
10/04/2012
Title:
DRAM WITH SCHOTTKY BARRIER FET AND MIM TRENCH CAPACITOR
36
Patent #:
Issue Dt:
11/06/2012
Application #:
13073110
Filing Dt:
03/28/2011
Publication #:
Pub Dt:
10/04/2012
Title:
FABRICATION OF DEVICES HAVING DIFFERENT INTERFACIAL OXIDE THICKNESS VIA LATERAL OXIDATION
37
Patent #:
Issue Dt:
01/08/2013
Application #:
13073151
Filing Dt:
03/28/2011
Publication #:
Pub Dt:
10/04/2012
Title:
FORMING BORDERLESS CONTACT FOR TRANSISTORS IN A REPLACEMENT METAL GATE PROCESS
38
Patent #:
Issue Dt:
11/05/2013
Application #:
13073181
Filing Dt:
03/28/2011
Publication #:
Pub Dt:
10/04/2012
Title:
SELECTIVE ELECTROMIGRATION IMPROVEMENT FOR HIGH CURRENT C4S
39
Patent #:
Issue Dt:
06/18/2013
Application #:
13074854
Filing Dt:
03/29/2011
Publication #:
Pub Dt:
10/04/2012
Title:
SELF-ALIGNED III-V FIELD EFFECT TRANSISTOR (FET), INTEGRATED CIRCUIT (IC) CHIP WITH SELF-ALIGNED III-V FETS AND METHOD OF MANUFACTURE
40
Patent #:
Issue Dt:
03/13/2012
Application #:
13075271
Filing Dt:
03/30/2011
Publication #:
Pub Dt:
07/21/2011
Title:
DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY
41
Patent #:
Issue Dt:
08/27/2013
Application #:
13075443
Filing Dt:
03/30/2011
Publication #:
Pub Dt:
10/04/2012
Title:
STRUCTURE AND PROCESS FOR METAL FILL IN REPLACEMENT METAL GATE INTEGRATION
42
Patent #:
Issue Dt:
11/08/2011
Application #:
13075552
Filing Dt:
03/30/2011
Publication #:
Pub Dt:
07/21/2011
Title:
SOI BODY CONTACT USING E-DRAM TECHNOLOGY
43
Patent #:
Issue Dt:
04/09/2013
Application #:
13075657
Filing Dt:
03/30/2011
Publication #:
Pub Dt:
10/04/2012
Title:
LOW-TEMPERATURE IN-SITU REMOVAL OF OXIDE FROM A SILICON SURFACE DURING CMOS EPITAXIAL PROCESSING
44
Patent #:
Issue Dt:
11/04/2014
Application #:
13076192
Filing Dt:
03/30/2011
Publication #:
Pub Dt:
07/21/2011
Title:
METHOD AND APPARATUS FOR MANUFACTURING ELECTRONIC INTEGRATED CIRCUIT CHIP
45
Patent #:
Issue Dt:
04/09/2013
Application #:
13076781
Filing Dt:
03/31/2011
Publication #:
Pub Dt:
10/04/2012
Title:
TUNABLE SEMICONDUCTOR DEVICE
46
Patent #:
Issue Dt:
12/10/2013
Application #:
13077216
Filing Dt:
03/31/2011
Publication #:
Pub Dt:
07/28/2011
Title:
METHOD OF PLACING A SEMICONDUCTING NANOSTRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTING NANOSTRUCTURE
47
Patent #:
Issue Dt:
05/17/2016
Application #:
13077765
Filing Dt:
03/31/2011
Publication #:
Pub Dt:
10/04/2012
Title:
MULTI-CORE FIBER OPTICAL COUPLING ELEMENTS
48
Patent #:
NONE
Issue Dt:
Application #:
13078063
Filing Dt:
04/01/2011
Publication #:
Pub Dt:
10/04/2012
Title:
NOISE REDUCTION USING FEEDBACK TO A WIRE SPREADER ROUTER
49
Patent #:
Issue Dt:
07/23/2013
Application #:
13078305
Filing Dt:
04/01/2011
Publication #:
Pub Dt:
10/04/2012
Title:
MULTILAYERED LOW K CAP WITH CONFORMAL GAP FILL AND UV STABLE COMPRESSIVE STRESS PROPERTIES
50
Patent #:
Issue Dt:
01/21/2014
Application #:
13079842
Filing Dt:
04/05/2011
Publication #:
Pub Dt:
10/11/2012
Title:
Dynamically Tune Power Proxy Architectures
51
Patent #:
Issue Dt:
02/05/2013
Application #:
13080019
Filing Dt:
04/05/2011
Publication #:
Pub Dt:
10/11/2012
Title:
ELECTRICAL FUSE FORMED BY REPLACEMENT METAL GATE PROCESS
52
Patent #:
Issue Dt:
08/07/2012
Application #:
13080055
Filing Dt:
04/05/2011
Title:
DATA STRUCTURE FOR DESCRIBING MBIST ARCHITECTURE
53
Patent #:
Issue Dt:
07/09/2013
Application #:
13080084
Filing Dt:
04/05/2011
Publication #:
Pub Dt:
10/11/2012
Title:
Method of Removing High-K Dielectric Layer on Sidewalls of Gate Structure
54
Patent #:
Issue Dt:
02/26/2013
Application #:
13080105
Filing Dt:
04/05/2011
Publication #:
Pub Dt:
10/11/2012
Title:
SOLDER BALL CONTACT SUSCEPTIBLE TO LOWER STRESS
55
Patent #:
Issue Dt:
10/30/2012
Application #:
13080326
Filing Dt:
04/05/2011
Publication #:
Pub Dt:
07/28/2011
Title:
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME
56
Patent #:
Issue Dt:
06/11/2013
Application #:
13080352
Filing Dt:
04/05/2011
Publication #:
Pub Dt:
07/28/2011
Title:
CARRIER MOBILITY ENHANCED CHANNEL DEVICES AND METHOD OF MANUFACTURE
57
Patent #:
Issue Dt:
10/07/2014
Application #:
13080390
Filing Dt:
04/05/2011
Publication #:
Pub Dt:
10/11/2012
Title:
SEMICONDUCTOR NANOWIRE STRUCTURE REUSING SUSPENSION PADS
58
Patent #:
Issue Dt:
05/07/2013
Application #:
13080690
Filing Dt:
04/06/2011
Publication #:
Pub Dt:
10/11/2012
Title:
JUNCTION FIELD EFFECT TRANSISTOR WITH AN EPITAXIALLY GROWN GATE STRUCTURE
59
Patent #:
Issue Dt:
07/31/2012
Application #:
13080716
Filing Dt:
04/06/2011
Publication #:
Pub Dt:
07/28/2011
Title:
METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS
60
Patent #:
Issue Dt:
03/25/2014
Application #:
13080773
Filing Dt:
04/06/2011
Publication #:
Pub Dt:
10/13/2011
Title:
PROCESSING EXECUTION REQUESTS WITHIN DIFFERENT COMPUTING ENVIRONMENTS
61
Patent #:
Issue Dt:
09/24/2013
Application #:
13080799
Filing Dt:
04/06/2011
Publication #:
Pub Dt:
10/11/2012
Title:
MULTI-USE PHYSICAL ARCHITECTURE
62
Patent #:
Issue Dt:
05/07/2013
Application #:
13080962
Filing Dt:
04/06/2011
Publication #:
Pub Dt:
07/28/2011
Title:
DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS
63
Patent #:
NONE
Issue Dt:
Application #:
13082066
Filing Dt:
04/07/2011
Publication #:
Pub Dt:
10/11/2012
Title:
INTEGRATED CIRCUIT CHIP INCORPORATING A TEST CIRCUIT THAT ALLOWS FOR ON-CHIP STRESS TESTING IN ORDER TO MODEL OR MONITOR DEVICE PERFORMANCE DEGRADATION
64
Patent #:
Issue Dt:
03/19/2013
Application #:
13082440
Filing Dt:
04/08/2011
Publication #:
Pub Dt:
11/03/2011
Title:
METHOD AND SYSTEM FOR COMPUTING FOURIER SERIES COEFFICIENTS FOR MASK LAYOUTS USING FFT
65
Patent #:
Issue Dt:
02/19/2013
Application #:
13082786
Filing Dt:
04/08/2011
Publication #:
Pub Dt:
10/11/2012
Title:
REDUCTION OF ALERTS IN INFORMATION TECHNOLOGY SYSTEMS
66
Patent #:
Issue Dt:
05/28/2013
Application #:
13082867
Filing Dt:
04/08/2011
Publication #:
Pub Dt:
10/11/2012
Title:
STRUCTURE AND FABRICATION METHOD OF TUNNEL FIELD EFFECT TRANSISTOR WITH INCREASED DRIVE CURRENT AND REDUCED GATE INDUCED DRAIN LEAKAGE (GIDL)
67
Patent #:
NONE
Issue Dt:
Application #:
13083057
Filing Dt:
04/08/2011
Publication #:
Pub Dt:
11/03/2011
Title:
METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
68
Patent #:
Issue Dt:
10/22/2013
Application #:
13083631
Filing Dt:
04/11/2011
Publication #:
Pub Dt:
10/11/2012
Title:
INTEGRATED CIRCUIT STRUCTURE HAVING SUBSTANTIALLY PLANAR N-P STEP HEIGHT AND METHODS OF FORMING
69
Patent #:
Issue Dt:
05/28/2013
Application #:
13083803
Filing Dt:
04/11/2011
Publication #:
Pub Dt:
10/11/2012
Title:
THERMAL EXPANSION CONTROL EMPLOYING PLATELET FILLERS
70
Patent #:
Issue Dt:
03/25/2014
Application #:
13083879
Filing Dt:
04/11/2011
Publication #:
Pub Dt:
10/11/2012
Title:
SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SAME
71
Patent #:
Issue Dt:
11/10/2015
Application #:
13083893
Filing Dt:
04/11/2011
Publication #:
Pub Dt:
10/11/2012
Title:
SEMICONDUCTOR DEVICE EXHIBITING REDUCED PARASITICS AND METHOD FOR MAKING SAME
72
Patent #:
Issue Dt:
12/11/2012
Application #:
13084088
Filing Dt:
04/11/2011
Publication #:
Pub Dt:
08/04/2011
Title:
PORE PHASE CHANGE MATERIAL CELL FABRICATED FROM RECESSED PILLAR
73
Patent #:
Issue Dt:
02/25/2014
Application #:
13084435
Filing Dt:
04/11/2011
Publication #:
Pub Dt:
10/11/2012
Title:
ROBOTIC DEVICE FOR SUBSTRATE TRANSFER APPLICATIONS
74
Patent #:
Issue Dt:
09/16/2014
Application #:
13085511
Filing Dt:
04/13/2011
Publication #:
Pub Dt:
10/18/2012
Title:
Method And Structure For Compound Semiconductor Contact
75
Patent #:
Issue Dt:
02/19/2013
Application #:
13085632
Filing Dt:
04/13/2011
Publication #:
Pub Dt:
08/04/2011
Title:
ELECTRICALLY PROGRAMMABLE FUSE AND FABRICATION METHOD
76
Patent #:
Issue Dt:
08/27/2013
Application #:
13085717
Filing Dt:
04/13/2011
Publication #:
Pub Dt:
08/04/2011
Title:
OPTICAL COUPLING METHOD
77
Patent #:
Issue Dt:
06/16/2015
Application #:
13085970
Filing Dt:
04/13/2011
Publication #:
Pub Dt:
10/18/2012
Title:
PASSIVE DEVICES FABRICATED ON GLASS SUBSTRATES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
78
Patent #:
Issue Dt:
07/29/2014
Application #:
13086428
Filing Dt:
04/14/2011
Publication #:
Pub Dt:
10/18/2012
Title:
PLACEMENT OF STRUCTURED NETS
79
Patent #:
Issue Dt:
04/08/2014
Application #:
13086459
Filing Dt:
04/14/2011
Publication #:
Pub Dt:
10/18/2012
Title:
MOSFET with Recessed channel FILM and Abrupt Junctions
80
Patent #:
NONE
Issue Dt:
Application #:
13087449
Filing Dt:
04/15/2011
Publication #:
Pub Dt:
10/18/2012
Title:
REINFORCED VIA FARM INTERCONNECT STRUCTURE, A METHOD OF FORMING A REINFORCED VIA FARM INTERCONNECT STRUCTURE AND A METHOD OF REDESIGNING AN INTEGRATED CIRCUIT CHIP TO INCLUDE SUCH A REINFORCED VIA FARM INTERCONNECT STRUCTURE
81
Patent #:
Issue Dt:
09/24/2013
Application #:
13087464
Filing Dt:
04/15/2011
Publication #:
Pub Dt:
10/18/2012
Title:
BONDING CONTROLLER GUIDED ASSESSMENT AND OPTIMIZATIONFOR CHIP-TO-CHIP STACKING
82
Patent #:
NONE
Issue Dt:
Application #:
13087915
Filing Dt:
04/15/2011
Publication #:
Pub Dt:
10/18/2012
Title:
METHOD OF MANUFACTURE OF VERTICAL SUBSTRATE DIODE
83
Patent #:
Issue Dt:
06/09/2015
Application #:
13088054
Filing Dt:
04/15/2011
Publication #:
Pub Dt:
10/18/2012
Title:
INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING ON-CHIP INTERCONNECT STRUCTURES BY IMAGE REVERSAL
84
Patent #:
Issue Dt:
12/02/2014
Application #:
13088083
Filing Dt:
04/15/2011
Publication #:
Pub Dt:
10/18/2012
Title:
METHOD FOR FORMING SELF-ALIGNED AIRGAP INTERCONNECT STRUCTURES
85
Patent #:
Issue Dt:
11/18/2014
Application #:
13088110
Filing Dt:
04/15/2011
Publication #:
Pub Dt:
10/18/2012
Title:
MIDDLE OF LINE STRUCTURES
86
Patent #:
Issue Dt:
03/06/2012
Application #:
13088339
Filing Dt:
04/16/2011
Publication #:
Pub Dt:
08/11/2011
Title:
TECHNIQUES FOR THREE-DIMENSIONAL CIRCUIT INTEGRATION
87
Patent #:
Issue Dt:
09/03/2013
Application #:
13088376
Filing Dt:
04/17/2011
Publication #:
Pub Dt:
10/18/2012
Title:
SOI DEVICE WITH DTI AND STI
88
Patent #:
Issue Dt:
12/09/2014
Application #:
13088663
Filing Dt:
04/18/2011
Publication #:
Pub Dt:
10/18/2012
Title:
SEMICONDUCTOR STRUCTURES WITH DUAL TRENCH REGIONS AND METHODS OF MANUFACTURING THE SEMICONDUCTOR STRUCTURES
89
Patent #:
Issue Dt:
12/10/2013
Application #:
13088688
Filing Dt:
04/18/2011
Publication #:
Pub Dt:
10/18/2012
Title:
DELAY MODEL CONSTRUCTION IN THE PRESENCE OF MULTIPLE INPUT SWITCHING EVENTS
90
Patent #:
Issue Dt:
03/20/2012
Application #:
13088727
Filing Dt:
04/18/2011
Publication #:
Pub Dt:
08/11/2011
Title:
MICRO-FLUIDIC INJECTION MOLDED SOLDER (IMS)
91
Patent #:
Issue Dt:
02/04/2014
Application #:
13088766
Filing Dt:
04/18/2011
Publication #:
Pub Dt:
10/18/2012
Title:
GRAPHENE NANORIBBONS AND CARBON NANOTUBES FABRICATED FROM SIC FINS OR NANOWIRE TEMPLATES
92
Patent #:
NONE
Issue Dt:
Application #:
13089234
Filing Dt:
04/18/2011
Publication #:
Pub Dt:
08/11/2011
Title:
Charge Carrier Barrier for Image Sensor
93
Patent #:
Issue Dt:
08/26/2014
Application #:
13091275
Filing Dt:
04/21/2011
Publication #:
Pub Dt:
10/25/2012
Title:
INDEPENDENTLY VOLTAGE CONTROLLED VOLUME OF SILICON ON A SILICON ON INSULATOR CHIP
94
Patent #:
Issue Dt:
09/03/2013
Application #:
13091292
Filing Dt:
04/21/2011
Publication #:
Pub Dt:
10/25/2012
Title:
EDRAM HAVING DYNAMIC RETENTION AND PERFORMANCE TRADEOFF
95
Patent #:
Issue Dt:
12/10/2013
Application #:
13092247
Filing Dt:
04/22/2011
Publication #:
Pub Dt:
10/25/2012
Title:
RESONANCE NANOELECTROMECHANICAL SYSTEMS
96
Patent #:
Issue Dt:
04/02/2013
Application #:
13092304
Filing Dt:
04/22/2011
Publication #:
Pub Dt:
10/25/2012
Title:
Enhancing Redundancy Removal with Early Merging
97
Patent #:
Issue Dt:
08/27/2013
Application #:
13092424
Filing Dt:
04/22/2011
Publication #:
Pub Dt:
10/25/2012
Title:
SELF-SEALED FLUIDIC CHANNELS FOR NANOPORE ARRAY
98
Patent #:
Issue Dt:
07/09/2013
Application #:
13093034
Filing Dt:
04/25/2011
Publication #:
Pub Dt:
08/11/2011
Title:
SILICON-ON-INSULATOR SUBSTRATE WITH BUILT-IN SUBSTRATE JUNCTION
99
Patent #:
Issue Dt:
09/30/2014
Application #:
13095099
Filing Dt:
04/27/2011
Publication #:
Pub Dt:
11/03/2011
Title:
INTEGRATED CIRCUIT DESIGN AND SIMULATION
100
Patent #:
Issue Dt:
08/21/2012
Application #:
13095577
Filing Dt:
04/27/2011
Publication #:
Pub Dt:
08/18/2011
Title:
NONVOLATIVE MEMORY DEVICE USING SEMICONDUCTOR NANOCRYSTALS AND METHOD OF FORMING SAME
Assignors
1
Exec Dt:
09/10/2015
2
Exec Dt:
09/10/2015
Assignee
1
PO BOX 309
UGLAND HOUSE
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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