|
|
Patent #:
|
|
Issue Dt:
|
06/22/2010
|
Application #:
|
11417160
|
Filing Dt:
|
05/04/2006
|
Publication #:
|
|
Pub Dt:
|
11/08/2007
| | | | |
Title:
|
METHOD AND APPARATUS PROVIDING MULTIPLE TRANSFER GATE CONTROL LINES PER PIXEL FOR AUTOMATIC EXPOSURE CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
11417389
|
Filing Dt:
|
05/03/2006
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR OPTIMIZING INTERCONNECTIONS OF COMPONENTS IN A MULTICHIP MEMORY MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
11417390
|
Filing Dt:
|
05/03/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
SYNCHRONOUS CLOCK GENERATOR INCLUDING DUTY CYCLE CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
11417573
|
Filing Dt:
|
05/04/2006
|
Publication #:
|
|
Pub Dt:
|
11/08/2007
| | | | |
Title:
|
METHOD FOR READING A MULTILEVEL CELL IN A NON-VOLATILE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2008
|
Application #:
|
11417577
|
Filing Dt:
|
05/04/2006
|
Publication #:
|
|
Pub Dt:
|
11/08/2007
| | | | |
Title:
|
MIMICKING PROGRAM VERIFY DRAIN RESISTANCE IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
11417620
|
Filing Dt:
|
05/03/2006
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
LEADFRAME ALTERATION TO DIRECT COMPOUND FLOW INTO PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2009
|
Application #:
|
11418170
|
Filing Dt:
|
05/04/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
METHODS FOR FORMING INTERCONNECTS IN MICROELECTRONIC WORKPIECES AND MICROELECTRONIC WORKPIECES FORMED USING SUCH METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
11418337
|
Filing Dt:
|
05/04/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
METHODS AND SYSTEMS FOR CONTROLLING TEMPERATURE DURING MICROFEATURE WORKPIECE PROCESSING, E.G. CVD DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2009
|
Application #:
|
11418556
|
Filing Dt:
|
05/05/2006
|
Publication #:
|
|
Pub Dt:
|
09/21/2006
| | | | |
Title:
|
METHODS OF FORMING GATELINES AND TRANSISTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11418582
|
Filing Dt:
|
05/04/2006
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11418724
|
Filing Dt:
|
05/03/2006
|
Publication #:
|
|
Pub Dt:
|
11/08/2007
| | | | |
Title:
|
METHODS OF PROVIDING SEMICONDUCTOR COMPONENTS WITHIN SOCKETS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2009
|
Application #:
|
11418897
|
Filing Dt:
|
05/04/2006
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR AN ASYNCHRONOUS DATA BUFFER HAVING BUFFER WRITE AND READ POINTERS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
11419173
|
Filing Dt:
|
05/18/2006
|
Publication #:
|
|
Pub Dt:
|
11/22/2007
| | | | |
Title:
|
METHOD AND DEVICE TO VARY GROWTH RATE OF THIN FILMS OVER SEMICONDUCTOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
11419261
|
Filing Dt:
|
05/19/2006
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2012
|
Application #:
|
11421399
|
Filing Dt:
|
05/31/2006
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
DYNAMIC ARRAYS AND OVERLAYS WITH BOUNDS POLICIES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
11421614
|
Filing Dt:
|
06/01/2006
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
ANTIFUSE PROGRAMMING CIRCUIT WITH SNAPBACK SELECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2009
|
Application #:
|
11423075
|
Filing Dt:
|
06/08/2006
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
METHOD AND DEVICE FOR CHECKING LITHOGRAPHY DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2009
|
Application #:
|
11423082
|
Filing Dt:
|
06/08/2006
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
METHOD AND DEVICE FOR CHECKING LITHOGRAPHY DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2009
|
Application #:
|
11423197
|
Filing Dt:
|
06/09/2006
|
Publication #:
|
|
Pub Dt:
|
12/13/2007
| | | | |
Title:
|
METHOD OF FORMING A LAYER OF MATERIAL USING AN ATOMIC LAYER DEPOSITION PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2011
|
Application #:
|
11424394
|
Filing Dt:
|
06/15/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
SEMICONDUCTOR CONTACT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2009
|
Application #:
|
11424401
|
Filing Dt:
|
06/15/2006
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
Title:
|
RESISTIVE HEATER FOR THERMO OPTIC DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
11426523
|
Filing Dt:
|
06/26/2006
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
GATE DIELECTRIC ANTIFUSE CIRCUIT TO PROTECT A HIGH-VOLTAGE TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
11426768
|
Filing Dt:
|
06/27/2006
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
ETCH MASK AND METHOD OF FORMING A MAGNETIC RANDOM ACCESS MEMORY STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2009
|
Application #:
|
11427038
|
Filing Dt:
|
06/28/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
WRITE ONCE READ ONLY MEMORY EMPLOYING CHARGE TRAPPING IN INSULATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
11427569
|
Filing Dt:
|
06/29/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
LANTHANIDE DOPED TIOX DIELECTRIC FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2008
|
Application #:
|
11428620
|
Filing Dt:
|
07/05/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE HAVING ELECTRICALLY DISCONNECTED SOLDER BALLS FOR MOUNTING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
11428625
|
Filing Dt:
|
07/05/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE HAVING ELECTRICALLY DISCONNECTED SOLDER BALLS FOR MOUNTING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11428959
|
Filing Dt:
|
07/06/2006
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
Title:
|
EPITAXIAL SEMICONDUCTOR LAYER AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
11429030
|
Filing Dt:
|
05/04/2006
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
DYNAMIC VOLUME MANAGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2009
|
Application #:
|
11429293
|
Filing Dt:
|
05/04/2006
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
METHOD AND SYSTEM FOR TRANSFERRING DATA TO AN ELECTRONIC TOY OR OTHER ELECTRONIC DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
11429856
|
Filing Dt:
|
05/08/2006
|
Publication #:
|
|
Pub Dt:
|
09/07/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR INITIALIZATION OF READ LATENCY TRACKING CIRCUIT IN HIGH-SPEED DRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
11430046
|
Filing Dt:
|
05/09/2006
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
METHOD OF FORMING NON-VOLATILE RESISTANCE VARIABLE DEVICES AND METHOD OF FORMING A PROGRAMMABLE MEMORY CELL OF MEMORY CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2009
|
Application #:
|
11430047
|
Filing Dt:
|
05/09/2006
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
METHOD OF MANUFACTURE OF A PCRAM MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
11430138
|
Filing Dt:
|
05/09/2006
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
Title:
|
MAGNETIC MEMORY HAVING SYNTHETIC ANTIFERROMAGNETIC PINNED LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
11430339
|
Filing Dt:
|
05/09/2006
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
DATA COMPRESSION READ MODE FOR MEMORY TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11430375
|
Filing Dt:
|
05/08/2006
|
Publication #:
|
|
Pub Dt:
|
09/21/2006
| | | | |
Title:
|
SUPPORT ELEMENTS FOR SEMICONDUCTOR DEVICES WITH PERIPHERALLY LOCATED BOND PADS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
11430379
|
Filing Dt:
|
05/08/2006
|
Title:
|
SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION DURING EXTENDED REFRESH PERIODS OF DYNAMIC RANDOM ACCESS MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2008
|
Application #:
|
11430470
|
Filing Dt:
|
05/08/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
INPUT AND OUTPUT BUFFERS HAVING SYMMETRICAL OPERATING CHARACTERISTICS AND IMMUNITY FROM VOLTAGE VARIATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
11430471
|
Filing Dt:
|
05/08/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR REDUCED POWER OPEN-LOOP SYNTHESIS OF OUTPUT CLOCK SIGNALS HAVING A SELECTED PHASE RELATIVE TO AN INPUT CLOCK SIGNAL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2009
|
Application #:
|
11430483
|
Filing Dt:
|
05/09/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
METHODS FOR PACKAGING MICROFEATURE DEVICES AND MICROFEATURE DEVICES FORMED BY SUCH METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
11430540
|
Filing Dt:
|
05/08/2006
|
Publication #:
|
|
Pub Dt:
|
11/08/2007
| | | | |
Title:
|
SUBSTRATES, SYSTEMS, AND DEVICES INCLUDING STRUCTURES FOR SUPPRESSING POWER AND GROUND PLANE NOISE, AND METHODS FOR SUPPRESSING POWER AND GROUND PLANE NOISE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
11430549
|
Filing Dt:
|
05/09/2006
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
DATA COMPRESSION READ MODE FOR MEMORY TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
11430550
|
Filing Dt:
|
05/09/2006
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
Title:
|
DATA COMPRESSION READ MODE FOR MEMORY TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
11430735
|
Filing Dt:
|
05/09/2006
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
Title:
|
MICROELECTRONIC DEVICES HAVING VIAS, AND PACKAGED MICROELECTRONIC DEVICES HAVING VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2007
|
Application #:
|
11430792
|
Filing Dt:
|
05/09/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
SILICON RICH BARRIER LAYERS FOR INTEGRATED CIRCUIT DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
11431269
|
Filing Dt:
|
05/10/2006
|
Publication #:
|
|
Pub Dt:
|
11/15/2007
| | | | |
Title:
|
METHODS OF MAKING SELF-ALIGNED NANO-STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2010
|
Application #:
|
11431509
|
Filing Dt:
|
05/11/2006
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A CYLINDRICAL CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
|
Application #:
|
11431958
|
Filing Dt:
|
05/10/2006
|
Publication #:
|
|
Pub Dt:
|
11/15/2007
| | | | |
Title:
|
ELECTRICAL COMPONENTS FOR MICROELECTRONIC DEVICES AND METHODS OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2009
|
Application #:
|
11432009
|
Filing Dt:
|
05/10/2006
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
Title:
|
LOW POWER COST-EFFECTIVE ECC MEMORY SYSTEM AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2010
|
Application #:
|
11432013
|
Filing Dt:
|
05/10/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR OPTIMIZING INTERCONNECTIONS OF MEMORY DEVICES IN A MULTICHIP MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11432015
|
Filing Dt:
|
05/10/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR MULTIPLE BIT OPTICAL DATA TRANSMISSION IN MEMORY SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11432016
|
Filing Dt:
|
05/10/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
METHOD AND SYSTEM FOR REDUCING MISMATCH BETWEEN REFERENCE AND INTENSITY PATHS IN ANALOG TO DIGITAL CONVERTERS IN CMOS ACTIVE PIXEL SENSORS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2009
|
Application #:
|
11432017
|
Filing Dt:
|
05/10/2006
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR TRANSMITTING DATA PACKETS IN A COMPUTER SYSTEM HAVING A MEMORY HUB ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
11432018
|
Filing Dt:
|
05/10/2006
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR COMMUNICATING THE SYNCHRONIZATION STATUS OF MEMORY MODULES DURING INITIALIZATION OF THE MEMORY MODULES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2009
|
Application #:
|
11432019
|
Filing Dt:
|
05/11/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
MULTI-STATE MEMORY CELL WITH ASYMMETRIC CHARGE TRAPPING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
11432060
|
Filing Dt:
|
05/10/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR READ SYNCHRONIZATION OF MEMORY MODULES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2008
|
Application #:
|
11432135
|
Filing Dt:
|
05/11/2006
|
Publication #:
|
|
Pub Dt:
|
11/15/2007
| | | | |
Title:
|
NAND ARCHITECTURE MEMORY DEVICES AND OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
11432238
|
Filing Dt:
|
05/10/2006
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
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Title:
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MULTI-PHASE CLOCK SIGNAL GENERATOR AND METHOD HAVING INHERENTLY UNLIMITED FREQUENCY CAPABILITY
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Patent #:
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Issue Dt:
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08/30/2011
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Application #:
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11432270
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Filing Dt:
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05/11/2006
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Publication #:
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Pub Dt:
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11/15/2007
| | | | |
Title:
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DUAL WORK FUNCTION RECESSED ACCESS DEVICE AND METHODS OF FORMING
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Patent #:
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Issue Dt:
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07/20/2010
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Application #:
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11432301
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Filing Dt:
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05/10/2006
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Publication #:
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Pub Dt:
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01/18/2007
| | | | |
Title:
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FLASH MEMORY DEVICE WITH IMPROVED MANAGEMENT OF PROTECTION INFORMATION
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Patent #:
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Issue Dt:
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10/30/2007
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Application #:
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11432334
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Filing Dt:
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05/12/2006
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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SEMICONDUCTOR DEVICE HAVING A MODULE BOARD
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Patent #:
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Issue Dt:
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04/07/2009
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Application #:
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11432421
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Filing Dt:
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05/10/2006
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Publication #:
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Pub Dt:
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11/15/2007
| | | | |
Title:
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METHOD AND APPARATUS FOR OUTPUT DRIVER CALIBRATION
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Patent #:
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Issue Dt:
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01/27/2009
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Application #:
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11432578
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Filing Dt:
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05/11/2006
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Publication #:
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Pub Dt:
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09/21/2006
| | | | |
Title:
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MICROMECHANICAL STRAINED SEMICONDUCTOR BY WAFER BONDING
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Patent #:
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Issue Dt:
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03/16/2010
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Application #:
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11432739
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Filing Dt:
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05/11/2006
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Publication #:
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Pub Dt:
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09/14/2006
| | | | |
Title:
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INTERMEDIATE SEMICONDUCTOR DEVICE STRUCTURES USING PHOTOPATTERNABLE, DIELECTRIC MATERIALS
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Patent #:
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Issue Dt:
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03/22/2011
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Application #:
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11433015
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Filing Dt:
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05/12/2006
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Publication #:
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Pub Dt:
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11/15/2007
| | | | |
Title:
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METHOD OF FABRICATING MICROELECTRONIC DEVICES
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Patent #:
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Issue Dt:
|
05/05/2009
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Application #:
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11433131
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Filing Dt:
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05/11/2006
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Publication #:
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Pub Dt:
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09/28/2006
| | | | |
Title:
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METHOD AND SYSTEM FOR SYNCHRONIZING COMMUNICATIONS LINKS IN A HUB-BASED MEMORY SYSTEM
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Patent #:
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Issue Dt:
|
12/25/2007
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Application #:
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11433182
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Filing Dt:
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05/11/2006
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Publication #:
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Pub Dt:
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09/14/2006
| | | | |
Title:
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LOW SUPPLY VOLTAGE TEMPERATURE COMPENSATED REFERENCE VOLTAGE GENERATOR AND METHOD
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|
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Patent #:
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Issue Dt:
|
08/21/2007
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Application #:
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11433216
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Filing Dt:
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05/11/2006
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Publication #:
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Pub Dt:
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09/14/2006
| | | | |
Title:
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SYSTEM AND METHOD FOR OPEN-LOOP SYNTHESIS OF OUTPUT CLOCK SIGNALS HAVING A SELECTED PHASE RELATIVE TO AN INPUT CLOCK SIGNAL
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|
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Patent #:
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Issue Dt:
|
12/02/2008
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Application #:
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11433217
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Filing Dt:
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05/11/2006
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Publication #:
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Pub Dt:
|
09/14/2006
| | | | |
Title:
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MEMORY SYSTEM AND METHOD HAVING SELECTIVE ECC DURING LOW POWER REFRESH
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Patent #:
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Issue Dt:
|
01/27/2009
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Application #:
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11433220
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Filing Dt:
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05/11/2006
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Publication #:
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Pub Dt:
|
09/28/2006
| | | | |
Title:
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SYSTEM AND METHOD FOR TESTING A MEMORY FOR A MEMORY FAILURE EXHIBITED BY A FAILING MEMORY
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|
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Patent #:
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|
Issue Dt:
|
06/29/2010
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Application #:
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11433322
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Filing Dt:
|
05/11/2006
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Publication #:
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Pub Dt:
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09/14/2006
| | | | |
Title:
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METHOD AND SYSTEM FOR GENERATING REFERENCE VOLTAGES FOR SIGNAL RECEIVERS
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|
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Patent #:
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Issue Dt:
|
03/23/2010
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Application #:
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11433324
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Filing Dt:
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05/11/2006
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Publication #:
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Pub Dt:
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11/15/2007
| | | | |
Title:
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METHODS OF FORMING TRENCH ISOLATION AND METHODS OF FORMING ARRAYS OF FLASH MEMORY CELLS
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|
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Patent #:
|
|
Issue Dt:
|
02/10/2009
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Application #:
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11433341
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Filing Dt:
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05/12/2006
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Publication #:
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Pub Dt:
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11/15/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR GENERATING READ AND VERIFY OPERATIONS IN NON-VOLATILE MEMORIES
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|
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Patent #:
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|
Issue Dt:
|
07/13/2010
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Application #:
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11433383
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Filing Dt:
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05/15/2006
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Publication #:
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Pub Dt:
|
09/28/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR REDUCING IMAGER FLOATING DIFFUSION LEAKAGE
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|
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Patent #:
|
|
Issue Dt:
|
08/16/2011
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Application #:
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11433384
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Filing Dt:
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05/15/2006
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Publication #:
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Pub Dt:
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11/15/2007
| | | | |
Title:
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METHOD FOR FORMING A FLOATING GATE USING CHEMICAL MECHANICAL PLANARIZATION
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|
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Patent #:
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|
Issue Dt:
|
08/11/2009
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Application #:
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11433533
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Filing Dt:
|
05/12/2006
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Publication #:
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Pub Dt:
|
11/15/2007
| | | | |
Title:
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NON-PLANAR TRANSISTOR AND TECHNIQUES FOR FABRICATING THE SAME
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|
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Patent #:
|
|
Issue Dt:
|
02/16/2010
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Application #:
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11433562
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Filing Dt:
|
05/15/2006
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Publication #:
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Pub Dt:
|
11/15/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR PROGRAMMING FLASH MEMORY
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|
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Patent #:
|
|
Issue Dt:
|
02/26/2008
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Application #:
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11434475
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Filing Dt:
|
05/15/2006
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Publication #:
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Pub Dt:
|
09/14/2006
| | | | |
Title:
|
SEMICONDUCTOR COMPONENT HAVING STIFFENER, CIRCUIT DECAL AND TERMINAL CONTACTS
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|
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Patent #:
|
|
Issue Dt:
|
09/18/2007
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Application #:
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11434497
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Filing Dt:
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05/15/2006
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Publication #:
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Pub Dt:
|
01/25/2007
| | | | |
Title:
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USE OF NON-VOLATILE MEMORY TO PERFORM ROLLBACK FUNCTION
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|
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Patent #:
|
|
Issue Dt:
|
04/28/2009
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Application #:
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11434564
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Filing Dt:
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05/15/2006
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Publication #:
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Pub Dt:
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11/30/2006
| | | | |
Title:
|
ROW DECODER CIRCUIT AND RELATED SYSTEM AND METHOD
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|
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Patent #:
|
|
Issue Dt:
|
04/10/2012
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Application #:
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11434982
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Filing Dt:
|
05/16/2006
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Publication #:
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Pub Dt:
|
11/22/2007
| | | | |
Title:
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METHODS FOR FILLING TRENCHES IN A SEMICONDUCTOR MATERIAL
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|
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Patent #:
|
|
Issue Dt:
|
09/25/2007
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Application #:
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11435421
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Filing Dt:
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05/17/2006
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Publication #:
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Pub Dt:
|
10/19/2006
| | | | |
Title:
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SCALABLE HIGH DENSITY NON-VOLATILE MEMORY CELLS IN A CONTACTLESS MEMORY ARRAY
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|
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Patent #:
|
|
Issue Dt:
|
08/12/2008
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Application #:
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11435620
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Filing Dt:
|
05/17/2006
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Publication #:
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Pub Dt:
|
09/21/2006
| | | | |
Title:
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IN-SERVICE RECONFIGURABLE DRAM AND FLASH MEMORY DEVICE
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|
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Patent #:
|
|
Issue Dt:
|
04/15/2008
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Application #:
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11435621
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Filing Dt:
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05/17/2006
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Publication #:
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Pub Dt:
|
10/05/2006
| | | | |
Title:
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IN-SERVICE RECONFIGURABLE DRAM AND FLASH MEMORY DEVICE
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|
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Patent #:
|
|
Issue Dt:
|
12/27/2011
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Application #:
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11435813
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Filing Dt:
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05/18/2006
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Publication #:
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Pub Dt:
|
09/14/2006
| | | | |
Title:
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ISOLATION STRUCTURE FOR A MEMORY CELL USING AL2O3 DIELECTRIC
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|
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Patent #:
|
|
Issue Dt:
|
03/13/2007
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Application #:
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11436247
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Filing Dt:
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05/18/2006
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Publication #:
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Pub Dt:
|
09/21/2006
| | | | |
Title:
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NON-PLANAR FLASH MEMORY HAVING SHIELDING BETWEEN FLOATING GATES
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|
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Patent #:
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Issue Dt:
|
08/12/2008
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Application #:
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11436323
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Filing Dt:
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05/18/2006
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Publication #:
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Pub Dt:
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11/22/2007
| | | | |
Title:
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PROGRAMMING A NON-VOLATILE MEMORY DEVICE
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|
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Patent #:
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Issue Dt:
|
07/07/2009
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Application #:
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11436352
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Filing Dt:
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05/18/2006
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Publication #:
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Pub Dt:
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11/22/2007
| | | | |
Title:
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NAND SYSTEM WITH A DATA WRITE FREQUENCY GREATER THAN A COMMAND-AND-ADDRESS-LOAD FREQUENCY
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|
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Patent #:
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Issue Dt:
|
09/09/2008
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Application #:
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11436726
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Filing Dt:
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05/17/2006
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Publication #:
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Pub Dt:
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11/22/2007
| | | | |
Title:
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METHOD OF FORMING GATE ARRAYS ON A PARTIAL SOI SUBSTRATE
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|
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Patent #:
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Issue Dt:
|
03/17/2009
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Application #:
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11436863
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Filing Dt:
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05/17/2006
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Publication #:
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Pub Dt:
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11/22/2007
| | | | |
Title:
|
LOW VOLTAGE SENSE AMPLIFIER AND SENSING METHOD
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|
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Patent #:
|
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Issue Dt:
|
04/20/2010
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Application #:
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11436864
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Filing Dt:
|
05/17/2006
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Publication #:
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Pub Dt:
|
12/06/2007
| | | | |
Title:
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APPARATUS AND METHOD FOR REDUCED PEAK POWER CONSUMPTION DURING COMMON OPERATION OF MULTI-NAND FLASH MEMORY DEVICES
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|
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Patent #:
|
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Issue Dt:
|
04/24/2007
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Application #:
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11437040
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Filing Dt:
|
05/19/2006
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Publication #:
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Pub Dt:
|
09/21/2006
| | | | |
Title:
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SYNCHRONOUS CLOCK GENERATOR INCLUDING DUTY CYCLE CORRECTION
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|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
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Application #:
|
11437268
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Filing Dt:
|
05/19/2006
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Publication #:
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Pub Dt:
|
03/29/2007
| | | | |
Title:
|
CHARGE-PUMP TYPE, VOLTAGE-BOOSTING DEVICE WITH REDUCED RIPPLE, IN PARTICULAR FOR NON-VOLATILE FLASH MEMORIES
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|
|
Patent #:
|
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Issue Dt:
|
04/29/2008
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Application #:
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11437397
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Filing Dt:
|
05/18/2006
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Publication #:
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Pub Dt:
|
09/21/2006
| | | | |
Title:
|
MICROELECTRONIC COMPONENT ASSEMBLIES WITH RECESSED WIRE BONDS AND METHODS OF MAKING SAME
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|
|
Patent #:
|
|
Issue Dt:
|
04/21/2009
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Application #:
|
11437405
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Filing Dt:
|
05/19/2006
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Publication #:
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Pub Dt:
|
03/08/2007
| | | | |
Title:
|
HIGH-VOLTAGE SWITCH WITH LOW OUTPUT RIPPLE FOR NON-VOLATILE FLOATING-GATE MEMORIES
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|
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Patent #:
|
|
Issue Dt:
|
08/10/2010
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Application #:
|
11437706
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Filing Dt:
|
05/22/2006
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Publication #:
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Pub Dt:
|
11/22/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR PROVIDING A NON-VOLATILE MEMORY WITH REDUCED CELL CAPACITIVE COUPLING
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|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
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Application #:
|
11437999
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Filing Dt:
|
05/18/2006
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Publication #:
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Pub Dt:
|
09/21/2006
| | | | |
Title:
|
METHODS OF REDUCING FLOATING BODY EFFECT
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|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11438419
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Filing Dt:
|
05/23/2006
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Publication #:
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Pub Dt:
|
03/01/2007
| | | | |
Title:
|
VERTICAL WRAP-AROUND-GATE FIELD-EFFECT-TRANSISTOR FOR HIGH DENSITY, LOW VOLTAGE LOGIC AND MEMORY ARRAY
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|
|
Patent #:
|
|
Issue Dt:
|
09/28/2010
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Application #:
|
11438771
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Filing Dt:
|
05/23/2006
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Publication #:
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Pub Dt:
|
10/05/2006
| | | | |
Title:
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DEVICE HAVING CONDUCTIVE MATERIAL DISPOSED IN A CAVITY FORMED IN AN ISOLATION OXIDE DISPOSED IN A TRENCH
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2010
|
Application #:
|
11438978
|
Filing Dt:
|
05/23/2006
|
Publication #:
|
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Pub Dt:
|
09/28/2006
| | | | |
Title:
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BALLISTIC DIRECT INJECTION NROM CELL ON STRAINED SILICON STRUCTURES
|
|