|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
13096361
|
Filing Dt:
|
04/28/2011
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
LOGIC MODIFICATION SYNTHESIS FOR HIGH PERFORMANCE CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
13096811
|
Filing Dt:
|
04/28/2011
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
Title:
|
EQUALIZER COMPUTATION IN A MEDIA SYSTEM USING A DATA SET SEPARATOR SEQUENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2014
|
Application #:
|
13096850
|
Filing Dt:
|
04/28/2011
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
TAPERED VIA AND MIM CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13097171
|
Filing Dt:
|
04/29/2011
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
VERIFYING DATA INTENSIVE STATE TRANSITION MACHINES RELATED APPLICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
13097193
|
Filing Dt:
|
04/29/2011
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
MODEL CHECKING IN STATE TRANSITION MACHINE VERIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13097307
|
Filing Dt:
|
04/29/2011
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
Title:
|
METHOD FOR FABRICATION OF CRYSTALLINE DIODES FOR RESISTIVE MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13097402
|
Filing Dt:
|
04/29/2011
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
DATA ENCODING IN SOLID-STATE STORAGE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
13097459
|
Filing Dt:
|
04/29/2011
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
METHOD OF FORMING SILICIDE CONTACTS OF DIFFERENT SHAPES SELECTIVELY ON REGIONS OF A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13097465
|
Filing Dt:
|
04/29/2011
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
Title:
|
SEMICONDUCTOR PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13097712
|
Filing Dt:
|
04/29/2011
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
Nanostructured Organosilicates from Thermally Curable Block Copolymers
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13098044
|
Filing Dt:
|
04/29/2011
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
ANOMALY DETECTION, FORECASTING AND ROOT CAUSE ANALYSIS OF ENERGY CONSUMPTION FOR A PORTFOLIO OF BUILDINGS USING MULTI-STEP STATISTICAL MODELING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
13098143
|
Filing Dt:
|
04/29/2011
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13098723
|
Filing Dt:
|
05/02/2011
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
Title:
|
TEST METHOD FOR DETERMINING RETICLE TRANSMISSION STABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13098816
|
Filing Dt:
|
05/02/2011
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
BUFFER PAD IN SOLDER BUMP CONNECTIONS AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13099276
|
Filing Dt:
|
05/02/2011
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
Title:
|
CONTROLLING AN ELECTRIC MOTOR BY DYNAMIC SWITCHING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13099358
|
Filing Dt:
|
05/03/2011
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
Calibration Assembly for Aide in Detection of Analytes with Electromagnetic Read-Write Heads
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
13099406
|
Filing Dt:
|
05/03/2011
|
Publication #:
|
|
Pub Dt:
|
09/01/2011
| | | | |
Title:
|
ASYMMETRIC SOURCE AND DRAIN STRESSOR REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13099767
|
Filing Dt:
|
05/03/2011
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
DECOUPLING CAPACITOR INSERTION USING HYPERGRAPH CONNECTIVITY ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
13099790
|
Filing Dt:
|
05/03/2011
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
Title:
|
SCAVANGING METAL STACK FOR A HIGH-K GATE DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13099827
|
Filing Dt:
|
05/03/2011
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
TRANSPARENT PHOTODETECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
13100026
|
Filing Dt:
|
05/03/2011
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
NONCONTACT WRITING OF NANOMETER SCALE MAGNETIC BITS USING HEAT FLOW INDUCED SPIN TORQUE EFFECT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2012
|
Application #:
|
13100133
|
Filing Dt:
|
05/03/2011
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
Title:
|
METHOD OF FULL-FIELD SOLDER COVERAGE USING A VACUUM FILL HEAD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
13100456
|
Filing Dt:
|
05/04/2011
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
Title:
|
REPROGRAMMABLE FUSE STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13100589
|
Filing Dt:
|
05/04/2011
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
SPACER AS HARD MASK SCHEME FOR IN-SITU DOPING IN CMOS FINFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
13101260
|
Filing Dt:
|
05/05/2011
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
CAVITY-FREE INTERFACE BETWEEN EXTENSION REGIONS AND EMBEDDED SILICON-CARBON ALLOY SOURCE/DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13101267
|
Filing Dt:
|
05/05/2011
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
Title:
|
METHOD OF FORMING A PLANAR FIELD EFFECT TRANSISTOR WITH EMBEDDED AND FACETED SOURCE/DRAIN STRESSORS ON A SILICON-ON-INSULATOR (SOI) WAFER, A PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND A DESIGN STRUCTURE FOR THE PLANAR FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13101268
|
Filing Dt:
|
05/05/2011
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
3-D Integration using Multi Stage Vias
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
13101436
|
Filing Dt:
|
05/05/2011
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
DATA DEPENDENT SRAM WRITE ASSIST
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
13102007
|
Filing Dt:
|
05/05/2011
|
Publication #:
|
|
Pub Dt:
|
09/08/2011
| | | | |
Title:
|
METHOD OF PATTERNING SEMICONDUCTOR STRUCTURE AND STRUCTURE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13102550
|
Filing Dt:
|
05/06/2011
|
Publication #:
|
|
Pub Dt:
|
09/01/2011
| | | | |
Title:
|
CHEMICAL MECHANICAL POLISHING STOP LAYER FOR FULLY AMORPHOUS PHASE CHANGE MEMORY PORE CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
13102776
|
Filing Dt:
|
05/06/2011
|
Publication #:
|
|
Pub Dt:
|
11/08/2012
| | | | |
Title:
|
TIMING DRIVEN ROUTING IN INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13103193
|
Filing Dt:
|
05/09/2011
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
Title:
|
Nanoelectromechanical Structures Exhibiting Tensile Stress And Techniques For Fabrication Thereof
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13103197
|
Filing Dt:
|
05/09/2011
|
Publication #:
|
|
Pub Dt:
|
09/01/2011
| | | | |
Title:
|
METAL-GATE HIGH-K REFERENCE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13103569
|
Filing Dt:
|
05/09/2011
|
Publication #:
|
|
Pub Dt:
|
08/25/2011
| | | | |
Title:
|
DENSE PITCH BULK FINFET PROCESS BY SELECTIVE EPI AND ETCH
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13104542
|
Filing Dt:
|
05/10/2011
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
Title:
|
INTEGRATED CIRCUIT DIODE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
13104573
|
Filing Dt:
|
05/10/2011
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
Title:
|
LOGICAL CIRCUIT NETLIST REDUCTION AND MODEL SIMPLIFICATION USING SIMULATION RESULTS CONTAINING SYMBOLIC VALUES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
|
Application #:
|
13104591
|
Filing Dt:
|
05/10/2011
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
Title:
|
CARBON FIELD EFFECT TRANSISTORS HAVING CHARGED MONOLAYERS TO REDUCE PARASITIC RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
13106005
|
Filing Dt:
|
05/12/2011
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
Title:
|
CHANGING THE LOCATION OF A BUFFER BAY IN A NETLIST
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
|
Application #:
|
13106349
|
Filing Dt:
|
05/12/2011
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
Title:
|
SUPPRESSION OF DIFFUSION IN EPITAXIAL BURIED PLATE FOR DEEP TRENCHES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13106900
|
Filing Dt:
|
05/13/2011
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
Title:
|
SOI FET with embedded stressor block
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13106930
|
Filing Dt:
|
05/13/2011
|
Publication #:
|
|
Pub Dt:
|
09/01/2011
| | | | |
Title:
|
CONTACT MICROSCOPE USING POINT SOURCE ILLUMINATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
13107087
|
Filing Dt:
|
05/13/2011
|
Publication #:
|
|
Pub Dt:
|
09/08/2011
| | | | |
Title:
|
PROGRAMMABLE VIA DEVICES IN BACK END OF LINE LEVEL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13107355
|
Filing Dt:
|
05/13/2011
|
Publication #:
|
|
Pub Dt:
|
11/15/2012
| | | | |
Title:
|
TABLE-LOOKUP-BASED MODELS FOR YIELD ANALYSIS ACCELERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13108008
|
Filing Dt:
|
05/16/2011
|
Publication #:
|
|
Pub Dt:
|
09/01/2011
| | | | |
Title:
|
SATISFIABILITY (SAT) BASED BOUNDED MODEL CHECKERS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
|
Application #:
|
13108138
|
Filing Dt:
|
05/16/2011
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
Title:
|
SELF-ALIGNED METAL GATE CMOS WITH METAL BASE LAYER AND DUMMY GATE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13108144
|
Filing Dt:
|
05/16/2011
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
Title:
|
BARRIER TRENCH STRUCTURE AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2015
|
Application #:
|
13108213
|
Filing Dt:
|
05/16/2011
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
Title:
|
INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORS (FETS) AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13108240
|
Filing Dt:
|
05/16/2011
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
Title:
|
Post-Silicide Process and Structure For Stressed Liner Integration
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
13108282
|
Filing Dt:
|
05/16/2011
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
Title:
|
EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) FET WITH A BACK GATE AND REDUCED PARASITIC CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13108290
|
Filing Dt:
|
05/16/2011
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE HAVING NFET AND PFET FORMED IN SOI SUBSTRATE WITH UNDERLAPPED EXTENSIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13108305
|
Filing Dt:
|
05/16/2011
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
Title:
|
JUNCTION GATE FIELD EFFECT TRANSISTOR STRUCRURE HAVING N-CHANNEL
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13108574
|
Filing Dt:
|
05/16/2011
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
Title:
|
PORTABLE ELECTRONIC DEVICE CASE WITH ACTIVE THERMAL PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2013
|
Application #:
|
13108955
|
Filing Dt:
|
05/16/2011
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
Title:
|
TALL MEZZANINE CONNECTOR
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13109567
|
Filing Dt:
|
05/17/2011
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
Title:
|
SELECTIVE EPITAXIAL GROWTH BY INCUBATION TIME ENGINEERING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13109948
|
Filing Dt:
|
05/17/2011
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
Title:
|
METHOD AND COMPUTER PROGRAM PRODUCT FOR SYSTEM TUNING BASED ON PERFORMANCE MEASUREMENTS AND HISTORICAL PROBLEM DATA AND SYSTEM THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2013
|
Application #:
|
13110175
|
Filing Dt:
|
05/18/2011
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
GROUNDED LID FOR MICRO-ELECTRONIC ASSEMBLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13111283
|
Filing Dt:
|
05/19/2011
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE HAVING OFFSET PASSIVATION TO REDUCE ELECTROMIGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13112356
|
Filing Dt:
|
05/20/2011
|
Publication #:
|
|
Pub Dt:
|
10/06/2011
| | | | |
Title:
|
HYDRAZINE-FREE SOLUTION DEPOSITION OF CHALCOGENIDE FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
13112465
|
Filing Dt:
|
05/20/2011
|
Publication #:
|
|
Pub Dt:
|
11/22/2012
| | | | |
Title:
|
SINGLE-CRYSTALLINE SILICON ALKALINE TEXTURING WITH GLYCEROL OR ETHYLENE GLYCOL ADDITIVES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
13112477
|
Filing Dt:
|
05/20/2011
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
APPARATUS FOR AN ENHANCED MAGNETIC PLATING METHOD
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13112687
|
Filing Dt:
|
05/20/2011
|
Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
Title:
|
SYSTEMS AND METHODS FOR FORECASTING PROCESS EVENT DATES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13113107
|
Filing Dt:
|
05/23/2011
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
IMPLANT DAMAGE CONTROL BY IN-SITU C DOPING DURING SIGE EPITAXY FOR DEVICE APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2012
|
Application #:
|
13113256
|
Filing Dt:
|
05/23/2011
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
FIELD-BASED SIMILARITY SEARCH SYSTEM AND METHOD
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13113259
|
Filing Dt:
|
05/23/2011
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
Title:
|
REDUCED STRESS GULL WING SOLDER JOINTS FOR PRINTED WIRING BOARD CONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
13113421
|
Filing Dt:
|
05/23/2011
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
Title:
|
CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13114079
|
Filing Dt:
|
05/24/2011
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
Title:
|
WIRING STRUCTURE AND METHOD OF FORMING THE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
13114283
|
Filing Dt:
|
05/24/2011
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
Title:
|
STRUCTURE FOR CMOS ETSOI WITH MULTIPLE THRESHOLD VOLTAGES AND ACTIVE WELL BIAS CAPABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
13114342
|
Filing Dt:
|
05/24/2011
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
ELECTROMIGRATION RESISTANT ALUMINUM-BASED METAL INTERCONNECT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
13114543
|
Filing Dt:
|
05/24/2011
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
Title:
|
DUAL CONTACT TRENCH RESISTOR AND CAPACITOR IN SHALLOW TRENCH ISOLATION (STI) AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2012
|
Application #:
|
13115149
|
Filing Dt:
|
05/25/2011
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
COMPUTER PROGRAM PRODUCT FOR CONTROLLING A STORAGE DEVICE HAVING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13115314
|
Filing Dt:
|
05/25/2011
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
Title:
|
NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13115492
|
Filing Dt:
|
05/25/2011
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
Title:
|
GATE DIELECTRIC BREAKDOWN PROTECTION DURING ESD EVENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
13115823
|
Filing Dt:
|
05/25/2011
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
Title:
|
TECHNIQUE FOR VERIFYING THE MICROSTRUCTURE OF LEAD-FREE INTERCONNECTS IN SEMICONDUCTOR ASSEMBLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2014
|
Application #:
|
13116396
|
Filing Dt:
|
05/26/2011
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
SOI RADIO FREQUENCY SWITCH WITH ENHANCED SIGNAL FIDELITY AND ELECTRICAL ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13116416
|
Filing Dt:
|
05/26/2011
|
Publication #:
|
|
Pub Dt:
|
09/15/2011
| | | | |
Title:
|
CHARGE BREAKDOWN AVOIDANCE FOR MIM ELEMENTS IN SOI BASE TECHNOLOGY AND METHOD
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13116776
|
Filing Dt:
|
05/26/2011
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
Title:
|
INTERCONNECT FORMATION UNDER LOAD
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13117356
|
Filing Dt:
|
05/27/2011
|
Publication #:
|
|
Pub Dt:
|
11/29/2012
| | | | |
Title:
|
LEADFRAME-BASED BALL GRID ARRAY PACKAGING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13117536
|
Filing Dt:
|
05/27/2011
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
Title:
|
A COMPOSITION FOR FORMING A LOW-K DIELECTRIC LAYER COMPRISING A POLYMERIC PRECERAMIC PRECURSOR AND A SOLVENT.
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13118689
|
Filing Dt:
|
05/31/2011
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
Title:
|
Formation of Field Effect Transistor Devices
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13118881
|
Filing Dt:
|
05/31/2011
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
Title:
|
HIGH DENSITY MEMORY CELLS USING LATERAL EPITAXY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13126546
|
Filing Dt:
|
06/06/2011
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
METHOD, DEVICE, COMPUTER PROGRAM AND COMPUTER PROGRAM PRODUCT FOR DETERMINING A REPRESENTATION OF A SIGNAL
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13126546
|
Filing Dt:
|
06/06/2011
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | |
PCT #:
|
IB2009054807
|
Title:
|
METHOD, DEVICE, COMPUTER PROGRAM AND COMPUTER PROGRAM PRODUCT FOR DETERMINING A REPRESENTATION OF A SIGNAL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13135031
|
Filing Dt:
|
06/23/2011
|
Publication #:
|
|
Pub Dt:
|
01/05/2012
| | | | |
Title:
|
METHODS AND APPARATUS FOR SELECTIVE EPITAXY OF SI-CONTAINING MATERIALS AND SUBSTITUTIONALLY DOPED CRYSTALLINE SI-CONTAINING MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
13149108
|
Filing Dt:
|
05/31/2011
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
Title:
|
ELECTRICALLY PROGRAMMABLE METAL FUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13149797
|
Filing Dt:
|
05/31/2011
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
Title:
|
BEOL STRUCTURES INCORPORATING ACTIVE DEVICES AND MECHANICAL STRENGTH
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
13150437
|
Filing Dt:
|
06/01/2011
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
Title:
|
STRUCTURE AND METHOD FOR LATCHUP IMPROVEMENT USING THROUGH WAFER VIA LATCHUP GUARD RING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
13150440
|
Filing Dt:
|
06/01/2011
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
Title:
|
Si and SiGeC On A Buried Oxide Layer On A Substrate
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13150445
|
Filing Dt:
|
06/01/2011
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
Title:
|
Decentralized Dynamically Scheduled Parallel Static Timing Analysis
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13150612
|
Filing Dt:
|
06/01/2011
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
Title:
|
STRESS ENHANCED LDMOS TRANSISTOR TO MINIMIZE ON-RESISTANCE AND MAINTAIN HIGH BREAKDOWN VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13150690
|
Filing Dt:
|
06/01/2011
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
Title:
|
MEMORY PROGRAMMING FOR A PHASE CHANGE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
13150705
|
Filing Dt:
|
06/01/2011
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
Title:
|
POST DEPOSITION METHOD FOR REGROWTH OF CRYSTALLINE PHASE CHANGE MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
13151295
|
Filing Dt:
|
06/02/2011
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
Title:
|
METHOD FOR PERFORMING A PARALLEL STATIC TIMING ANALYSIS USING THREAD-SPECIFIC SUB-GRAPHS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
13151313
|
Filing Dt:
|
06/02/2011
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
Title:
|
METHOD, A SYSTEM AND A PROGRAM STORAGE DEVICE FOR MODELING THE RESISTANCE OF A MULTI-CONTACTED DIFFUSION REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
13151337
|
Filing Dt:
|
06/02/2011
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
Title:
|
SYSTEMS AND METHODS FOR DETERMINING ADJUSTABLE WAFER ACCEPTANCE CRITERIA BASED ON CHIP CHARACTERISTICS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
13151413
|
Filing Dt:
|
06/02/2011
|
Publication #:
|
|
Pub Dt:
|
12/06/2012
| | | | |
Title:
|
PARALLEL SOLVING OF LAYOUT OPTIMIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13151525
|
Filing Dt:
|
06/02/2011
|
Publication #:
|
|
Pub Dt:
|
09/22/2011
| | | | |
Title:
|
HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
13153051
|
Filing Dt:
|
06/03/2011
|
Publication #:
|
|
Pub Dt:
|
10/20/2011
| | | | |
Title:
|
SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13153381
|
Filing Dt:
|
06/03/2011
|
Publication #:
|
|
Pub Dt:
|
03/22/2012
| | | | |
Title:
|
ANNEALING THIN FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13153806
|
Filing Dt:
|
06/06/2011
|
Publication #:
|
|
Pub Dt:
|
09/29/2011
| | | | |
Title:
|
EMBEDDED DRAM INTEGRATED CIRCUITS WITH EXTREMELY THIN SILICON-ON-INSULATOR PASS TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13154677
|
Filing Dt:
|
06/07/2011
|
Publication #:
|
|
Pub Dt:
|
12/13/2012
| | | | |
Title:
|
HIGHLY SCALED ETSOI FLOATING BODY MEMORY AND MEMORY CIRCUIT
|
|