|
|
Patent #:
|
|
Issue Dt:
|
03/17/2009
|
Application #:
|
11439636
|
Filing Dt:
|
05/23/2006
|
Publication #:
|
|
Pub Dt:
|
11/29/2007
| | | | |
Title:
|
SYSTEM AND METHOD FOR MORE EFFICIENTLY USING ERROR CORRECTION CODES TO FACILITATE MEMORY DEVICE TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
11439685
|
Filing Dt:
|
05/24/2006
|
Publication #:
|
|
Pub Dt:
|
09/21/2006
| | | | |
Title:
|
DELAY-LOCKED LOOP WITH FEEDBACK COMPENSATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
11439965
|
Filing Dt:
|
05/25/2006
|
Publication #:
|
|
Pub Dt:
|
09/21/2006
| | | | |
Title:
|
METHOD AND STRUCTURE TO REDUCE OPTICAL CROSSTALK IN A SOLID STATE IMAGER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11440181
|
Filing Dt:
|
05/25/2006
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
CHIP INFORMATION MANAGING METHOD, CHIP INFORMATION MANAGING SYSTEM, AND CHIP INFORMATION MANAGING PROGRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2008
|
Application #:
|
11440250
|
Filing Dt:
|
05/24/2006
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
VOLTAGE LEVEL TRANSLATOR CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
11440260
|
Filing Dt:
|
05/24/2006
|
Publication #:
|
|
Pub Dt:
|
03/29/2007
| | | | |
Title:
|
METHOD OF MANUFACTURING DEVICES HAVING VERTICAL JUNCTION EDGE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2010
|
Application #:
|
11440348
|
Filing Dt:
|
05/24/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
MEMORY BLOCK QUALITY IDENTIFICATION IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2008
|
Application #:
|
11440646
|
Filing Dt:
|
05/24/2006
|
Publication #:
|
|
Pub Dt:
|
09/21/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR A FLASH MEMORY DEVICE COMPRISING A SOURCE LOCAL INTERCONNECT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
11440913
|
Filing Dt:
|
05/25/2006
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
Title:
|
STACKED DIE-IN-DIE BGA PACKAGE WITH DIE HAVING A RECESS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
11442506
|
Filing Dt:
|
05/25/2006
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
BUILT-IN SYSTEM AND METHOD FOR TESTING INTEGRATED CIRCUIT TIMING PARAMETERS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2008
|
Application #:
|
11442510
|
Filing Dt:
|
05/25/2006
|
Publication #:
|
|
Pub Dt:
|
11/29/2007
| | | | |
Title:
|
DE-EMPHASIS SYSTEM AND METHOD FOR COUPLING DIGITAL SIGNALS THROUGH CAPACITIVELY LOADED LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
11442515
|
Filing Dt:
|
05/25/2006
|
Publication #:
|
|
Pub Dt:
|
12/27/2007
| | | | |
Title:
|
WIDE FREQUENCY RANGE SIGNAL GENERATOR AND METHOD, AND INTEGRATED CIRCUIT TEST SYSTEM USING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
11443266
|
Filing Dt:
|
05/31/2006
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
Title:
|
LAYERED RESISTANCE VARIABLE MEMORY DEVICE AND METHOD OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
11444404
|
Filing Dt:
|
06/01/2006
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
Title:
|
MICROELECTRONIC IMAGING UNITS AND METHODS OF MANUFACTURING MICROELECTRONIC IMAGING UNITS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11444705
|
Filing Dt:
|
06/01/2006
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
ERROR DETECTION, DOCUMENTATION, AND CORRECTION IN A FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
11444820
|
Filing Dt:
|
06/01/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
ERROR DETECTION, DOCUMENTATION, AND CORRECTION IN A FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
11444892
|
Filing Dt:
|
05/31/2006
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
CIRCUIT AND METHOD FOR RETRIEVING DATA STORED IN SEMICONDUCTOR MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11444993
|
Filing Dt:
|
06/01/2006
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
Title:
|
METAL-SUBSTITUTED TRANSISTOR GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
11445000
|
Filing Dt:
|
06/01/2006
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
Title:
|
METAL-SUBSTITUTED TRANSISTOR GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2010
|
Application #:
|
11445032
|
Filing Dt:
|
05/31/2006
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
Title:
|
METHODS FOR ASSESSING ALIGNMENTS OF SUBSTRATES WITHIN DEPOSITION APPARATUSES; AND METHODS FOR ASSESSING THICKNESSES OF DEPOSITED LAYERS WITHIN DEPOSITION APPARATUSES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2008
|
Application #:
|
11445491
|
Filing Dt:
|
05/31/2006
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
Title:
|
FLASH MEMORY DEVICE WITH NAND ARCHITECTURE WITH REDUCED CAPACITIVE COUPLING EFFECT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
11445544
|
Filing Dt:
|
06/02/2006
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
METHODS OF SHAPING VERTICAL SINGLE CRYSTAL SILICON WALLS AND RESULTING STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2009
|
Application #:
|
11445708
|
Filing Dt:
|
06/02/2006
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
METHODS OF FORMING CARBON NANOTUBES AND METHODS OF FABRICATING INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/2009
|
Application #:
|
11445718
|
Filing Dt:
|
06/02/2006
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
WET ETCH SUITABLE FOR CREATING SQUARE CUTS IN SI
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
11445766
|
Filing Dt:
|
06/01/2006
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
MASKING TECHNIQUES AND CONTACT IMPRINT RETICLES FOR DENSE SEMICONDUCTOR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
11445907
|
Filing Dt:
|
06/02/2006
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
TOPOGRAPHY BASED PATTERNING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2009
|
Application #:
|
11445911
|
Filing Dt:
|
06/02/2006
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
METHODS OF FABRICATING INTERMEDIATE SEMICONDUCTOR STRUCTURES BY SELECTIVELY ETCHING POCKETS OF IMPLANTED SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
11446003
|
Filing Dt:
|
06/01/2006
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
MICROELECTRONIC WORKPIECES AND METHODS AND SYSTEMS FOR FORMING INTERCONNECTS IN MICROELECTRONIC WORKPIECES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2009
|
Application #:
|
11446004
|
Filing Dt:
|
06/01/2006
|
Publication #:
|
|
Pub Dt:
|
10/25/2007
| | | | |
Title:
|
INTEGRATED CIRCUIT DEVICES WITH STACKED PACKAGE INTERPOSERS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2009
|
Application #:
|
11446725
|
Filing Dt:
|
06/05/2006
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
Title:
|
FAST DATA ACCESS MODE IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2008
|
Application #:
|
11447147
|
Filing Dt:
|
06/06/2006
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
METHOD FOR FORMING CAPACITOR IN SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
11447272
|
Filing Dt:
|
06/06/2006
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
INDIVIDUAL I/O MODULATION IN MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11447709
|
Filing Dt:
|
06/06/2006
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
SEMICONDUCTOR MAGNETIC MEMORY INTEGRATING A MAGNETIC TUNNELING JUNCTION ABOVE A FLOATING-GATE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11447740
|
Filing Dt:
|
06/05/2006
|
Title:
|
METHOD AND APPARATUS FOR REDUCING OSCILLATION IN SYNCHRONOUS CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2009
|
Application #:
|
11447741
|
Filing Dt:
|
06/05/2006
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
Title:
|
CHEMICAL MECHANICAL POLISHING PADS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11447808
|
Filing Dt:
|
06/06/2006
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
Title:
|
PLATING BUSS AND A METHOD OF USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
11447909
|
Filing Dt:
|
06/07/2006
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
METHODS OF FORMING AMORPHOUS CARBON BASED NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2009
|
Application #:
|
11447921
|
Filing Dt:
|
06/07/2006
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
Title:
|
STRUCTURE FOR AMORPHOUS CARBON BASED NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
11448062
|
Filing Dt:
|
06/06/2006
|
Publication #:
|
|
Pub Dt:
|
06/14/2007
| | | | |
Title:
|
HIGH VOLTAGE SWITCHING CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
11448063
|
Filing Dt:
|
06/06/2006
|
Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICE TO REDUCE FLOATING-GATE-TO-FLOATING-GATE COUPLING EFFECT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
11448220
|
Filing Dt:
|
06/07/2006
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
Title:
|
COMMON WORDLINE FLASH ARRAY ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2008
|
Application #:
|
11448257
|
Filing Dt:
|
06/06/2006
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
Title:
|
SEMICONDUCTOR SUBSTRATES AND FIELD EFFECT TRANSISTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2008
|
Application #:
|
11448375
|
Filing Dt:
|
06/06/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
SEMICONDUCTOR SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11448996
|
Filing Dt:
|
06/07/2006
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
Title:
|
METHOD OF EXPOSING A SUBSTRATE TO A SURFACE MICROWAVE PLASMA, ETCHING METHOD, DEPOSITION METHOD, SURFACE MICROWAVE PLASMA GENERATING APPARATUS, SEMICONDUCTOR SUBSTRATE ETCHING APPARATUS, SEMICONDUCTOR SUBSTRATE DEPOSITION APPARATUS, AND MICROWAVE PLASMA GENERATING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2008
|
Application #:
|
11449472
|
Filing Dt:
|
06/07/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
METHODS RELATING TO THE RECONSTRUCTION OF SEMICONDUCTOR WAFERS FOR WAFER-LEVEL PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2010
|
Application #:
|
11449539
|
Filing Dt:
|
06/07/2006
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
Title:
|
CONCENTRIC OR NESTED CONTAINER CAPACITOR STRUCTURE FOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2009
|
Application #:
|
11449754
|
Filing Dt:
|
06/09/2006
|
Publication #:
|
|
Pub Dt:
|
12/20/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR MANAGING BEHAVIOR OF MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2009
|
Application #:
|
11449755
|
Filing Dt:
|
06/09/2006
|
Publication #:
|
|
Pub Dt:
|
11/15/2007
| | | | |
Title:
|
METHOD, APPARATUS, AND SYSTEM FOR PROVIDING INITIAL STATE RANDOM ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
|
Application #:
|
11450020
|
Filing Dt:
|
06/09/2006
|
Publication #:
|
|
Pub Dt:
|
12/13/2007
| | | | |
Title:
|
METHODS OF FORMING VARIABLE RESISTANCE MEMORY CELLS, AND METHODS OF ETCHING GERMANIUM, ANTIMONY, AND TELLURIUM-COMPRISING MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2008
|
Application #:
|
11450485
|
Filing Dt:
|
06/09/2006
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
Title:
|
STACKED DIE PACKAGE FOR PERIPHERAL AND CENTER DEVICE PAD LAYOUT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2009
|
Application #:
|
11450630
|
Filing Dt:
|
06/09/2006
|
Publication #:
|
|
Pub Dt:
|
12/27/2007
| | | | |
Title:
|
LOCAL COARSE DELAY UNITS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
11450661
|
Filing Dt:
|
06/08/2006
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
Title:
|
CAPACITORLESS DRAM ON BULK SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2009
|
Application #:
|
11450759
|
Filing Dt:
|
06/09/2006
|
Publication #:
|
|
Pub Dt:
|
12/13/2007
| | | | |
Title:
|
APPARATUS AND METHODS FOR PROGRAMMING MULTILEVEL-CELL NAND MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2009
|
Application #:
|
11450760
|
Filing Dt:
|
06/09/2006
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
Title:
|
FLASH MEMORY CELLS WITH REDUCED DISTANCES BETWEEN CELL ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
11451703
|
Filing Dt:
|
06/13/2006
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
SELF ALIGNED METAL GATES ON HIGH-K DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2009
|
Application #:
|
11451723
|
Filing Dt:
|
06/12/2006
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
METHODS AND APPARATUS FOR ELECTRICAL, MECHANICAL AND/OR CHEMICAL REMOVAL OF CONDUCTIVE MATERIAL FROM A MICROELECTRONIC SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2009
|
Application #:
|
11451822
|
Filing Dt:
|
06/13/2006
|
Publication #:
|
|
Pub Dt:
|
12/20/2007
| | | | |
Title:
|
CHARGE PUMP OPERATION IN A NON-VOLATILE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2009
|
Application #:
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11451920
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Filing Dt:
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06/13/2006
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Publication #:
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Pub Dt:
|
10/19/2006
| | | | |
Title:
|
MERGED MOS-BIPOLAR CAPACITOR MEMORY CELL
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|
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Patent #:
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Issue Dt:
|
10/13/2009
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Application #:
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11451925
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Filing Dt:
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06/12/2006
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Publication #:
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Pub Dt:
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10/19/2006
| | | | |
Title:
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MAGNETIC ANNEALING SEQUENCES FOR PATTERNED MRAM SYNTHETIC ANTIFERROMAGNETIC PINNED LAYERS
|
|
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Patent #:
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Issue Dt:
|
10/27/2009
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Application #:
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11452025
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Filing Dt:
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06/13/2006
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Publication #:
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Pub Dt:
|
10/12/2006
| | | | |
Title:
|
MERGED MOS-BIPOLAR CAPACITOR MEMORY CELL
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|
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Patent #:
|
|
Issue Dt:
|
05/26/2009
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Application #:
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11452594
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Filing Dt:
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06/14/2006
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Publication #:
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Pub Dt:
|
01/04/2007
| | | | |
Title:
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DATA SECURITY FOR DIGITAL DATA STORAGE
|
|
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Patent #:
|
|
Issue Dt:
|
10/11/2011
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Application #:
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11452696
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Filing Dt:
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06/14/2006
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Publication #:
|
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Pub Dt:
|
10/19/2006
| | | | |
Title:
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AUTOMATIC TEST ENTRY TERMINATION IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2008
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Application #:
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11452697
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Filing Dt:
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06/14/2006
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Publication #:
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Pub Dt:
|
12/20/2007
| | | | |
Title:
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ARCHITECTURE AND METHOD FOR NAND FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2009
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Application #:
|
11452698
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Filing Dt:
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06/14/2006
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Publication #:
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Pub Dt:
|
12/20/2007
| | | | |
Title:
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PROGRAMMING METHOD FOR NAND FLASH
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2012
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Application #:
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11452750
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Filing Dt:
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06/13/2006
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Publication #:
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Pub Dt:
|
10/04/2007
| | | | |
Title:
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PACKAGED MICROELECTRONIC DEVICES RECESSED IN SUPPORT MEMBER CAVITIES, AND ASSOCIATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2009
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Application #:
|
11452783
|
Filing Dt:
|
06/13/2006
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Publication #:
|
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Pub Dt:
|
12/14/2006
| | | | |
Title:
|
BIAS SENSING IN SENSE AMPLIFIERS THROUGH A VOLTAGE-COUPLING/DECOUPLING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11452817
|
Filing Dt:
|
06/13/2006
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Publication #:
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|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
ATOMIC LAYER DEPOSITION METHODS AND CHEMICAL VAPOR DEPOSITION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
11452830
|
Filing Dt:
|
06/13/2006
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
11453425
|
Filing Dt:
|
06/14/2006
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
METHODS OF FORMING RETICLES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2009
|
Application #:
|
11454464
|
Filing Dt:
|
06/16/2006
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
Title:
|
DEFECTIVE MEMORY BLOCK IDENTIFICATION IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2009
|
Application #:
|
11454501
|
Filing Dt:
|
06/16/2006
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
APPARATUS FOR CONDITIONING CHEMICAL-MECHANICAL POLISHING PADS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
11455023
|
Filing Dt:
|
06/15/2006
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
Title:
|
METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2009
|
Application #:
|
11455877
|
Filing Dt:
|
06/19/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
MEMORY DEVICE WITH HIGH DIELECTRIC CONSTANT GATE DIELECTRICS AND METAL FLOATING GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11456058
|
Filing Dt:
|
07/06/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
MEMORY DEVICE HAVING TERMINALS FOR TRANSFERRING MULTIPLE TYPES OF DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
11456366
|
Filing Dt:
|
07/10/2006
|
Publication #:
|
|
Pub Dt:
|
01/10/2008
| | | | |
Title:
|
ANTIFUSE CIRCUIT WITH WELL BIAS TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11457223
|
Filing Dt:
|
07/13/2006
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
Title:
|
BOW CONTROL IN AN ELECTRONIC PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2010
|
Application #:
|
11457298
|
Filing Dt:
|
07/13/2006
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
Title:
|
MEMORY DEVICE HAVING CONDITIONING OUTPUT DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2009
|
Application #:
|
11457423
|
Filing Dt:
|
07/13/2006
|
Title:
|
MEMORY ARRAY WITH ULTRA-THIN ETCHED PILLAR SURROUND GATE ACCESS TRANSISTORS AND BURIED DATA/BIT LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11457620
|
Filing Dt:
|
07/14/2006
|
Publication #:
|
|
Pub Dt:
|
01/17/2008
| | | | |
Title:
|
METHOD OF FORMING MEMORY DEVICES BY PERFORMING HALOGEN ION IMPLANTATION AND DIFFUSION PROCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
11457966
|
Filing Dt:
|
07/17/2006
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
SEALING METHOD FOR ELECTRONIC DEVICES FORMED ON A COMMON SEMICONDUCTOR SUBSTRATE AND CORRESPONDING CIRCUIT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
11458053
|
Filing Dt:
|
07/17/2006
|
Title:
|
TECHNIQUES FOR GENERATING SERIAL PRESENCE DETECT CONTENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2009
|
Application #:
|
11458064
|
Filing Dt:
|
07/17/2006
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
PROTECTION IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11458155
|
Filing Dt:
|
07/18/2006
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
Title:
|
CAPACITIVE TECHNIQUES TO REDUCE NOISE IN HIGH SPEED INTERCONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
11458195
|
Filing Dt:
|
07/18/2006
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
STRUCTURES AND METHODS TO ENHANCE COPPER METALLIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11458631
|
Filing Dt:
|
07/19/2006
|
Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CONTROLLING CLOCK CYCLE TIME FOR REDUCED POWER CONSUMPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
11458642
|
Filing Dt:
|
07/19/2006
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
Title:
|
TRANSPARENT AMORPHOUS CARBON STRUCTURE IN SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2009
|
Application #:
|
11458847
|
Filing Dt:
|
07/20/2006
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
Title:
|
NOR FLASH MEMORY CELL WITH HIGH STORAGE DENSITY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
11458859
|
Filing Dt:
|
07/20/2006
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
APPARATUS AND METHOD FOR HIGH DENSITY MULTI-CHIP STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
11458863
|
Filing Dt:
|
07/20/2006
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
METHOD OF CLEANING SEMICONDUCTOR SURFACES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11458904
|
Filing Dt:
|
07/20/2006
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHOD FOR ACCESSING A MULTILEVEL NONVOLATILE MEMORY DEVICE OF THE FLASH NAND TYPE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
11458967
|
Filing Dt:
|
07/20/2006
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING AN ACTIVE AREA PARTIALLY ISOLATED BY A LATERAL CAVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
11458975
|
Filing Dt:
|
07/20/2006
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
METHODS FOR MAKING INTEGRATED-CIRCUIT WIRING FROM COPPER, SILVER, GOLD, AND OTHER METALS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
11458976
|
Filing Dt:
|
07/20/2006
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
MICROSTRIP LINE DIELECTRIC OVERLAY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
11459831
|
Filing Dt:
|
07/25/2006
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE WITH A PAGE BUFFER HAVING AN IMPROVED LAYOUT ARRANGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
11460089
|
Filing Dt:
|
07/26/2006
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
WAFER LEVEL PRE-PACKAGED FLIP CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2010
|
Application #:
|
11460093
|
Filing Dt:
|
07/26/2006
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
WAFER LEVEL PRE-PACKAGED FLIP CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2008
|
Application #:
|
11460203
|
Filing Dt:
|
07/26/2006
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
ATOMIC LAYER DEPOSITION OF ZR3N4/ZRO2 FILMS AS GATE DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
11460371
|
Filing Dt:
|
07/27/2006
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
BIT INVERSION IN MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
11460391
|
Filing Dt:
|
07/27/2006
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
GETTERING OF SILICON ON INSULATOR USING RELAXED SILICON GERMANIUM EPITAXIAL PROXIMITY LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2010
|
Application #:
|
11460435
|
Filing Dt:
|
07/27/2006
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
WAFER LEVEL PRE-PACKAGED FLIP CHIP SYSTEMS
|
|