|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13431108
|
Filing Dt:
|
03/27/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
MEMORY DEVICE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13431254
|
Filing Dt:
|
03/27/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
PAD BONDING EMPLOYING A SELF-ALIGNED PLATED LINER FOR ADHESION ENHANCEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13431328
|
Filing Dt:
|
03/27/2012
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SIGE CHANNEL ENGINEERING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2015
|
Application #:
|
13431343
|
Filing Dt:
|
03/27/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
BOTTOM-UP PLATING OF THROUGH-SUBSTRATE VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13431368
|
Filing Dt:
|
03/27/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
RELATIVE ORDERING CIRCUIT SYNTHESIS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2014
|
Application #:
|
13431414
|
Filing Dt:
|
03/27/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2014
|
Application #:
|
13431456
|
Filing Dt:
|
03/27/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13431539
|
Filing Dt:
|
03/27/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
ELECTRIC VEHICLE CHARGING TRANSACTION INTERFACE FOR MANAGING ELECTRIC VEHICLE CHARGING TRANSACTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2013
|
Application #:
|
13431599
|
Filing Dt:
|
03/27/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13431770
|
Filing Dt:
|
03/27/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
METHODS OF MANUFACTURING FINFET DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13432018
|
Filing Dt:
|
03/28/2012
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
PRE-GATE, SOURCE/DRAIN STRAIN LAYER FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13432036
|
Filing Dt:
|
03/28/2012
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
TWO-DIMENSIONAL PATTERNING EMPLOYING SELF-ASSEMBLED MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13432349
|
Filing Dt:
|
03/28/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
UTILIZING GATE PHASES FOR CIRCUIT TUNING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13432353
|
Filing Dt:
|
03/28/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
THREE DIMENSIONAL SOLID-STATE BATTERY INTEGRATED WITH CMOS DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13432395
|
Filing Dt:
|
03/28/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
METAL HIGH-K TRANSISTOR HAVING SILICON SIDEWALLS FOR REDUCED PARASITIC CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2016
|
Application #:
|
13432414
|
Filing Dt:
|
03/28/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
REACTIVE METAL OPTICAL SECURITY DEVICE AND METHODS OF FABRICATION AND USE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13432421
|
Filing Dt:
|
03/28/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
DUAL-DAMASCENE PROCESS TO FABRICATE THICK WIRE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
13432440
|
Filing Dt:
|
03/28/2012
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13432716
|
Filing Dt:
|
03/28/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
13432772
|
Filing Dt:
|
03/28/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
VISUALLY DETECTING ELECTROSTATIC DISCHARGE EVENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13432963
|
Filing Dt:
|
03/28/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
FORMING SEMICONDUCTOR CHIP CONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13432966
|
Filing Dt:
|
03/28/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
REMOVING MATERIAL FROM DEFECTIVE OPENING IN GLASS MOLD AND RELATED GLASS MOLD FOR INJECTION MOLDED SOLDER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13433401
|
Filing Dt:
|
03/29/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT WITH ON-CHIP RESISTORS AND METHOD OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13433423
|
Filing Dt:
|
03/29/2012
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13433537
|
Filing Dt:
|
03/29/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2016
|
Application #:
|
13433659
|
Filing Dt:
|
03/29/2012
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
HIGH-K/METAL GATE STACK USING CAPPING LAYER METHODS, IC AND RELATED TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13433815
|
Filing Dt:
|
03/29/2012
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
TECHNIQUES FOR ENABLING MULTIPLE VT DEVICES USING HIGH-K METAL GATE STACKS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13434128
|
Filing Dt:
|
03/29/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
ASYMMETRIC FET FORMED THROUGH USE OF VARIABLE PITCH GATE FOR USE AS LOGIC DEVICE AND TEST STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13434495
|
Filing Dt:
|
03/29/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
TEST CASE PATTERN MATCHING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13434739
|
Filing Dt:
|
03/29/2012
|
Publication #:
|
|
Pub Dt:
|
03/06/2014
| | | | |
Title:
|
PARALLEL PROGRAMMING MULTIPLE PHASE CHANGE MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13434883
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
ENHANCED CAPACITANCE TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2015
|
Application #:
|
13434934
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13434964
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
NON-PLANAR CAPACITOR AND METHOD OF FORMING THE NON-PLANAR CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13435056
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
13435795
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
PLACEMENT AND OPTIMIZATION OF PROCESS DUMMY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13435828
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
SINGLE CYCLE DATA COPY FOR TWO-PORT SRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
|
Application #:
|
13436039
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13436045
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT STRUCTURE HAVING AIR-GAP TRENCH ISOLATION AND RELATED DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
13436196
|
Filing Dt:
|
03/30/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
LOGIC DESIGN VERIFICATION TECHNIQUES FOR LIVENESS CHECKING WITH RETIMING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13436850
|
Filing Dt:
|
03/31/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
N-TYPE CARRIER ENHANCEMENT IN SEMICONDUCTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13437036
|
Filing Dt:
|
04/02/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
N-TYPE CARRIER ENHANCEMENT IN SEMICONDUCTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
13437198
|
Filing Dt:
|
04/02/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
ASYNCHRONOUS DELETION OF A RANGE OF MESSAGES PROCESSED BY A PARALLEL DATABASE REPLICATION APPLY PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13437273
|
Filing Dt:
|
04/02/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
DISCONTINUOUS GUARD RING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13437309
|
Filing Dt:
|
04/02/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
STRESS REDUCTION MEANS FOR WARP CONTROL OF SUBSTRATES THROUGH CLAMPING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
13437506
|
Filing Dt:
|
04/02/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
IDENTIFICATION OF LOCALIZABLE FUNCTION CALLS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13438230
|
Filing Dt:
|
04/03/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13438437
|
Filing Dt:
|
04/03/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
LOW EXTENSION DOSE IMPLANTS IN SRAM FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13438508
|
Filing Dt:
|
04/03/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTORS AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2013
|
Application #:
|
13439188
|
Filing Dt:
|
04/04/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
METHOD AND APPARATUS FOR GENERATING TEST PATTERNS FOR USE IN AT-SPEED TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
13439198
|
Filing Dt:
|
04/04/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
DIRECT EDGE CONNECTION FOR MULTI-CHIP INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13439885
|
Filing Dt:
|
04/05/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
AUTOMATIC PARITY CHECKING IDENTIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13440514
|
Filing Dt:
|
04/05/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
SELF-PROTECTED DRAIN-EXTENDED METAL-OXIDE-SEMICONDUCTOR TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
13440546
|
Filing Dt:
|
04/05/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
DEVICE AND METHOD FOR FORMING SHARP EXTENSION REGION WITH CONTROLLABLE JUNCTION DEPTH AND LATERAL OVERLAP
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13440590
|
Filing Dt:
|
04/05/2012
|
Publication #:
|
|
Pub Dt:
|
07/26/2012
| | | | |
Title:
|
NANOWIRE MOSFET WITH DOPED EPITAXIAL CONTACTS FOR SOURCE AND DRAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13441048
|
Filing Dt:
|
04/06/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13441053
|
Filing Dt:
|
04/06/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
BEST CLOCK FREQUENCY SEARCH FOR FPGA-BASED DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
13441245
|
Filing Dt:
|
04/06/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
ON-CHIP VARIABLE DELAY TRANSMISSION LINE WITH FIXED CHARACTERISTIC IMPEDANCE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13442008
|
Filing Dt:
|
04/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13442011
|
Filing Dt:
|
04/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
13442062
|
Filing Dt:
|
04/09/2012
|
Publication #:
|
|
Pub Dt:
|
01/30/2014
| | | | |
Title:
|
STRUCTURE AND METHOD TO ENSURE CORRECT OPERATION OF AN INTEGRATED CIRCUIT IN THE PRESENCE OF IONIZING RADIATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
13442087
|
Filing Dt:
|
04/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
HIGH-K TRANSISTORS WITH LOW THRESHOLD VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13442090
|
Filing Dt:
|
04/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
HIGH-K TRANSISTORS WITH LOW THRESHOLD VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13442168
|
Filing Dt:
|
04/09/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
ROBUST ISOLATION FOR THIN-BOX ETSOI MOSFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
13442322
|
Filing Dt:
|
04/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
METHOD OF FULL-FIELD SOLDER COVERAGE BY INVERTING A FILL HEAD AND A MOLD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
13443003
|
Filing Dt:
|
04/10/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
GRAPHENE GROWTH ON A CARBON-CONTAINING SEMICONDUCTOR LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
|
Application #:
|
13443062
|
Filing Dt:
|
04/10/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
THERMALLY EXCITED NEAR-FIELD SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13443133
|
Filing Dt:
|
04/10/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
STRUCTURE AND METHOD OF HIGH-PERFORMANCE EXTREMELY THIN SILICON ON INSULATOR COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTORS WITH DUAL STRESS BURIED INSULATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2014
|
Application #:
|
13443183
|
Filing Dt:
|
04/10/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
IMPLEMENTING LOW DUTY CYCLE DISTORTION AND LOW POWER DIFFERENTIAL TO SINGLE ENDED LEVEL SHIFTER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13443418
|
Filing Dt:
|
04/10/2012
|
Publication #:
|
|
Pub Dt:
|
11/21/2013
| | | | |
Title:
|
BONDING OF SUBSTRATES INCLUDING METAL-DIELECTRIC PATTERNS WITH METAL RAISED ABOVE DIELECTRIC AND STRUCTURES SO FORMED
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13443426
|
Filing Dt:
|
04/10/2012
|
Publication #:
|
|
Pub Dt:
|
10/10/2013
| | | | |
Title:
|
VIA SELECTION IN INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13443427
|
Filing Dt:
|
04/10/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
METHOD AND APPARATUS FOR SUB-PELLICLE DEFECT REDUCTION ON PHOTOMASKS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13444094
|
Filing Dt:
|
04/11/2012
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
COMPUTING VALIDATION COVERAGE OF INTEGRATED CIRCUIT MODEL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13444193
|
Filing Dt:
|
04/11/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
ELECTROSTATIC CHUCKING OF AN INSULATOR HANDLE SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
13444219
|
Filing Dt:
|
04/11/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
FINFET NON-VOLATILE MEMORY AND METHOD OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13444343
|
Filing Dt:
|
04/11/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13444405
|
Filing Dt:
|
04/11/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
ADVANCED LOW K CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
13444415
|
Filing Dt:
|
04/11/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
ADVANCED LOW K CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13444447
|
Filing Dt:
|
04/11/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
REPLACEMENT GATE STRUCTURES AND METHODS OF MANUFACTURING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13444633
|
Filing Dt:
|
04/11/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
IMPLEMENTING PHASE LOCKED LOOP (PLL) WITH ENHANCED LOCKING CAPABILITY WITH A WIDE RANGE DYNAMIC REFERENCE CLOCK
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
13444647
|
Filing Dt:
|
04/11/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
INTEGRATED CIRCUIT INCLUDING THERMAL GATE, RELATED METHOD AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13445101
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
Nano/Microwire Solar Cell Fabricated by Nano/Microsphere Lithography
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13445128
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
SOLVING CONGESTION USING NET GROUPING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
13445172
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13445187
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
READ ONLY MEMORY (ROM) WITH REDUNDANCY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
13445194
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
13445446
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
METHOD FOR MINIMIZING PRODUCTIVITY LOSS WHILE USING A MANUFACTURING SCHEDULER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
13445641
|
Filing Dt:
|
04/12/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
APPARATUS FOR THERMAL CHARACTERIZATION UNDER NON-UNIFORM HEAT LOAD
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13445959
|
Filing Dt:
|
04/13/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
STRAINED SOI FINFET ON EPITAXIALLY GROWN BOX
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
13446115
|
Filing Dt:
|
04/13/2012
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
SWITCH WITH REDUCED INSERTION LOSS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
13446350
|
Filing Dt:
|
04/13/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE HAVING A SOURCE AND A DRAIN WITH REVERSE FACETS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13446369
|
Filing Dt:
|
04/13/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
MITIGATION OF MASK DEFECTS BY PATTERN SHIFTING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
13446602
|
Filing Dt:
|
04/13/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13447055
|
Filing Dt:
|
04/13/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
PLANNING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
13447221
|
Filing Dt:
|
04/15/2012
|
Publication #:
|
|
Pub Dt:
|
08/02/2012
| | | | |
Title:
|
PROOF BASED BOUNDED MODEL CHECKING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13447344
|
Filing Dt:
|
04/16/2012
|
Title:
|
METHODOLOGIES FOR AUTOMATIC 3-D DEVICE STRUCTURE SYNTHESIS FROM CIRCUIT LAYOUTS FOR DEVICE SIMULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
13447751
|
Filing Dt:
|
04/16/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
REDUCING REPEATER POWER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2015
|
Application #:
|
13447982
|
Filing Dt:
|
04/16/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
METHOD AND APPARATUS FOR FABRICATING OR ALTERING MICROSTRUCTURES USING LOCAL CHEMICAL ALTERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
13448428
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
Operation of a Noise Cancellation Device
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13448500
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
METHOD OF FORMING UNDERBUMP METALLURGY STRUCTURE EMPLOYING SPUTTER-DEPOSITED NICKEL COPPER ALLOY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13448749
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES
|
|