|
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Patent #:
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|
Issue Dt:
|
11/17/1998
|
Application #:
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08903198
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Filing Dt:
|
07/15/1997
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Title:
|
INTEGRATED CIRCUITRY WITH INTERCONNECTION PILLAR
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|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
08903222
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Filing Dt:
|
07/22/1997
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Title:
|
ARTICLE TRANSFER METHODS
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|
|
Patent #:
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|
Issue Dt:
|
08/30/2005
|
Application #:
|
08903486
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Filing Dt:
|
07/29/1997
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Title:
|
SILICON CARBIDE GATE TRANSISTOR
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|
|
Patent #:
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|
Issue Dt:
|
11/23/1999
|
Application #:
|
08904657
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Filing Dt:
|
08/01/1997
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Title:
|
METHOD FOR MAKING POLISHING PAD WITH ELONGATED MICROCOLUMNS
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|
|
Patent #:
|
|
Issue Dt:
|
02/29/2000
|
Application #:
|
08904746
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Filing Dt:
|
08/01/1997
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Title:
|
APPARATUS AND METHOD FOR IMPROVING UNIFORMITY IN BATCH PROCESSING OF SEMICONDUCTOR WAFERS
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|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
08905602
|
Filing Dt:
|
08/04/1997
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Title:
|
METHOD OF FORMING A DIRECT DIE CONTACT (DDC) SEMICONDUCTOR PACKAGE
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|
|
Patent #:
|
|
Issue Dt:
|
10/10/2000
|
Application #:
|
08905617
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Filing Dt:
|
08/04/1997
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Title:
|
METHOD OF FORMING AN ISOLATION STRUCTURE IN A SEMICONDUCTOR DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08905618
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Filing Dt:
|
08/04/1997
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Title:
|
ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
08906297
|
Filing Dt:
|
08/05/1997
|
Title:
|
METHODS FOR FORMING CONDUCTIVE MICRO-BUMPS AND RECESSED CONTACTS FOR FLIP-CHIP TECHNOLOGY AND METHOD OF FLIP-CHIP ASSEMBLY
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|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
08906568
|
Filing Dt:
|
08/05/1997
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Title:
|
MEMORY DEVICE AND SYSTEM WITH LEAKAGE BLOCKING CIRCUITY
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|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
08906583
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Filing Dt:
|
08/05/1997
|
Title:
|
HIGH RESOLUTION PRESSURE SENSING DEVICE HAVING AN INSULATING FLEXIBLE MATRIX LOADED WITH FILLER PARTICLES
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|
|
Patent #:
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|
Issue Dt:
|
01/11/2000
|
Application #:
|
08906673
|
Filing Dt:
|
08/05/1997
|
Title:
|
METHOD FOR APPLYING ADHESIVES TO A LEAD FRAME
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|
|
Patent #:
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|
Issue Dt:
|
08/29/2000
|
Application #:
|
08906889
|
Filing Dt:
|
08/06/1997
|
Title:
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CONTACT FORMATION USING TWO ANNEAL STEPS
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|
|
Patent #:
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|
Issue Dt:
|
11/16/1999
|
Application #:
|
08907116
|
Filing Dt:
|
08/06/1997
|
Title:
|
KIT FOR ELECTRICALLY ISOLATING COLLIMATOR OF PVD CHAMBER, CHAMBER SO MODIFIED, AND METHOD OF USING
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|
Patent #:
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|
Issue Dt:
|
11/10/1998
|
Application #:
|
08907275
|
Filing Dt:
|
08/06/1997
|
Title:
|
MEMORY DEVICE EQUILIBRATION CIRCUIT AND METHOD
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|
|
Patent #:
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|
Issue Dt:
|
04/18/2000
|
Application #:
|
08907330
|
Filing Dt:
|
08/06/1997
|
Title:
|
METHOD AND APPARATUS FOR EPOXY LOC DIE ATTACHMENT
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|
|
Patent #:
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|
Issue Dt:
|
05/30/2000
|
Application #:
|
08908234
|
Filing Dt:
|
08/07/1997
|
Title:
|
METHOD FOR MULTIPLE STAGED POWER UP OF INTEGRATED CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
06/10/2003
|
Application #:
|
08908242
|
Filing Dt:
|
08/07/1997
|
Title:
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SERIAL COMMAND PORT METHOD, CIRCUIT, AND SYSTEM INCLUDING MAIN AND COMMAND CLOCK GENERATORS TO FILTER SIGNALS OF LESS THAN A PREDETERMINED DURATION
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|
|
Patent #:
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|
Issue Dt:
|
08/21/2001
|
Application #:
|
08908425
|
Filing Dt:
|
08/07/1997
|
Title:
|
STRESS REDUCTION FEATURE FOR LOC LEAD FRAME
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|
|
Patent #:
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|
Issue Dt:
|
02/22/2000
|
Application #:
|
08908486
|
Filing Dt:
|
08/07/1997
|
Title:
|
AUTOMATIC PIPELINE RELOADING OF SERIAL READ PIPELINE ON LAST BIT TRANSFERS TO SERIAL ACCESS MEMORY
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|
|
Patent #:
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|
Issue Dt:
|
09/28/1999
|
Application #:
|
08908688
|
Filing Dt:
|
08/07/1997
|
Title:
|
MULTI-CHIP MODULE SYSTEM
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|
|
Patent #:
|
|
Issue Dt:
|
07/13/1999
|
Application #:
|
08908830
|
Filing Dt:
|
08/08/1997
|
Title:
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METHOD FOR SHARPENING EMITTER SITES USING LOW TEMPERATURE OXIDATION PROCESSES
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|
|
Patent #:
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|
Issue Dt:
|
09/28/1999
|
Application #:
|
08909228
|
Filing Dt:
|
08/11/1997
|
Title:
|
TRANSFER MOLDING ENCAPSULATION OF A SEMICONDUCTOR DIE WITH ATTACHED HEAT SINK
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|
|
Patent #:
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|
Issue Dt:
|
04/11/2000
|
Application #:
|
08909230
|
Filing Dt:
|
08/11/1997
|
Title:
|
LEAD PENETRATING CLAMPING SYSTEM
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|
|
Patent #:
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|
Issue Dt:
|
08/31/1999
|
Application #:
|
08909294
|
Filing Dt:
|
08/11/1997
|
Title:
|
STRUCTURE FOR ATTACHING A SEMICONDUCTOR WAFER SECTION TO A SUPPORT
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|
|
Patent #:
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|
Issue Dt:
|
05/08/2001
|
Application #:
|
08909345
|
Filing Dt:
|
08/11/1997
|
Title:
|
ION IMPLANTATION WITH PROGRAMMABLE ENERGY, ANGLE, AND BEAM CURRENT
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|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
08909570
|
Filing Dt:
|
08/12/1997
|
Title:
|
METHOD AND APPARATUS FOR VERIFYING THE PRESENCE OR ABSENCE OF A COMPONENT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/1999
|
Application #:
|
08909572
|
Filing Dt:
|
08/12/1997
|
Title:
|
PROCESS LIQUID DISPENSE METHOD AND APPARATUS
|
|
|
Patent #:
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|
Issue Dt:
|
01/04/2000
|
Application #:
|
08909683
|
Filing Dt:
|
08/12/1997
|
Title:
|
ANISOTROPIC CONDUCTIVE INTERCONNECT MATERIAL FOR ELECTRONIC DEVICES, METHOD OF USE OF RESULTING PRODUCT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
08909785
|
Filing Dt:
|
08/12/1997
|
Title:
|
SURFACE MOUNT IC USING SILICON VIAS IN AN AREA ARRAY FORMAT OR SAME SIZE AS DIE ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
08909931
|
Filing Dt:
|
08/12/1997
|
Title:
|
LEAD FRAME INCLUDING ANGLE IRON TIE BAR AND METHOD OF MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08910299
|
Filing Dt:
|
08/11/1997
|
Title:
|
UNDERFILL OF BUMPED OR RAISED DIE USING A BARRIER ADJACENT TO THE SIDEWALL OF SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08910701
|
Filing Dt:
|
08/13/1997
|
Title:
|
APPARATUS AND METHOD FOR STABILIZATION OF THRESHOLD VOLTAGE IN FIELD EMISSION DISPLAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
08910908
|
Filing Dt:
|
08/13/1997
|
Title:
|
METHODS OF FORMING REFRACTORY METAL SILICIDE COMPONENTS AND METHODS OF RESTRICTING SILICON SURFACE MIGRATION OF A SILICON STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/1999
|
Application #:
|
08910969
|
Filing Dt:
|
08/07/1997
|
Title:
|
FAST POWER UP REFERENCE VOLTAGE CIRCUIT AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/1999
|
Application #:
|
08911074
|
Filing Dt:
|
08/14/1997
|
Title:
|
CIRCUIT AND METHOD FOR A MEMORY DEVICE WITH P-CHANNEL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08911151
|
Filing Dt:
|
08/14/1997
|
Title:
|
METHOD FOR IMPROVED BOTTOM AND SIDE WALL COVERAGE OF HIGH ASPECT RATIO FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/1999
|
Application #:
|
08911329
|
Filing Dt:
|
08/14/1997
|
Title:
|
TRACKING SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/1999
|
Application #:
|
08911389
|
Filing Dt:
|
08/14/1997
|
Title:
|
LASER WIRE BONDING FOR WIRE EMBEDDED DIELECTRICS TO INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
08911498
|
Filing Dt:
|
08/14/1997
|
Title:
|
CIRCUIT FOR SRAM TEST MODE ISOLATED BITLINE MODULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/1999
|
Application #:
|
08911552
|
Filing Dt:
|
08/14/1997
|
Title:
|
METHOD AND MEMORY DEVICE FOR DYNAMIC CELL PLATE SENSING WITH AC EQUILIBRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/1999
|
Application #:
|
08911582
|
Filing Dt:
|
08/14/1997
|
Title:
|
LASER WIRE BONDING FOR WIRE EMBEDDED DIELECTRICS TO INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2000
|
Application #:
|
08911669
|
Filing Dt:
|
08/14/1997
|
Title:
|
LAYOUT FOR A SEMICONDUCTOR MEMORY DEVICE WHEREIN INTERCOUPLING LINES ARE SHARED BY TWO SETS OF FUSE BANKS AND TWO SETS OF REDUNDANT ELEMENTS NOT SIMULTANEOUSLY ACTIVE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
08911897
|
Filing Dt:
|
08/15/1997
|
Title:
|
FREQUENCY ADJUSTABLE, ZERO TEMPERATURE COEFFICIENT REFERENCING RING OSCILLATOR CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08912050
|
Filing Dt:
|
08/18/1997
|
Title:
|
METHOD FOR FORMING DIELECTRIC WITHIN A RECESS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
08912051
|
Filing Dt:
|
08/18/1997
|
Title:
|
METALLIZATION LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08912108
|
Filing Dt:
|
08/04/1997
|
Title:
|
METHODS OF FORMING INTEGRATED CIRCUITRY AND INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
08912347
|
Filing Dt:
|
08/18/1997
|
Title:
|
METHOD OF IMPROVING RESIST ADHESION FOR USE IN PATTERNING CONDUCTIVE LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/1999
|
Application #:
|
08912380
|
Filing Dt:
|
08/18/1997
|
Title:
|
MULTI-LAYER ABSTRACTION BUCKET MECHANISM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/1999
|
Application #:
|
08912875
|
Filing Dt:
|
08/15/1997
|
Title:
|
N-CHANNEL VOLTAGE REGULATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/1998
|
Application #:
|
08912900
|
Filing Dt:
|
08/15/1997
|
Title:
|
CAPACITOR CONSTRUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2000
|
Application #:
|
08914072
|
Filing Dt:
|
08/18/1997
|
Title:
|
VT CANCELLATION IN OUTPUT STAGE 0F CHARGE PUMP
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
08914369
|
Filing Dt:
|
08/19/1997
|
Title:
|
METHODS OF FORMING SRAM CELLS AND PAIRS OF FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2000
|
Application #:
|
08914417
|
Filing Dt:
|
08/19/1997
|
Title:
|
MULTIPLE IMAGE RETICLE FOR FORMING LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08914469
|
Filing Dt:
|
08/19/1997
|
Title:
|
METHOD FOR FABRICATING MICROBUMP INTERCONNECT FOR BARE SEMICONDUCTOR DICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/29/2000
|
Application #:
|
08914509
|
Filing Dt:
|
08/19/1997
|
Title:
|
PROCESSING COMPOSITIONS AND METHODS OF USING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08914515
|
Filing Dt:
|
08/19/1997
|
Title:
|
DEVICE AND METHOD FOR STACKING WIRE-BONDED INTEGRATED CIRCUIT DICE ON FLIP-CHIP BONDED INTEGRATED CIRCUIT DICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/1999
|
Application #:
|
08914571
|
Filing Dt:
|
08/19/1997
|
Title:
|
MASK FOR FORMING FEATURES ON A SEMICONDUCTOR SUBSTRATE AND A METHOD FOR FORMING THE MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/1999
|
Application #:
|
08914718
|
Filing Dt:
|
08/19/1997
|
Title:
|
HYBRID FRAME WITH LEAD-LOCK TAPE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2000
|
Application #:
|
08914719
|
Filing Dt:
|
08/19/1997
|
Title:
|
DEVICE AND METHOD FOR STACKING WIRE-BONDED INTEGRATED CIRCUIT DICE ON FLIP-CHIP BONDED INTEGRATED CIRCUIT DICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
08914935
|
Filing Dt:
|
08/20/1997
|
Title:
|
METHOD AND COMPOSITION FOR SELECTIVELY ETCHING AGAINST COBALT SILICIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
08914979
|
Filing Dt:
|
08/20/1997
|
Title:
|
UNDERFILL COATING FOR LOC PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
08914994
|
Filing Dt:
|
08/20/1997
|
Title:
|
" METHOD & APPARATUS FOR PREDICTING PROCESS CHARACTERISTICS OF POLYURETHANE PADS"
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
08915006
|
Filing Dt:
|
08/20/1997
|
Title:
|
SUSPENSIONS AND METHODS FOR DEPOSITION OF LUMINESCENT MATERIALS AND ARTICLES PRODUCED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
08915074
|
Filing Dt:
|
08/20/1997
|
Title:
|
METHOD AND APPARATUS FOR TESTING MEMORY DEVICES AND DISPLAYING RESULTS OF SUCH TESTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/1999
|
Application #:
|
08915075
|
Filing Dt:
|
08/20/1997
|
Title:
|
SHARED PULL-UP AND SELECTION CIRCUITRY FOR PROGRAMMABLE CELLS SUCH AS ANTIFUSE CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
08915157
|
Filing Dt:
|
08/20/1997
|
Title:
|
WAFER SURFACE TREATMENT METHODS AND SYSTEMS USING ELECTROCAPILLARITY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2000
|
Application #:
|
08915159
|
Filing Dt:
|
08/20/1997
|
Title:
|
SINGULATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/1999
|
Application #:
|
08915186
|
Filing Dt:
|
08/20/1997
|
Title:
|
EQUILIBRATE CIRCUIT FOR DYNAMIC PLATE SENSING MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
08915190
|
Filing Dt:
|
08/20/1997
|
Title:
|
METHOD AND APPARATUS FOR REPLACING A DEFECTIVE INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08915193
|
Filing Dt:
|
08/20/1997
|
Title:
|
METHOD FOR CLEANING WASTE MATTER FROM THE BACKSIDE OF A SEMICONDUCTOR WAFER SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08915197
|
Filing Dt:
|
08/20/1997
|
Title:
|
ULTRA HIGH DENSITY FLASH MEMORY HAVING VERTICALLY STACKED DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
08915211
|
Filing Dt:
|
08/20/1997
|
Title:
|
METHOD OF DEPOSITING A THERMOPLASTIC POLYMER IN SEMICONDUCTOR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/1999
|
Application #:
|
08915215
|
Filing Dt:
|
08/20/1997
|
Title:
|
METHOD AND APPARATUS FOR REPROGRAMMING A SUPERVOLTAGE CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
08915312
|
Filing Dt:
|
08/20/1997
|
Title:
|
SHARED PULL-UP AND SELECTION CIRCUITRY FOR PROGRAMMABLE CELLS SUCH AS ANTIFUSE CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2000
|
Application #:
|
08915313
|
Filing Dt:
|
08/20/1997
|
Title:
|
METHOD AND APPARATUS FOR DETECTING INTERCELL DEFECTS IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
08915386
|
Filing Dt:
|
08/20/1997
|
Title:
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SELF-ALIGNED CONTACT FORMATION FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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09/28/1999
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Application #:
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08915422
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Filing Dt:
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08/20/1997
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Title:
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UNDERFILL COATING FOR LOC PACKAGE
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08915517
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Filing Dt:
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08/13/1997
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Title:
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METHOD FOR CLEANING SEMICONDUCTOR WAFERS AND EQUIPMENT
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Patent #:
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Issue Dt:
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04/20/2010
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Application #:
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08915658
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Filing Dt:
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08/21/1997
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Title:
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LOW RESISTANCE METAL SILICIDE LOCAL INTERCONNECTS AND A METHOD OF MAKING
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Patent #:
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Issue Dt:
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06/20/2000
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Application #:
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08915849
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Filing Dt:
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08/21/1997
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Title:
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CREATING LAYOUT FOR INTEGRATED CIRCUIT STRUCTURES
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08915853
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Filing Dt:
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08/21/1997
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Title:
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COLUMN SELECT LATCH FOR SDRAM
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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08915855
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Filing Dt:
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08/21/1997
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Title:
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DEVICE FOR THE PROTECTION OF STORED DATA USING A TIME DELAY CIRCUIT
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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08915885
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Filing Dt:
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08/21/1997
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Title:
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METHOD AND SYSTEM FOR TRACKING MANUFACTURING DATA FOR INTEGRATED CIRCUIT PARTS
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Patent #:
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Issue Dt:
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02/23/1999
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Application #:
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08915888
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Filing Dt:
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08/21/1997
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Title:
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CVD METHOD FOR FORMING METAL-CONTAINING FILMS
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Patent #:
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Issue Dt:
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07/06/1999
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Application #:
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08915951
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Filing Dt:
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08/21/1997
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Title:
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METHOD AND APPARATUS FOR IMPROVING THE STRUCTURAL INTEGRITY OF STACKED CAPACITORS
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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08915987
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Filing Dt:
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08/21/1997
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Title:
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METHOD OF DEPOSITING SILICON OXIDES
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Patent #:
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Issue Dt:
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06/29/1999
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Application #:
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08916024
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Filing Dt:
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08/21/1997
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Title:
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DEPLETION COMPENSATED POLYSILICON ELECTRODES
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Patent #:
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Issue Dt:
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07/28/1998
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Application #:
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08916054
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Filing Dt:
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08/21/1997
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Title:
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DEVICE FOR THE PROTECTION OF STORED DATA
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Patent #:
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Issue Dt:
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05/25/1999
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Application #:
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08916112
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Filing Dt:
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08/21/1997
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Title:
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APPARATUS AND METHOD FOR EXTRACTING BROKEN THREADED MEMBERS
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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08916114
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Filing Dt:
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08/21/1997
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Title:
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SEMICONDUCTOR RELIABILITY TEST CHIP
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Patent #:
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Issue Dt:
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06/15/1999
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Application #:
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08916117
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Filing Dt:
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08/21/1997
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Title:
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MEMORY CELL ARCHITECTURE ULITILIZING A TRANSISTOR HAVING A DUAL ACCESS GATE
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Patent #:
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Issue Dt:
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07/20/1999
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Application #:
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08916182
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Filing Dt:
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08/21/1997
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Title:
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CONTENT ADDRESSABLE BIT REPLACEMENT MEMORY
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Patent #:
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Issue Dt:
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04/25/2000
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Application #:
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08916219
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Filing Dt:
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08/22/1997
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Title:
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COPPER ELECTROLESS DEPOSITION ON A TITANIUM-CONTAINING SURFACE
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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08916275
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Filing Dt:
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08/22/1997
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Title:
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TITANIUM BORIDE GATE ELECTRODE AND INTERCONNECT AND METHODS REGARDING SAME
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Patent #:
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Issue Dt:
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09/19/2000
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Application #:
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08916276
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Filing Dt:
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08/22/1997
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Title:
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ISOLATION USING AN ANTIREFLECTIVE COATING
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Patent #:
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Issue Dt:
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12/08/1998
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Application #:
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08916356
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Filing Dt:
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08/22/1997
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Title:
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LOCAL INTERCONNECT COMPRISING TITANIUM NITRIDE BARRIER LAYER
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Patent #:
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Issue Dt:
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06/06/2000
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Application #:
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08916434
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Filing Dt:
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08/22/1997
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Title:
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SYSTEM FOR TESTING SEMICONDUCTOR COMPONENTS
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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08916584
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Filing Dt:
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08/22/1997
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Title:
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SYNCHRONOUS MEMORY WITH PROGRAMMABLE READ LATENCY
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Patent #:
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Issue Dt:
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03/23/1999
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Application #:
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08916603
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Filing Dt:
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08/22/1997
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Title:
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HIGH AND NEGATIVE VOLTAGE COMPARE
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