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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:039708/0001   Pages: 123
Recorded: 08/11/2016
Attorney Dkt #:3483.000
Conveyance: PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS
Total properties: 2101
Page 12 of 22
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
1
Patent #:
Issue Dt:
06/12/2007
Application #:
10147828
Filing Dt:
05/17/2002
Title:
RANDOM NUMBER GENERATOR
2
Patent #:
Issue Dt:
03/23/2004
Application #:
10150179
Filing Dt:
05/16/2002
Title:
CASCADABLE BUS BASED CROSSBAR SWITCHING IN A PROGRAMMABLE LOGIC DEVICE
3
Patent #:
Issue Dt:
11/05/2002
Application #:
10150556
Filing Dt:
05/17/2002
Title:
METHOD FOR FABRICATING SELF-ALIGNED GATE OF FLASH MEMORY CELL
4
Patent #:
Issue Dt:
08/03/2004
Application #:
10151127
Filing Dt:
05/16/2002
Title:
METHODS OF FORMING SEMICONDUCTOR STRUCTURES, AND ARTICLES AND DEVICES FORMED THEREBY
5
Patent #:
Issue Dt:
11/29/2005
Application #:
10151669
Filing Dt:
05/20/2002
Title:
REDUCING TESTER CHANNELS FOR HIGH PINOUT INTEGRATED CIRCUITS
6
Patent #:
Issue Dt:
03/15/2005
Application #:
10152590
Filing Dt:
05/21/2002
Title:
BOLTLESS CARRIER RING/CARRIER PLATE ATTACHMENT ASSEMBLY
7
Patent #:
Issue Dt:
09/26/2006
Application #:
10154089
Filing Dt:
05/23/2002
Title:
PROBE FOR TESTING INTEGRATED CIRCUITS
8
Patent #:
Issue Dt:
11/04/2003
Application #:
10159323
Filing Dt:
05/31/2002
Title:
METHOD FOR INCREASING CORE GAIN IN FLASH MEMORY DEVICE USING STRAINED SILICON
9
Patent #:
Issue Dt:
07/18/2006
Application #:
10160442
Filing Dt:
05/31/2002
Title:
USB DEVICE COMMUNICATION
10
Patent #:
Issue Dt:
05/03/2005
Application #:
10175139
Filing Dt:
06/19/2002
Title:
SELF ALIGNED METAL INTERCONNECTION AND METHOD OF MAKING THE SAME
11
Patent #:
Issue Dt:
09/09/2003
Application #:
10176594
Filing Dt:
06/21/2002
Title:
USE OF HIGH-K DIELECTRIC MATERIAL FOR ONO AND TUNNEL OXIDE TO IMPROVE FLOATING GATE FLASH MEMORY COUPLING
12
Patent #:
Issue Dt:
10/31/2006
Application #:
10176976
Filing Dt:
06/21/2002
Title:
SUBSTRATE CONFIGURABLE JTAG ID SCHEME
13
Patent #:
Issue Dt:
01/02/2007
Application #:
10177545
Filing Dt:
06/20/2002
Title:
METHOD FOR ISSUING VENDOR SPECIFIC REQUESTS FOR ACCESSING ASIC CONFIGURATION AND DESCRIPTOR MEMORY WHILE STILL USING A MASS STORAGE CLASS DRIVER
14
Patent #:
Issue Dt:
11/08/2005
Application #:
10177802
Filing Dt:
06/21/2002
Title:
DEVICE ENUMERATION CURRENT REDUCTION
15
Patent #:
Issue Dt:
08/01/2006
Application #:
10177818
Filing Dt:
06/21/2002
Title:
ATA DEVICE ACCESS SYSTEM WITH SURROGATE REGISTERS CORRESPONDING TO ATA REGISTERS
16
Patent #:
Issue Dt:
06/24/2003
Application #:
10178106
Filing Dt:
06/24/2002
Title:
INNOVATIVE NARROW GATE FORMATION FOR FLOATING GATE FLASH TECHNOLOGY
17
Patent #:
Issue Dt:
11/11/2003
Application #:
10178144
Filing Dt:
06/24/2002
Title:
EXTRACTION OF DRAIN JUNCTION OVERLAP WITH THE GATE AND THE CHANNEL LENGTH FOR ULTRA-SMALL CMOS DEVICES WITH ULTRA-THIN GATE OXIDES
18
Patent #:
Issue Dt:
04/15/2003
Application #:
10179061
Filing Dt:
06/24/2002
Title:
NOVEL CAPPING LAYER
19
Patent #:
Issue Dt:
01/27/2004
Application #:
10180695
Filing Dt:
06/26/2002
Title:
MAGNETIC MEMORY CELL AND METHOD FOR ASSIGNING TUNABLE WRITING CURRENTS
20
Patent #:
Issue Dt:
09/12/2006
Application #:
10183141
Filing Dt:
06/25/2002
Title:
EARLY DETECTION AND GRANT, AN ARBITRATION SCHEME FOR SINGLE TRANSFERS ON AMBA ADVANCED HIGH-PERFORMANCE BUS
21
Patent #:
Issue Dt:
09/28/2004
Application #:
10184232
Filing Dt:
06/28/2002
Title:
ASYMMETRIC DOT SHAPE FOR INCREASING SELECT-UNSELECT MARGIN IN MRAM DEVICES
22
Patent #:
Issue Dt:
09/13/2005
Application #:
10184419
Filing Dt:
06/27/2002
Title:
METHOD TO FACILITATE TESTING OF LASER FUSES
23
Patent #:
Issue Dt:
10/12/2004
Application #:
10184697
Filing Dt:
06/28/2002
Title:
BIPOLAR TRANSISTOR AND METHOD FOR MAKING THE SAME
24
Patent #:
Issue Dt:
08/14/2007
Application #:
10185646
Filing Dt:
06/28/2002
Title:
NITRIDE LAYER ON A GATE STACK
25
Patent #:
Issue Dt:
12/20/2011
Application #:
10186453
Filing Dt:
06/28/2002
Title:
GATE STACK HAVING NITRIDE LAYER
26
Patent #:
Issue Dt:
10/25/2005
Application #:
10186465
Filing Dt:
06/28/2002
Title:
CONFIGURABLE USB INTERFACE WITH VIRTUAL REGISTER ARCHITECTURE
27
Patent #:
Issue Dt:
03/18/2008
Application #:
10186910
Filing Dt:
06/28/2002
Title:
ENABLING MULTIPLE ATA DEVICES USING A SINGLE BUS BRIDGE
28
Patent #:
Issue Dt:
09/30/2003
Application #:
10189651
Filing Dt:
07/03/2002
Title:
MEMORY DEVICE AND METHOD OF MAKING
29
Patent #:
Issue Dt:
02/22/2005
Application #:
10190420
Filing Dt:
07/03/2002
Title:
TEST STRUCTURE FOR MEASURING EFFECT OF TRENCH ISOLATION ON OXIDE IN A MEMORY DEVICE
30
Patent #:
Issue Dt:
05/18/2004
Application #:
10190916
Filing Dt:
07/08/2002
Title:
CHARGE PUMP CIRCUIT
31
Patent #:
Issue Dt:
03/15/2005
Application #:
10191546
Filing Dt:
07/10/2002
Publication #:
Pub Dt:
01/15/2004
Title:
METHOD OF 193 NM PHOTORESIST STABILIZATION BY THE USE OF ION IMPLANTATION
32
Patent #:
Issue Dt:
06/01/2004
Application #:
10196106
Filing Dt:
07/15/2002
Title:
METHOD AND APPARATUS FOR CONFIGURING AN INTERFACE CONTROLLER
33
Patent #:
Issue Dt:
05/18/2004
Application #:
10197152
Filing Dt:
07/15/2002
Title:
SYSTEM FOR RECONFIGURING A PERIPHERAL DEVICE USING CONFIGRUATION RESIDING ON THE PERIPHERAL DEVICE BY ELECTRONICALLY SIMULATING A PHYSICAL DISCONNECTION AND RECONNECTION TO A HOST DEVICE
34
Patent #:
Issue Dt:
08/08/2006
Application #:
10198418
Filing Dt:
07/17/2002
Title:
METHOD AND APPARATUS FOR INTERRUPT SIGNALING IN A COMMUNICATION NETWORK
35
Patent #:
Issue Dt:
06/15/2004
Application #:
10199793
Filing Dt:
07/19/2002
Title:
NONVOLATILE MEMORY CELL WITH A NITRIDATED OXIDE LAYER
36
Patent #:
Issue Dt:
03/07/2006
Application #:
10200518
Filing Dt:
07/22/2002
Title:
ADDRESS SEQUENCER WITHIN BIST (BUILT-IN-SELF-TEST) SYSTEM
37
Patent #:
Issue Dt:
04/11/2006
Application #:
10200526
Filing Dt:
07/22/2002
Title:
DIAGNOSTIC MODE FOR TESTING FUNCTIONALITY OF BIST (BUILT-IN-SELF-TEST) BACK-END STATE MACHINE
38
Patent #:
Issue Dt:
02/15/2005
Application #:
10207056
Filing Dt:
07/30/2002
Publication #:
Pub Dt:
06/05/2003
Title:
SEMICONDUCTOR MEMORY AND METHOD OF DRIVING THE SAME
39
Patent #:
Issue Dt:
07/06/2004
Application #:
10209088
Filing Dt:
07/30/2002
Title:
ARRAY OF DICE FOR TESTING INTEGRATED CIRCUITS
40
Patent #:
Issue Dt:
03/14/2006
Application #:
10211317
Filing Dt:
08/05/2002
Title:
NON-VOLATILE MEMORY DEVICE
41
Patent #:
Issue Dt:
03/30/2004
Application #:
10214149
Filing Dt:
08/08/2002
Publication #:
Pub Dt:
12/19/2002
Title:
CURRENT PULSE RECEIVING CIRCUIT
42
Patent #:
Issue Dt:
02/24/2004
Application #:
10217807
Filing Dt:
08/12/2002
Title:
METHOD OF PROTECTING A STACKED GATE STRUCTURE DURING FABRICATION
43
Patent #:
Issue Dt:
03/08/2005
Application #:
10217965
Filing Dt:
08/12/2002
Title:
METHOD AND SYSTEM FOR DETECTING TUNNEL OXIDE ENCROACHMENT ON A MEMORY DEVICE
44
Patent #:
Issue Dt:
06/24/2008
Application #:
10218504
Filing Dt:
08/13/2002
Title:
METHOD AND SYSTEM FOR PROVIDING HYBRID CLOCK DISTRIBUTION
45
Patent #:
Issue Dt:
07/06/2004
Application #:
10224737
Filing Dt:
08/20/2002
Title:
METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A GATE CURRENT MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND DEVICE THEREBY FORMED
46
Patent #:
Issue Dt:
04/26/2005
Application #:
10225052
Filing Dt:
08/20/2002
Title:
METHOD OF FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE BY DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING AN OVERDRIVE CURRENT MEASUREMENT TECHNIQUE AND A DEVICE THEREBY FABRICATED
47
Patent #:
Issue Dt:
10/05/2004
Application #:
10228436
Filing Dt:
08/27/2002
Title:
BUFFER CIRCUIT
48
Patent #:
Issue Dt:
11/01/2005
Application #:
10229432
Filing Dt:
08/27/2002
Title:
DEVICE, SYSTEM AND METHOD FOR AN INTEGRATED CIRCUIT ADAPTABLE FOR USE IN COMPUTING SYSTEMS OF DIFFERING MEMORY REQUIREMENTS
49
Patent #:
Issue Dt:
03/04/2008
Application #:
10230184
Filing Dt:
08/27/2002
Title:
METHOD AND SYSTEM FOR SUPPLEMENTING CURRENT DURING ENUMERATION OF A USB DEVICE
50
Patent #:
Issue Dt:
12/07/2004
Application #:
10232487
Filing Dt:
08/30/2002
Title:
FLOATING GATE MEMORY DEVICE WITH HOMOGENEOUS OXYNITRIDE TUNNELING DIELECTRIC
51
Patent #:
Issue Dt:
04/19/2005
Application #:
10232586
Filing Dt:
08/30/2002
Publication #:
Pub Dt:
03/04/2004
Title:
BURIED-CHANNEL TRANSISTOR WITH REDUCED LEAKAGE CURRENT
52
Patent #:
Issue Dt:
05/18/2004
Application #:
10232920
Filing Dt:
08/30/2002
Title:
METHOD AND CIRCUIT FOR READING A POTENTIOMETER
53
Patent #:
Issue Dt:
06/01/2004
Application #:
10233906
Filing Dt:
09/03/2002
Title:
FLASH MEMORY ARRAY WITH DUAL FUNCTION CONTROL LINES AND ASYMMETRICAL SOURCE AND DRAIN JUNCTIONS
54
Patent #:
Issue Dt:
09/20/2005
Application #:
10234680
Filing Dt:
09/04/2002
Title:
FIFO MEMORY SYSTEM AND METHOD
55
Patent #:
Issue Dt:
05/17/2005
Application #:
10235160
Filing Dt:
09/05/2002
Title:
SYSTEM AND METHOD FOR FABRICATING OPENINGS IN A SEMICONDUCTOR TOPOGRAPHY
56
Patent #:
Issue Dt:
02/10/2004
Application #:
10237720
Filing Dt:
09/10/2002
Publication #:
Pub Dt:
12/26/2002
Title:
GAIN VARIABLE AMPLIFIER
57
Patent #:
Issue Dt:
11/09/2004
Application #:
10238880
Filing Dt:
09/11/2002
Publication #:
Pub Dt:
03/20/2003
Title:
MEMORY DEVICE
58
Patent #:
Issue Dt:
11/23/2004
Application #:
10241040
Filing Dt:
09/11/2002
Title:
LOCALIZED FIELD-INDUCING LINE AND METHOD FOR MAKING THE SAME
59
Patent #:
Issue Dt:
08/10/2004
Application #:
10243108
Filing Dt:
09/13/2002
Title:
MEMORY WORDLINE SPACER
60
Patent #:
Issue Dt:
04/27/2004
Application #:
10243433
Filing Dt:
09/12/2002
Title:
PATH GATE DRIVER CIRCUIT
61
Patent #:
Issue Dt:
09/30/2003
Application #:
10244129
Filing Dt:
09/13/2002
Title:
A VOID-FREE INTERLAYER DIELECTRIC (ILD0) FOR 0.18-MICRON FLASH MEMORY SEMICONDUCTOR DEVICE
62
Patent #:
Issue Dt:
12/09/2003
Application #:
10244229
Filing Dt:
09/16/2002
Title:
HIGH DENSITY FLOATING GATE FLASH MEMORY AND FABRICATION PROCESSES THEREFOR
63
Patent #:
Issue Dt:
03/14/2006
Application #:
10244591
Filing Dt:
09/17/2002
Publication #:
Pub Dt:
03/18/2004
Title:
ORGANIC THIN FILM ZENER DIODES
64
Patent #:
Issue Dt:
10/05/2004
Application #:
10251091
Filing Dt:
09/20/2002
Publication #:
Pub Dt:
03/25/2004
Title:
LOT-OPTIMIZED WAFER LEVEL BURN-IN
65
Patent #:
Issue Dt:
03/21/2006
Application #:
10253960
Filing Dt:
09/24/2002
Title:
SIMULTANEOUSLY DRIVING A HARDWARE DEVICE AND A SOFTWARE MODEL DURING A TEST
66
Patent #:
Issue Dt:
05/30/2006
Application #:
10256502
Filing Dt:
09/26/2002
Title:
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR DESIGNING AN INTEGRATED CIRCUIT USING SUBSTITUTION OF STANDARD CELLS WITH SUBSTITUTE CELLS HAVING DIFFERING ELECTRICAL CHARACTERISTICS
67
Patent #:
Issue Dt:
02/07/2012
Application #:
10256830
Filing Dt:
09/27/2002
Title:
SINGLE CYCLE REDUCED COMPLEXITY CPU
68
Patent #:
Issue Dt:
08/15/2006
Application #:
10256831
Filing Dt:
09/27/2002
Title:
TEMPERATURE-CONTROLLED GAS MICROSCOPE
69
Patent #:
Issue Dt:
07/04/2006
Application #:
10256964
Filing Dt:
09/27/2002
Title:
MICROSCOPE WITH OBJECTIVE LENS POSITION CONTROL APPARATUS
70
Patent #:
Issue Dt:
07/01/2008
Application #:
10260054
Filing Dt:
09/27/2002
Title:
SYSTEM, METHOD, AND APPARATUS FOR CONNECTING USB PERIPHERALS AT EXTENDED DISTANCES FROM A HOST COMPUTER
71
Patent #:
Issue Dt:
11/09/2004
Application #:
10260061
Filing Dt:
09/27/2002
Title:
FLASH MEMORY HAVING IMPROVED CORE FIELD ISOLATION IN SELECT GATE REGIONS
72
Patent #:
Issue Dt:
06/27/2006
Application #:
10260081
Filing Dt:
09/27/2002
Title:
DEVICE AND METHOD FOR ADAPTING SPEED OF A USB DEVICE BASED ON AVAILABLE POWER
73
Patent #:
Issue Dt:
11/06/2007
Application #:
10260109
Filing Dt:
09/27/2002
Title:
APPARATUS AND METHOD FOR DYNAMICALLY PROVIDING HUB OR HOST OPERATIONS
74
Patent #:
Issue Dt:
10/25/2011
Application #:
10260129
Filing Dt:
09/27/2002
Title:
METHOD AND SYSTEM USING SUBGRAPH ISOMORPHISM TO CONFIGURE HARDWARE RESOURCES
75
Patent #:
Issue Dt:
12/21/2004
Application #:
10265001
Filing Dt:
10/04/2002
Title:
METHOD FOR REDUCING DRAIN INDUCED BARRIER LOWERING IN A MEMORY DEVICE
76
Patent #:
Issue Dt:
09/14/2004
Application #:
10269391
Filing Dt:
10/11/2002
Title:
MEMORY DEVICE PROVIDING ASYNCHRONOUS AND SYNCHRONOUS DATA TRANSFER
77
Patent #:
Issue Dt:
10/07/2003
Application #:
10274063
Filing Dt:
10/17/2002
Title:
BI-LAYER FLOATING GATE FOR IMPROVED WORK FUNCTION BETWEEN FLOATING GATE AND A HIGH-K DIELECTRIC LAYER
78
Patent #:
Issue Dt:
12/27/2005
Application #:
10277541
Filing Dt:
10/22/2002
Title:
VERIFICATION OF INTEGRATED CIRCUIT DESIGNS USING BUFFER CONTROL
79
Patent #:
Issue Dt:
08/24/2004
Application #:
10282459
Filing Dt:
10/29/2002
Title:
BUFFER DRIVER CIRCUIT FOR PRODUCING A FAST, STABLE, AND ACCURATE REFERENCE VOLTAGE
80
Patent #:
Issue Dt:
12/28/2004
Application #:
10284769
Filing Dt:
10/31/2002
Title:
SYSTEM AND METHOD OF FORMING A PASSIVE LAYER BY A CMP PROCESS
81
Patent #:
Issue Dt:
03/15/2005
Application #:
10284866
Filing Dt:
10/30/2002
Publication #:
Pub Dt:
05/06/2004
Title:
NITROGEN OXIDATION TO REDUCE ENCROACHMENT
82
Patent #:
Issue Dt:
05/31/2005
Application #:
10284946
Filing Dt:
10/31/2002
Title:
MULTI-CELL ORGANIC MEMORY ELEMENT AND METHODS OF OPERATING AND FABRICATING
83
Patent #:
Issue Dt:
11/16/2004
Application #:
10285909
Filing Dt:
10/31/2002
Title:
MEMORY DEVICE HAVING RESISTIVE ELEMENT COUPLED TO REFERENCE CELL FOR IMPROVED RELIABILITY
84
Patent #:
Issue Dt:
01/25/2005
Application #:
10287363
Filing Dt:
11/04/2002
Publication #:
Pub Dt:
05/06/2004
Title:
CONTROL OF MEMORY ARRAYS UTILIZING ZENER DIODE-LIKE DEVICES
85
Patent #:
Issue Dt:
03/22/2005
Application #:
10287612
Filing Dt:
11/04/2002
Publication #:
Pub Dt:
05/06/2004
Title:
STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING
86
Patent #:
Issue Dt:
06/14/2005
Application #:
10289020
Filing Dt:
11/05/2002
Title:
METHOD AND STRUCTURE FOR DETERMINING A CONCENTRATION PROFILE OF AN IMPURITY WITHIN A SEMICONDUCTOR LAYER
87
Patent #:
Issue Dt:
04/06/2004
Application #:
10291293
Filing Dt:
11/08/2002
Publication #:
Pub Dt:
04/17/2003
Title:
METHOD OF FORMING FLASH MEMORY HAVING PRE-INTERPOLY DIELECTRIC TREATMENT LAYER
88
Patent #:
Issue Dt:
03/23/2004
Application #:
10292121
Filing Dt:
11/12/2002
Title:
FABRICATION OF SHALLOW TRENCH ISOLATION STRUCTURES WITH ROUNDED CORNER AND SELF-ALIGNED GATE
89
Patent #:
Issue Dt:
04/04/2006
Application #:
10299429
Filing Dt:
11/18/2002
Title:
METHOD AND APPARATUS FOR ATTACHING USB PERIPHERALS TO HOST PORTS
90
Patent #:
Issue Dt:
09/28/2004
Application #:
10301768
Filing Dt:
11/20/2002
Title:
METHOD AND APPARATUS FOR CONVERGING A CONTROL LOOP
91
Patent #:
Issue Dt:
09/05/2006
Application #:
10304762
Filing Dt:
11/27/2002
Publication #:
Pub Dt:
04/17/2003
Title:
SEMICONDUCTOR MEMORY APPARATUS
92
Patent #:
Issue Dt:
10/19/2004
Application #:
10304863
Filing Dt:
11/27/2002
Publication #:
Pub Dt:
02/12/2004
Title:
MEMORY DEVICE
93
Patent #:
Issue Dt:
03/16/2004
Application #:
10305625
Filing Dt:
11/27/2002
Title:
CURRENT STEERING REDUCED BITLINE VOLTAGE SWING, SENSE AMPLIFIER
94
Patent #:
Issue Dt:
12/09/2003
Application #:
10305699
Filing Dt:
11/26/2002
Title:
PARALLEL TEST IN ASYNCHRONOUS MEMORY WITH SINGLE-ENDED OUTPUT PATH
95
Patent #:
Issue Dt:
05/23/2006
Application #:
10305724
Filing Dt:
11/26/2002
Publication #:
Pub Dt:
05/27/2004
Title:
LATERAL DOPED CHANNEL
96
Patent #:
Issue Dt:
05/16/2006
Application #:
10306381
Filing Dt:
11/27/2002
Title:
CLASS AB ANALOG INVERTER
97
Patent #:
Issue Dt:
10/03/2006
Application #:
10306414
Filing Dt:
11/27/2002
Title:
PROCESSES PROVIDING HIGH AND LOW THRESHOLD P-TYPE AND N-TYPE TRANSISTORS
98
Patent #:
Issue Dt:
01/24/2006
Application #:
10309664
Filing Dt:
12/03/2002
Title:
BOUNDARY SCAN REGISTER FOR DIFFERENTIAL CHIP CORE
99
Patent #:
Issue Dt:
03/13/2007
Application #:
10313048
Filing Dt:
12/06/2002
Title:
SELECTIVE OXIDATION OF GATE STACK
100
Patent #:
Issue Dt:
10/12/2004
Application #:
10313049
Filing Dt:
12/06/2002
Title:
NITRIDE SPACER FORMATION
Assignor
1
Exec Dt:
08/11/2016
Assignees
1
198 CHAMPION COURT
SAN JOSE, CALIFORNIA 95134
2
915 DEGUIGNE DRIVE
SUNNYVALE, CALIFORNIA 94088
Correspondence name and address
WSGR, C/O QUI LU, SENIOR PARALEGAL
650 PAGE MILL ROAD
FH 2-1 P12
PALO ALTO, CA 94304

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