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05/07/2015
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07/07/2016
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05/21/2015
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07/14/2016
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07/14/2016
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04/30/2015
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05/07/2015
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06/14/2016
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06/11/2015
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05/07/2015
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01/19/2015
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05/21/2015
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09/13/2016
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05/14/2015
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05/14/2015
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07/12/2016
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01/20/2015
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12/29/2015
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05/28/2015
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05/14/2015
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07/28/2016
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10/25/2016
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05/21/2015
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05/14/2015
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01/23/2015
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07/28/2016
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05/10/2016
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04/19/2016
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06/21/2016
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08/04/2016
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04/26/2016
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02/04/2015
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12/26/2017
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11/03/2015
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11/29/2016
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Application #:
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14613983
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Filing Dt:
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02/04/2015
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Publication #:
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Pub Dt:
|
08/04/2016
| | | | |
Title:
|
METHODS OF FABRICATING NANOWIRE STRUCTURES
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Patent #:
|
|
Issue Dt:
|
02/23/2016
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Application #:
|
14614470
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Filing Dt:
|
02/05/2015
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Title:
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SYSTEM AND METHOD FOR MANAGING CIRCUIT PERFORMANCE AND POWER CONSUMPTION BY SELECTIVELY ADJUSTING SUPPLY VOLTAGE OVER TIME
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|
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Patent #:
|
|
Issue Dt:
|
07/12/2016
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Application #:
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14614489
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Filing Dt:
|
02/05/2015
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Title:
|
METHOD OF FORMING A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR STRUCTURE WITH N-TYPE AND P-TYPE FIELD EFFECT TRANSISTORS HAVING SYMMETRIC SOURCE/DRAIN JUNCTIONS AND OPTIONAL DUAL SILICIDES
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|
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Patent #:
|
|
Issue Dt:
|
05/03/2016
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Application #:
|
14615470
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Filing Dt:
|
02/06/2015
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Title:
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FABRICATING TRANSISTOR(S) WITH RAISED ACTIVE REGIONS HAVING ANGLED UPPER SURFACES
|
|
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Patent #:
|
|
Issue Dt:
|
08/09/2016
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Application #:
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14615529
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Filing Dt:
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02/06/2015
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Publication #:
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Pub Dt:
|
08/11/2016
| | | | |
Title:
|
METHODS OF FORMING A COMPLEX GAA FET DEVICE AT ADVANCED TECHNOLOGY NODES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2015
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Application #:
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14615762
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Filing Dt:
|
02/06/2015
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Publication #:
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Pub Dt:
|
06/25/2015
| | | | |
Title:
|
FINFET INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2016
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Application #:
|
14616226
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Filing Dt:
|
02/06/2015
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Publication #:
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Pub Dt:
|
08/11/2016
| | | | |
Title:
|
INTEGRATED CIRCUITS WITH MIDDLE OF LINE CAPACITANCE REDUCTION IN SELF-ALIGNED CONTACT PROCESS FLOW AND FABRICATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
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Application #:
|
14616614
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Filing Dt:
|
02/06/2015
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Publication #:
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|
Pub Dt:
|
06/04/2015
| | | | |
Title:
|
MULTI-FORMAT READ DRIVE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2017
|
Application #:
|
14616855
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Filing Dt:
|
02/09/2015
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Publication #:
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|
Pub Dt:
|
12/29/2016
| | | | |
Title:
|
PLANAR QUBITS HAVING INCREASED COHERENCE TIMES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2016
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Application #:
|
14617314
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Filing Dt:
|
02/09/2015
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Publication #:
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|
Pub Dt:
|
06/04/2015
| | | | |
Title:
|
Techniques to Form Uniform and Stable Silicide
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2016
|
Application #:
|
14618498
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Filing Dt:
|
02/10/2015
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Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
Title:
|
DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2016
|
Application #:
|
14620233
|
Filing Dt:
|
02/12/2015
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Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
Title:
|
LOCALLY RAISED EPITAXY FOR IMPROVED CONTACT BY LOCAL SILICON CAPPING DURING TRENCH SILICIDE PROCESSINGS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2017
|
Application #:
|
14620273
|
Filing Dt:
|
02/12/2015
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Publication #:
|
|
Pub Dt:
|
08/18/2016
| | | | |
Title:
|
SYSTEMS AND METHODS TO PREVENT INCORPORATION OF A USED INTEGRATED CIRCUIT CHIP INTO A PRODUCT
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|
|
Patent #:
|
|
Issue Dt:
|
10/20/2015
|
Application #:
|
14621039
|
Filing Dt:
|
02/12/2015
|
Publication #:
|
|
Pub Dt:
|
06/04/2015
| | | | |
Title:
|
LATERAL ETCH STOP FOR NEMS RELEASE ETCH FOR HIGH DENSITY NEMS/CMOS MONOLITHIC INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
14621785
|
Filing Dt:
|
02/13/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
TITANIUM OXYNITRIDE HARD MASK FOR LITHOGRAPHIC PATTERNING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2018
|
Application #:
|
14622997
|
Filing Dt:
|
02/16/2015
|
Publication #:
|
|
Pub Dt:
|
08/18/2016
| | | | |
Title:
|
MODIFIED TUNGSTEN SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2019
|
Application #:
|
14623115
|
Filing Dt:
|
02/16/2015
|
Publication #:
|
|
Pub Dt:
|
08/18/2016
| | | | |
Title:
|
MODIFIED TUNGSTEN SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
14623720
|
Filing Dt:
|
02/17/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
III-V Device with Overlapped Extension Regions Using Replacement Gate
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
14623732
|
Filing Dt:
|
02/17/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
III-V FET Device with Overlapped Extension Regions Using Gate Last
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2018
|
Application #:
|
14624601
|
Filing Dt:
|
02/18/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
LASER ASHING OF POLYIMIDE FOR SEMICONDUCTOR MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2017
|
Application #:
|
14624907
|
Filing Dt:
|
02/18/2015
|
Publication #:
|
|
Pub Dt:
|
08/18/2016
| | | | |
Title:
|
SYSTEM AND METHOD FOR IDENTIFYING OPERATING TEMPERATURES AND MODIFYING OF INTEGRATED CIRCUITS
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|
|
Patent #:
|
|
Issue Dt:
|
09/25/2018
|
Application #:
|
14626191
|
Filing Dt:
|
02/19/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
SCANNING PROBE WITH TWIN-NANOPORE OR A-SINGLE-NANOPORE FOR SENSING BIOMOLECULES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2016
|
Application #:
|
14628446
|
Filing Dt:
|
02/23/2015
|
Publication #:
|
|
Pub Dt:
|
08/25/2016
| | | | |
Title:
|
SAMPLE PLAN CREATION FOR OPTICAL PROXIMITY CORRECTION WITH MINIMAL NUMBER OF CLIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2016
|
Application #:
|
14628947
|
Filing Dt:
|
02/23/2015
|
Publication #:
|
|
Pub Dt:
|
08/25/2016
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE INCLUDING AT LEAST ONE ELECTRICALLY CONDUCTIVE PILLAR, SEMICONDUCTOR STRUCTURE INCLUDING A CONTACT CONTACTING AN OUTER LAYER OF AN ELECTRICALLY CONDUCTIVE STRUCTURE AND METHOD FOR THE FORMATION THEREOF
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|
|
Patent #:
|
|
Issue Dt:
|
12/04/2018
|
Application #:
|
14630529
|
Filing Dt:
|
02/24/2015
|
Publication #:
|
|
Pub Dt:
|
08/25/2016
| | | | |
Title:
|
METHOD, APPARATUS AND SYSTEM FOR ADVANCED CHANNEL CMOS INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2016
|
Application #:
|
14630676
|
Filing Dt:
|
02/25/2015
|
Publication #:
|
|
Pub Dt:
|
08/25/2016
| | | | |
Title:
|
METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DIRECTED SELF-ASSEMBLY INCLUDING A SUBSTANTIALLY PERIODIC ARRAY OF TOPOGRAPHICAL FEATURES THAT INCLUDES ETCH RESISTANT TOPOGRAPHICAL FEATURES FOR TRANSFERABILITY CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2017
|
Application #:
|
14630774
|
Filing Dt:
|
02/25/2015
|
Publication #:
|
|
Pub Dt:
|
08/25/2016
| | | | |
Title:
|
MITIGATING COLLISIONS IN A PHYSICAL SPACE DURING GAMING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2018
|
Application #:
|
14632180
|
Filing Dt:
|
02/26/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
METHOD AND DEVICE FOR COOLING A HEAT GENERATING COMPONENT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2019
|
Application #:
|
14632194
|
Filing Dt:
|
02/26/2015
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
Title:
|
METHOD AND DEVICE FOR COOLING A HEAT GENERATING COMPONENT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2016
|
Application #:
|
14632313
|
Filing Dt:
|
02/26/2015
|
Publication #:
|
|
Pub Dt:
|
06/18/2015
| | | | |
Title:
|
INTEGRATION OF DENSE AND VARIABLE PITCH FIN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
14633069
|
Filing Dt:
|
02/26/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
TRANSFERRING HEAT THROUGH AN OPTICAL LAYER OF INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14633246
|
Filing Dt:
|
02/27/2015
|
Publication #:
|
|
Pub Dt:
|
09/01/2016
| | | | |
Title:
|
METHODS FOR FABRICATING SEMICONDUCTOR STRUCTURE WITH CONDENSED SILICON GERMANIUM LAYER
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14633341
|
Filing Dt:
|
02/27/2015
|
Publication #:
|
|
Pub Dt:
|
09/01/2016
| | | | |
Title:
|
SELF ALIGNED RAISED FIN TIP END STI TO IMPROVE THE FIN END EPI QUALITY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2016
|
Application #:
|
14633351
|
Filing Dt:
|
02/27/2015
|
Publication #:
|
|
Pub Dt:
|
09/01/2016
| | | | |
Title:
|
INTEGRATED CIRCUITS WITH FETS HAVING NANOWIRES AND METHODS OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2017
|
Application #:
|
14633477
|
Filing Dt:
|
02/27/2015
|
Publication #:
|
|
Pub Dt:
|
09/03/2015
| | | | |
Title:
|
METHOD AND APPARATUS FOR PHYSICAL-AWARE HOLD VIOLATION FIXING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2017
|
Application #:
|
14633544
|
Filing Dt:
|
02/27/2015
|
Publication #:
|
|
Pub Dt:
|
09/01/2016
| | | | |
Title:
|
METHODS OF PERFORMING FIN CUT ETCH PROCESSES FOR FINFET SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2016
|
Application #:
|
14633914
|
Filing Dt:
|
02/27/2015
|
Publication #:
|
|
Pub Dt:
|
09/01/2016
| | | | |
Title:
|
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SELF-ALIGNED VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2016
|
Application #:
|
14633998
|
Filing Dt:
|
02/27/2015
|
Title:
|
LOW LINE RESISTIVITY AND REPEATABLE METAL RECESS USING CVD COBALT REFLOW
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2017
|
Application #:
|
14634483
|
Filing Dt:
|
02/27/2015
|
Publication #:
|
|
Pub Dt:
|
09/01/2016
| | | | |
Title:
|
CO-FABRICATION OF NON-PLANAR SEMICONDUCTOR DEVICES HAVING DIFFERENT THRESHOLD VOLTAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2018
|
Application #:
|
14634535
|
Filing Dt:
|
02/27/2015
|
Publication #:
|
|
Pub Dt:
|
09/03/2015
| | | | |
Title:
|
THIN NIB OR COB CAPPING LAYER FOR NON-NOBLE METALLIC BONDING LANDING PADS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14634978
|
Filing Dt:
|
03/02/2015
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
COIL INDUCTOR
|
|