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11/20/2018
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11/24/2016
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11/24/2016
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12/03/2015
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09/10/2015
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08/28/2018
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12/01/2016
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10/17/2017
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12/01/2016
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06/07/2016
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05/27/2015
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07/19/2016
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05/27/2015
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06/28/2016
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05/28/2015
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09/17/2015
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12/19/2017
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05/28/2015
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09/17/2015
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08/02/2016
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05/29/2015
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09/17/2015
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08/30/2016
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05/29/2015
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09/17/2015
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05/17/2016
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05/29/2015
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07/12/2016
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05/29/2015
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10/08/2015
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04/19/2016
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05/29/2015
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10/15/2015
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07/12/2016
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05/29/2015
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09/17/2015
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10/03/2017
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06/01/2015
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12/01/2016
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03/21/2017
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06/01/2015
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12/01/2016
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SUB-NANOSECOND DISTRIBUTED CLOCK SYNCHRONIZATION USING ALIGNMENT MARKER IN ETHERNET IEEE 1588 PROTOCOL
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09/06/2016
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06/01/2015
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01/03/2017
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06/01/2015
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12/01/2016
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03/27/2018
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06/02/2015
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12/08/2016
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02/21/2017
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06/03/2015
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12/08/2016
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01/09/2018
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06/03/2015
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12/08/2016
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01/24/2017
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06/03/2015
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07/28/2016
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09/13/2016
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06/03/2015
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09/17/2015
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09/05/2017
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06/03/2015
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12/08/2016
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09/19/2017
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06/04/2015
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12/08/2016
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11/15/2016
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06/04/2015
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12/08/2016
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11/01/2016
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06/04/2015
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09/24/2015
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08/28/2018
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06/04/2015
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09/24/2015
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07/12/2016
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06/04/2015
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01/10/2017
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06/05/2015
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12/08/2016
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07/18/2017
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06/05/2015
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09/24/2015
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05/03/2016
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06/05/2015
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12/17/2015
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10/03/2017
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06/05/2015
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12/08/2016
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01/28/2020
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06/05/2015
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12/08/2016
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08/09/2016
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06/05/2015
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06/14/2016
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06/06/2015
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09/24/2015
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03/07/2017
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06/08/2015
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10/22/2015
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CMOS PROTECTION DURING GERMANIUM PHOTODETECTOR PROCESSING
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07/18/2017
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06/08/2015
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09/24/2015
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07/25/2017
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06/08/2015
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12/08/2016
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11/07/2017
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06/08/2015
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12/08/2016
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05/22/2018
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06/09/2015
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09/24/2015
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03/01/2016
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06/09/2015
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10/15/2015
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11/22/2016
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06/09/2015
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12/15/2016
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03/21/2017
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06/09/2015
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12/15/2016
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02/14/2017
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06/09/2015
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12/15/2016
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01/19/2016
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06/09/2015
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10/29/2015
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BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
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12/26/2017
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06/10/2015
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12/15/2016
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04/04/2017
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06/10/2015
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12/15/2016
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02/09/2016
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06/11/2015
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10/01/2015
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07/26/2016
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06/11/2015
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TSV REDUNDANCY SCHEME AND ARCHITECTURE USING DECODER/ENCODER
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05/10/2016
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06/11/2015
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10/01/2015
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03/14/2017
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06/12/2015
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12/15/2016
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06/13/2017
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06/12/2015
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12/15/2016
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06/07/2016
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06/12/2015
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10/01/2015
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01/24/2017
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06/12/2015
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12/15/2016
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ALTERNATIVE THRESHOLD VOLTAGE SCHEME VIA DIRECT METAL GATE PATTERNING FOR HIGH PERFORMANCE CMOS FinFETs
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12/27/2016
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06/12/2015
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04/24/2018
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06/12/2015
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10/01/2015
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Patent #:
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Issue Dt:
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08/30/2016
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Application #:
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14739137
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Filing Dt:
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06/15/2015
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Publication #:
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Pub Dt:
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10/29/2015
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Title:
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LOW INTERFACIAL DEFECT FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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11/20/2018
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Application #:
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14739543
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Filing Dt:
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06/15/2015
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Publication #:
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Pub Dt:
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12/15/2016
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Title:
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SERIES RESISTANCE REDUCTION IN VERTICALLY STACKED SILICON NANOWIRE TRANSISTORS
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Patent #:
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Issue Dt:
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05/16/2017
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Application #:
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14739662
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Filing Dt:
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06/15/2015
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Publication #:
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Pub Dt:
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12/15/2016
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Title:
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FREESTANDING SPACER HAVING SUB-LITHOGRAPHIC LATERAL DIMENSION AND METHOD OF FORMING SAME
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Patent #:
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Issue Dt:
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05/03/2016
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Application #:
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14739703
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Filing Dt:
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06/15/2015
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Publication #:
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Pub Dt:
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10/08/2015
| | | | |
Title:
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MICROELECTRONIC STRUCTURE INCLUDING AIR GAP
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Patent #:
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Issue Dt:
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08/22/2017
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Application #:
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14740035
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Filing Dt:
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06/15/2015
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Publication #:
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Pub Dt:
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12/15/2016
| | | | |
Title:
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SACRIFICIAL AMORPHOUS SILICON HARD MASK FOR BEOL
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Patent #:
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Issue Dt:
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08/08/2017
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Application #:
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14740872
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Filing Dt:
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06/16/2015
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Publication #:
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Pub Dt:
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12/22/2016
| | | | |
Title:
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FIN SHAPE CONTACTS AND METHODS FOR FORMING FIN SHAPE CONTACTS
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Patent #:
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Issue Dt:
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02/07/2017
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Application #:
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14740987
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Filing Dt:
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06/16/2015
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Publication #:
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Pub Dt:
|
12/22/2016
| | | | |
Title:
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DUAL LINER SILICIDE
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Patent #:
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Issue Dt:
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06/14/2016
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Application #:
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14741528
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Filing Dt:
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06/17/2015
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Publication #:
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Pub Dt:
|
11/19/2015
| | | | |
Title:
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INTEGRATED CIRCUITS AND METHODS FOR OPERATING INTEGRATED CIRCUITS WITH NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
|
11/15/2016
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Application #:
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14741802
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Filing Dt:
|
06/17/2015
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Title:
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WAFER-LEVEL CHIP-SCALE PACKAGE STRUCTURE UTILIZING CONDUCTIVE POLYMER
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Patent #:
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Issue Dt:
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05/10/2016
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Application #:
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14742471
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Filing Dt:
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06/17/2015
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Title:
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VIRTUAL RELAXED SUBSTRATE ON EDGE-RELAXED COMPOSITE SEMICONDUCTOR PILLARS
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Patent #:
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Issue Dt:
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07/05/2016
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Application #:
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14742537
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Filing Dt:
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06/17/2015
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Publication #:
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Pub Dt:
|
10/08/2015
| | | | |
Title:
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SILICON-ON-INSULATOR FINFET WITH BULK SOURCE AND DRAIN
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Patent #:
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Issue Dt:
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05/02/2017
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Application #:
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14742801
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Filing Dt:
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06/18/2015
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Publication #:
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Pub Dt:
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12/22/2016
| | | | |
Title:
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INTEGRATED CIRCUIT CHIP RELIABILITY USING RELIABILITY-OPTIMIZED FAILURE MECHANISM TARGETING
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Patent #:
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Issue Dt:
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10/16/2018
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Application #:
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14742895
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Filing Dt:
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06/18/2015
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Publication #:
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Pub Dt:
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12/22/2016
| | | | |
Title:
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TEST STRUCTURES FOR DIELECTRIC RELIABILITY EVALUATIONS
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Patent #:
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Issue Dt:
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04/10/2018
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Application #:
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14742917
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Filing Dt:
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06/18/2015
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Publication #:
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Pub Dt:
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12/22/2016
| | | | |
Title:
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CAPACITIVE MEASUREMENTS OF DIVOTS IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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09/06/2016
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Application #:
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14742935
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Filing Dt:
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06/18/2015
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Title:
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MIDDLE-OF-LINE ARCHITECTURE FOR DENSE LIBRARY LAYOUT USING M0 HAND-SHAKE
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Patent #:
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Issue Dt:
|
03/29/2016
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Application #:
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14743030
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Filing Dt:
|
06/18/2015
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Title:
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INTEGRATED MICRO-PELTIER COOLING COMPONENTS IN SILICON-ON-INSULATOR (SOI) LAYERS
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Patent #:
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Issue Dt:
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10/16/2018
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Application #:
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14743208
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Filing Dt:
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06/18/2015
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Publication #:
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Pub Dt:
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12/22/2016
| | | | |
Title:
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DETECTING A VOID BETWEEN A VIA AND A WIRING LINE
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Patent #:
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Issue Dt:
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11/29/2016
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Application #:
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14743511
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Filing Dt:
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06/18/2015
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Publication #:
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Pub Dt:
|
12/22/2016
| | | | |
Title:
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SiARC REMOVAL WITH PLASMA ETCH AND FLUORINATED WET CHEMICAL SOLUTION COMBINATION
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Patent #:
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Issue Dt:
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02/13/2018
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Application #:
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14744198
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Filing Dt:
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06/19/2015
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Publication #:
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Pub Dt:
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12/22/2016
| | | | |
Title:
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NON-DESTRUCTIVE DIELECTRIC LAYER THICKNESS AND DOPANT MEASURING METHOD
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Patent #:
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Issue Dt:
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10/03/2017
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Application #:
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14744800
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Filing Dt:
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06/19/2015
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Publication #:
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Pub Dt:
|
12/22/2016
| | | | |
Title:
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LATCHING CURRENT SENSING AMPLIFIER FOR MEMORY ARRAY
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Patent #:
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Issue Dt:
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06/20/2017
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Application #:
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14745547
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Filing Dt:
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06/22/2015
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Publication #:
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Pub Dt:
|
12/22/2016
| | | | |
Title:
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GENERATING TENSILE STRAIN IN BULK FINFET CHANNEL
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Patent #:
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Issue Dt:
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10/15/2019
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Application #:
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14745704
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Filing Dt:
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06/22/2015
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Publication #:
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Pub Dt:
|
12/22/2016
| | | | |
Title:
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DEVICE STRUCTURES FOR A SILICON-ON-INSULATOR SUBSTRATE WITH A HIGH-RESISTANCE HANDLE WAFER
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Patent #:
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Issue Dt:
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08/08/2017
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Application #:
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14745764
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Filing Dt:
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06/22/2015
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Publication #:
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Pub Dt:
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12/22/2016
| | | | |
Title:
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BIPOLAR JUNCTION TRANSISTORS WITH DOUBLE-TAPERED EMITTER FINGERS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14745800
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Filing Dt:
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06/22/2015
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Publication #:
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Pub Dt:
|
12/22/2016
| | | | |
Title:
|
CHIP PACKAGE WITH REDUCED TEMPERATURE VARIATION HAVING EMITTER FINGERS FORMATION ACCORDING TO THEIR PROXIMITY TO THE THERMAL PATHWAY STRUCTURE AND A METHOD FOR FORMING A SAME
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Patent #:
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Issue Dt:
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10/04/2016
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Application #:
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14746017
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Filing Dt:
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06/22/2015
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Publication #:
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Pub Dt:
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10/08/2015
| | | | |
Title:
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SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY
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Patent #:
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Issue Dt:
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02/21/2017
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Application #:
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14746891
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Filing Dt:
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06/23/2015
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Publication #:
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Pub Dt:
|
12/29/2016
| | | | |
Title:
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ELECTRICAL FUSE WITH HIGH OFF RESISTANCE
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Patent #:
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Issue Dt:
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11/15/2016
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Application #:
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14747525
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Filing Dt:
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06/23/2015
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Publication #:
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Pub Dt:
|
10/29/2015
| | | | |
Title:
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SELF-ALIGNED EMITTER-BASE-COLLECTOR BIPOLAR JUNCTION TRANSISTORS WITH A SINGLE CRYSTAL RAISED EXTRINSIC BASE
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Patent #:
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Issue Dt:
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08/23/2016
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Application #:
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14747604
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Filing Dt:
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06/23/2015
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Title:
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REPLACEMENT EMITTER FOR REDUCED CONTACT RESISTANCE
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Patent #:
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Issue Dt:
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08/01/2017
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Application #:
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14747668
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Filing Dt:
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06/23/2015
|
Publication #:
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Pub Dt:
|
12/29/2016
| | | | |
Title:
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BIPOLAR JUNCTION TRANSISTORS WITH A BURIED DIELECTRIC REGION IN THE ACTIVE DEVICE REGION
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Patent #:
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Issue Dt:
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12/27/2016
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Application #:
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14748355
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Filing Dt:
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06/24/2015
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Publication #:
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Pub Dt:
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12/29/2016
| | | | |
Title:
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HIGH PERFORMANCE HEAT SHIELDS WITH REDUCED CAPACITANCE
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Patent #:
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Issue Dt:
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02/28/2017
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Application #:
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14748595
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Filing Dt:
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06/24/2015
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Publication #:
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Pub Dt:
|
12/29/2016
| | | | |
Title:
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MODELING LOCALIZED TEMPERATURE CHANGES ON AN INTEGRATED CIRCUIT CHIP USING THERMAL POTENTIAL THEORY
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Patent #:
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Issue Dt:
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06/27/2017
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Application #:
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14749165
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Filing Dt:
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06/24/2015
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Publication #:
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Pub Dt:
|
06/30/2016
| | | | |
Title:
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INTEGRATED CIRCUITS INCLUDING MAGNETIC TUNNEL JUNCTIONS FOR MAGNETORESISTIVE RANDOM-ACCESS MEMORY AND METHODS FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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03/15/2016
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Application #:
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14749245
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Filing Dt:
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06/24/2015
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Publication #:
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Pub Dt:
|
10/15/2015
| | | | |
Title:
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INTEGRATED CIRCUITS HAVING FINFETS WITH IMPROVED DOPED CHANNEL REGIONS AND METHODS FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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06/14/2016
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Application #:
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14749809
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Filing Dt:
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06/25/2015
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Title:
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HETEROJUNCTION BIPOLAR TRANSISTOR WITH IMPROVED PERFORMANCE AND BREAKDOWN VOLTAGE
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Patent #:
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Issue Dt:
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06/06/2017
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Application #:
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14749817
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Filing Dt:
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06/25/2015
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Publication #:
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Pub Dt:
|
12/29/2016
| | | | |
Title:
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STRUCTURE FOR BEOL METAL LEVELS WITH MULTIPLE DIELECTRIC LAYERS FOR IMPROVED DIELECTRIC TO METAL ADHESION
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Patent #:
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Issue Dt:
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01/03/2017
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Application #:
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14749843
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Filing Dt:
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06/25/2015
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Publication #:
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Pub Dt:
|
12/29/2016
| | | | |
Title:
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INTEGRATED CIRCUIT (IC) CHIPS WITH THROUGH SILICON VIAS (TSV) AND METHOD OF FORMING THE IC
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Patent #:
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Issue Dt:
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03/28/2017
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Application #:
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14749907
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Filing Dt:
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06/25/2015
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Publication #:
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Pub Dt:
|
12/29/2016
| | | | |
Title:
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MULTILEVEL WAVEGUIDE STRUCTURE
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Patent #:
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Issue Dt:
|
06/27/2017
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Application #:
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14749909
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Filing Dt:
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06/25/2015
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Publication #:
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Pub Dt:
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12/29/2016
| | | | |
Title:
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GENERATIVE LEARNING FOR REALISTIC AND GROUND RULE CLEAN HOT SPOT SYNTHESIS
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Patent #:
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Issue Dt:
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08/29/2017
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Application #:
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14750236
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Filing Dt:
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06/25/2015
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Publication #:
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Pub Dt:
|
12/29/2016
| | | | |
Title:
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TUNABLE CAPACITOR FOR FDSOI APPLICATIONS
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Patent #:
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Issue Dt:
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01/31/2017
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Application #:
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14750741
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Filing Dt:
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06/25/2015
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Publication #:
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Pub Dt:
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12/29/2016
| | | | |
Title:
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HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE
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Patent #:
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Issue Dt:
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12/13/2016
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Application #:
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14751222
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Filing Dt:
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06/26/2015
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Publication #:
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Pub Dt:
|
12/29/2016
| | | | |
Title:
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DYNAMIC AND ADAPTIVE TIMING SENSITIVITY DURING STATIC TIMING ANALYSIS USING LOOK-UP TABLE
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