|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
13765830
|
Filing Dt:
|
02/13/2013
|
Publication #:
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|
Pub Dt:
|
06/13/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL)
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
13766028
|
Filing Dt:
|
02/13/2013
|
Publication #:
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|
Pub Dt:
|
08/14/2014
| | | | |
Title:
|
INTERCONNECT WIRING SWITCHES AND INTEGRATED CIRCUITS INCLUDING THE SAME
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|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13766276
|
Filing Dt:
|
02/13/2013
|
Publication #:
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|
Pub Dt:
|
08/14/2014
| | | | |
Title:
|
SELECTIVE VOLTAGE BINNING WITHIN A THREE-DIMENSIONAL INTEGRATED CHIP STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
13766722
|
Filing Dt:
|
02/13/2013
|
Title:
|
COST-FUNCTION BASED ROUTING TECHNIQUES FOR REDUCING CROSSTALK IN ELECTRONIC PACKAGE DESIGNS
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|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
13766846
|
Filing Dt:
|
02/14/2013
|
Publication #:
|
|
Pub Dt:
|
08/14/2014
| | | | |
Title:
|
TEMPERATURE STABILIZATION IN SEMICONDUCTORS USING THE MAGNETOCALORIC EFFECT
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|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13766952
|
Filing Dt:
|
02/14/2013
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
ISOLATION STRUCTURES FOR GLOBAL SHUTTER IMAGER PIXEL, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13767024
|
Filing Dt:
|
02/14/2013
|
Publication #:
|
|
Pub Dt:
|
08/14/2014
| | | | |
Title:
|
BIOLOGICAL AND CHEMICAL SENSORS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13767845
|
Filing Dt:
|
02/14/2013
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A COPPER PLUG
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|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13768112
|
Filing Dt:
|
02/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/21/2014
| | | | |
Title:
|
INTEGRATED CIRCUIT PAD MODELING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13768248
|
Filing Dt:
|
02/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/21/2014
| | | | |
Title:
|
MIM CAPACITOR IN FINFET STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13768759
|
Filing Dt:
|
02/15/2013
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
Title:
|
CHIP ASSEMBLY WITH A CORELESS SUBSTRATE EMPLOYING A PATTERNED ADHESIVE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2013
|
Application #:
|
13769402
|
Filing Dt:
|
02/18/2013
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
Title:
|
LINER-FREE TUNGSTEN CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13769500
|
Filing Dt:
|
02/18/2013
|
Publication #:
|
|
Pub Dt:
|
08/21/2014
| | | | |
Title:
|
COLLECTOR-UP BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2015
|
Application #:
|
13769976
|
Filing Dt:
|
02/19/2013
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2016
|
Application #:
|
13770018
|
Filing Dt:
|
02/19/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
DEPLOYMENT PATTERN REALIZATION WITH MODELS OF COMPUTING ENVIRONMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13770229
|
Filing Dt:
|
02/19/2013
|
Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
Title:
|
Parsing Data Representative of a Hardware Design into Commands of a Hardware Design Environment
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13770534
|
Filing Dt:
|
02/19/2013
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
Title:
|
METHOD AND STRUCTURE FOR FORMING HIGH-K/METAL GATE EXTREMELY THIN SEMICONDUCTOR ON INSULATOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2016
|
Application #:
|
13770545
|
Filing Dt:
|
02/19/2013
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
Title:
|
MOSFETs WITH REDUCED CONTACT RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13770552
|
Filing Dt:
|
02/19/2013
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
REPLACEMENT GATE HAVING WORK FUNCTION AT VALENCE BAND EDGE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2016
|
Application #:
|
13770711
|
Filing Dt:
|
02/19/2013
|
Publication #:
|
|
Pub Dt:
|
08/21/2014
| | | | |
Title:
|
EFFICIENT VALIDATION OF COHERENCY BETWEEN PROCESSOR CORES AND ACCELERATORS IN COMPUTER SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
13771240
|
Filing Dt:
|
02/20/2013
|
Title:
|
FINFETS AND FIN ISOLATION STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2015
|
Application #:
|
13771255
|
Filing Dt:
|
02/20/2013
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
METHOD AND STRUCTURE FOR FORMING A LOCALIZED SOI FINFET
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13771668
|
Filing Dt:
|
02/20/2013
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
ON CHIP INDUCTOR WITH FREQUENCY DEPENDENT INDUCTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13771864
|
Filing Dt:
|
02/20/2013
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
STRUCTURE AND METHOD FOR INCREASING STRAIN IN A DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13771929
|
Filing Dt:
|
02/20/2013
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
FLUIDIC STRUCTURE WITH NANOPORE ARRAY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13771937
|
Filing Dt:
|
02/20/2013
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13772401
|
Filing Dt:
|
02/21/2013
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
13772402
|
Filing Dt:
|
02/21/2013
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
13772511
|
Filing Dt:
|
02/21/2013
|
Publication #:
|
|
Pub Dt:
|
08/29/2013
| | | | |
Title:
|
Ta-TaN SELECTIVE REMOVAL PROCESS FOR INTEGRATED DEVICE FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2014
|
Application #:
|
13772881
|
Filing Dt:
|
02/21/2013
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
JUNCTION FIELD EFFECT TRANSISTOR WITH AN EPITAXIALLY GROWN GATE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13772954
|
Filing Dt:
|
02/21/2013
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
Title:
|
TRENCH SILICIDE CONTACT WITH LOW INTERFACE RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13772993
|
Filing Dt:
|
02/21/2013
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13773012
|
Filing Dt:
|
02/21/2013
|
Publication #:
|
|
Pub Dt:
|
12/05/2013
| | | | |
Title:
|
BORDERLESS CONTACTS FOR METAL GATES THROUGH SELECTIVE CAP DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2016
|
Application #:
|
13773014
|
Filing Dt:
|
02/21/2013
|
Publication #:
|
|
Pub Dt:
|
08/29/2013
| | | | |
Title:
|
CMOS STRUCTURE ON REPLACEMENT SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13773397
|
Filing Dt:
|
02/21/2013
|
Publication #:
|
|
Pub Dt:
|
08/21/2014
| | | | |
Title:
|
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING METAL GATE ELECTRODES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13773854
|
Filing Dt:
|
02/22/2013
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
Title:
|
SETTING SWITCH SIZE AND TRANSITION PATTERN IN A RESONANT CLOCK DISTRIBUTION SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13773881
|
Filing Dt:
|
02/22/2013
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
Title:
|
METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) GATE TERMINATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
13774069
|
Filing Dt:
|
02/22/2013
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
STRUCTURE, METHOD AND SYSTEM FOR COMPLEMENTARY STRAIN FILL FOR INTEGRATED CIRCUIT CHIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13774205
|
Filing Dt:
|
02/22/2013
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
Title:
|
DESIGN STRUCTURE, STRUCTURE AND METHOD OF LATCH-UP IMMUNITY FOR HIGH AND LOW VOLTAGE INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13774373
|
Filing Dt:
|
02/22/2013
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
Title:
|
ELECTRICAL FUSES AND METHODS OF MAKING ELECTRICAL FUSES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2015
|
Application #:
|
13774573
|
Filing Dt:
|
02/22/2013
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
Title:
|
BODY CONTACTED HYBRID SURFACE SEMICONDUCTOR-ON-INSULATOR DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13774625
|
Filing Dt:
|
02/22/2013
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
PHOTORESIST COMPOSITION FOR NEGATIVE DEVELOPMENT AND PATTERN FORMING METHOD USING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2015
|
Application #:
|
13775281
|
Filing Dt:
|
02/25/2013
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
Title:
|
PHASE CHANGE MEMORY MANAGEMENT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13775338
|
Filing Dt:
|
02/25/2013
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
SAW FILTER HAVING PLANAR BARRIER LAYER AND METHOD OF MAKING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13775369
|
Filing Dt:
|
02/25/2013
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13775430
|
Filing Dt:
|
02/25/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
SCALING OF METAL GATE WITH ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13775436
|
Filing Dt:
|
02/25/2013
|
Publication #:
|
|
Pub Dt:
|
05/22/2014
| | | | |
Title:
|
METAL GATE STRUCTURES FOR CMOS TRANSISTOR DEVICES HAVING REDUCED PARASITIC CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13775570
|
Filing Dt:
|
02/25/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
13775593
|
Filing Dt:
|
02/25/2013
|
Title:
|
Managing Aging of Silicon in an Integrated Circuit Device
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2015
|
Application #:
|
13775917
|
Filing Dt:
|
02/25/2013
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
Title:
|
U-SHAPED SEMICONDUCTOR STRUCTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13775946
|
Filing Dt:
|
02/25/2013
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
Title:
|
CONTACT RESISTANCE REDUCTION IN FINFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13775958
|
Filing Dt:
|
02/25/2013
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
Title:
|
C-RICH CARBON BORON NITRIDE DIELECTRIC FILMS FOR USE IN ELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13775968
|
Filing Dt:
|
02/25/2013
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
Title:
|
III-V COMPOUND SEMICONDUCTOR MATERIAL PASSIVATION WITH CRYSTALLINE INTERLAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2015
|
Application #:
|
13775988
|
Filing Dt:
|
02/25/2013
|
Publication #:
|
|
Pub Dt:
|
11/21/2013
| | | | |
Title:
|
MASK FREE PROTECTION OF WORK FUNCTION MATERIAL PORTIONS IN WIDE REPLACEMENT GATE ELECTRODES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13776016
|
Filing Dt:
|
02/25/2013
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
Title:
|
ENHANCED DIFFUSION BARRIER FOR INTERCONNECT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13776324
|
Filing Dt:
|
02/25/2013
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
Title:
|
SILICON NITRIDE GATE ENCAPSULATION BY IMPLANTATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13776781
|
Filing Dt:
|
02/26/2013
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
CONTROLLING DENSITY OF PARTICLES WITHIN UNDERFILL SURROUNDING SOLDER BUMP CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
13776892
|
Filing Dt:
|
02/26/2013
|
Title:
|
METHODS AND SYSTEMS TO REDUCE A NUMBER OF SIMULATIONS IN A TIMING ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2016
|
Application #:
|
13776902
|
Filing Dt:
|
02/26/2013
|
Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
Title:
|
CHARACTERIZATION OF INTERFACE RESISTANCE IN A MULTI-LAYER CONDUCTIVE STRUCTURE
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Patent #:
|
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Issue Dt:
|
06/16/2015
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Application #:
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13776911
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Filing Dt:
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02/26/2013
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Publication #:
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Pub Dt:
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01/23/2014
| | | | |
Title:
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SOURCE/DRAIN-TO-SOURCE/DRAIN RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME
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Patent #:
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Issue Dt:
|
07/28/2015
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Application #:
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13777353
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Filing Dt:
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02/26/2013
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Publication #:
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Pub Dt:
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07/04/2013
| | | | |
Title:
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EPITAXIAL EXTENSION CMOS TRANSISTOR
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Patent #:
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Issue Dt:
|
07/21/2015
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Application #:
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13777364
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Filing Dt:
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02/26/2013
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Publication #:
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Pub Dt:
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08/28/2014
| | | | |
Title:
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SEMICONDUCTOR FABRICATION METHOD USING STOP LAYER
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Patent #:
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Issue Dt:
|
02/11/2014
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Application #:
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13777402
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Filing Dt:
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02/26/2013
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Publication #:
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Pub Dt:
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07/04/2013
| | | | |
Title:
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METHOD FOR GROWING CONFORMAL EPI LAYERS AND STRUCTURE THEREOF
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|
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Patent #:
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Issue Dt:
|
12/16/2014
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Application #:
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13777493
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Filing Dt:
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02/26/2013
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Publication #:
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Pub Dt:
|
07/04/2013
| | | | |
Title:
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ELECTRICAL FUSE STRUCTURE AND METHOD OF FABRICATING SAME
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|
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Patent #:
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Issue Dt:
|
09/23/2014
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Application #:
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13777506
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Filing Dt:
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02/26/2013
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Publication #:
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Pub Dt:
|
04/03/2014
| | | | |
Title:
|
POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13777554
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Filing Dt:
|
02/26/2013
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Publication #:
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Pub Dt:
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08/22/2013
| | | | |
Title:
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INTERCONNECT STRUCTURES AND METHODS OF MANUFACTURING OF INTERCONNECT STRUCTURES
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|
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
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13778263
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Filing Dt:
|
02/27/2013
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Publication #:
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Pub Dt:
|
07/04/2013
| | | | |
Title:
|
STRUCTURE AND METHOD FOR REDUCING VERTICAL CRACK PROPAGATION
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|
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Patent #:
|
|
Issue Dt:
|
11/18/2014
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Application #:
|
13778314
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Filing Dt:
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02/27/2013
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Publication #:
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Pub Dt:
|
08/28/2014
| | | | |
Title:
|
STRESS MEMORIZATION IN RMG FINFETS
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|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
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Application #:
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13778321
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Filing Dt:
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02/27/2013
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Publication #:
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|
Pub Dt:
|
08/28/2014
| | | | |
Title:
|
INTERDIGITATED CAPACITORS WITH A ZERO QUADRATIC VOLTAGE COEFFICIENT OF CAPACITANCE OR ZERO LINEAR TEMPERATURE COEFFICIENT OF CAPACITANCE
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|
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Patent #:
|
|
Issue Dt:
|
04/05/2016
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Application #:
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13778419
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Filing Dt:
|
02/27/2013
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Publication #:
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Pub Dt:
|
07/04/2013
| | | | |
Title:
|
STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13778479
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Filing Dt:
|
02/27/2013
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Publication #:
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|
Pub Dt:
|
08/28/2014
| | | | |
Title:
|
BI-DIRECTIONAL SILICON CONTROLLED RECTIFIER STRUCTURE
|
|
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Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13778668
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Filing Dt:
|
02/27/2013
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Title:
|
DELAY DEFECT TESTING OF POWER DROP EFFECTS IN INTEGRATED CIRCUITS
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13778826
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Filing Dt:
|
02/27/2013
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Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
Title:
|
METHODS FOR FORMING FIELD EFFECT TRANSISTOR DEVICES WITH PROTECTIVE SPACERS
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|
|
Patent #:
|
|
Issue Dt:
|
01/20/2015
|
Application #:
|
13779036
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Filing Dt:
|
02/27/2013
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Publication #:
|
|
Pub Dt:
|
08/28/2014
| | | | |
Title:
|
INFORMATION ENCODING USING WIREBONDS
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13779111
|
Filing Dt:
|
02/27/2013
|
Publication #:
|
|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
POWER MANAGEMENT SRAM GLOBAL BIT LINE PRECHARGE CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13779719
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Filing Dt:
|
02/27/2013
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
Title:
|
CHANGING THE LOCATION OF A BUFFER BAY IN A NETLIST
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
13780003
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Filing Dt:
|
02/28/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
REPLACEMENT METAL GATE STRUCTURES FOR EFFECTIVE WORK FUNCTION CONTROL
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13780017
|
Filing Dt:
|
02/28/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
DAMASCENE METAL GATE AND SHIELD STRUCTURE, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
13780205
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Filing Dt:
|
02/28/2013
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
DRAM ERROR DETECTION, EVALUATION, AND CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13780413
|
Filing Dt:
|
02/28/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
SYSTEMS AND METHODS FOR CORRELATED PARAMETERS IN STATISTICAL STATIC TIMING ANALYSIS
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|
|
Patent #:
|
|
Issue Dt:
|
04/28/2015
|
Application #:
|
13780449
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Filing Dt:
|
02/28/2013
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
DEPOSITION CHAMBER CLEANING METHOD INCLUDING STRESSED CLEANING LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13780454
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Filing Dt:
|
02/28/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
SINGLE-JUNCTION PHOTOVOLTAIC CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2014
|
Application #:
|
13780471
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Filing Dt:
|
02/28/2013
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
Title:
|
INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR PROGRAMMABLE ELECTRICAL FUSES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
13780762
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Filing Dt:
|
02/28/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2015
|
Application #:
|
13780877
|
Filing Dt:
|
02/28/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13780886
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Filing Dt:
|
02/28/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
ALIGNMENT MARKS FOR MULTI-EXPOSURE LITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13780887
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Filing Dt:
|
02/28/2013
|
Publication #:
|
|
Pub Dt:
|
01/02/2014
| | | | |
Title:
|
INTEGRATION OF A TITANIA LAYER IN AN ANTI-REFLECTIVE COATING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2015
|
Application #:
|
13780912
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Filing Dt:
|
02/28/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
SELF-ALIGNED CONTACT FOR REPLACEMENT GATE DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13780957
|
Filing Dt:
|
02/28/2013
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
ETCH STOP LAYER FORMATION IN METAL GATE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2014
|
Application #:
|
13781904
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
09/12/2013
| | | | |
Title:
|
METHOD AND SYSTEM FOR REPARTITIONING A HIERARCHICAL CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13782094
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
09/04/2014
| | | | |
Title:
|
BIPOLAR DEVICE HAVING A MONOCRYSTALLINE SEMICONDUCTOR INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13782139
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
09/04/2014
| | | | |
Title:
|
DYNAMIC POWER PREDICTION WITH PIN ATTRIBUTE DATA MODEL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2015
|
Application #:
|
13782364
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
SELECTIVELY LOWERING RESISTANCE OF A CONSTANTLY USED PORTION OF MOTOR WINDINGS IN DISK DRIVE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13782411
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
DYNAMIC RECONFIGURATION-SWITCHING OF WINDINGS IN A MOTOR USED AS A GENERATOR IN A TURBINE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13782452
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Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
Title:
|
SELECTIVELY LOWERING RESISTANCE OF A CONSTANTLY USED PORTION OF MOTOR WINDINGS IN AN ELECTRIC MOTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2015
|
Application #:
|
13782467
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
DYNAMIC RECONFIGURATION-SWITCHING OF WINDINGS IN AN ELECTRIC MOTOR USED AS A GENERATOR IN AN ELECTRIC VEHICLE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2015
|
Application #:
|
13782537
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
09/04/2014
| | | | |
Title:
|
SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STRUCTURES AND DESIGN STRUCTURES THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13782561
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
09/04/2014
| | | | |
Title:
|
THERMALLY-OPTIMIZED METAL FILL FOR STACKED CHIP SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13782678
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13783388
|
Filing Dt:
|
03/03/2013
|
Title:
|
SINGLE-MASK SPACER TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES
|
|