|
|
Patent #:
|
|
Issue Dt:
|
06/30/2015
|
Application #:
|
13782364
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
SELECTIVELY LOWERING RESISTANCE OF A CONSTANTLY USED PORTION OF MOTOR WINDINGS IN DISK DRIVE
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13782411
|
Filing Dt:
|
03/01/2013
|
Publication #:
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|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
DYNAMIC RECONFIGURATION-SWITCHING OF WINDINGS IN A MOTOR USED AS A GENERATOR IN A TURBINE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13782452
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
Title:
|
SELECTIVELY LOWERING RESISTANCE OF A CONSTANTLY USED PORTION OF MOTOR WINDINGS IN AN ELECTRIC MOTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2015
|
Application #:
|
13782467
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
DYNAMIC RECONFIGURATION-SWITCHING OF WINDINGS IN AN ELECTRIC MOTOR USED AS A GENERATOR IN AN ELECTRIC VEHICLE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2015
|
Application #:
|
13782537
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
09/04/2014
| | | | |
Title:
|
SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STRUCTURES AND DESIGN STRUCTURES THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13782561
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
09/04/2014
| | | | |
Title:
|
THERMALLY-OPTIMIZED METAL FILL FOR STACKED CHIP SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13782678
|
Filing Dt:
|
03/01/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13783388
|
Filing Dt:
|
03/03/2013
|
Title:
|
SINGLE-MASK SPACER TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13783438
|
Filing Dt:
|
03/04/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13783526
|
Filing Dt:
|
03/04/2013
|
Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13783705
|
Filing Dt:
|
03/04/2013
|
Publication #:
|
|
Pub Dt:
|
09/04/2014
| | | | |
Title:
|
PLANAR QUBITS HAVING INCREASED COHERENCE TIMES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13783729
|
Filing Dt:
|
03/04/2013
|
Publication #:
|
|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
HYBRID LATCH AND FUSE SCHEME FOR MEMORY REPAIR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13783943
|
Filing Dt:
|
03/04/2013
|
Publication #:
|
|
Pub Dt:
|
09/04/2014
| | | | |
Title:
|
CONTROLLED METAL EXTRUSION OPENING IN SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING
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|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
13785109
|
Filing Dt:
|
03/05/2013
|
Title:
|
TEST COVERAGE OF INTEGRATED CIRCUITS WITH MASKING PATTERN SELECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13785438
|
Filing Dt:
|
03/05/2013
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13785602
|
Filing Dt:
|
03/05/2013
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
MEMORY STATE SENSING BASED ON CELL CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13785816
|
Filing Dt:
|
03/05/2013
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
FRONT SIDE WAFER ID PROCESSING
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13786629
|
Filing Dt:
|
03/06/2013
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
DIAGNOSTIC TESTING FOR A DOUBLE-PUMPED MEMORY ARRAY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13788125
|
Filing Dt:
|
03/07/2013
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
BURST NOISE IN LINE TEST
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
13788406
|
Filing Dt:
|
03/07/2013
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
High Density Memory Cells Using Lateral Epitaxy
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
13788450
|
Filing Dt:
|
03/07/2013
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
APPARATUS AND METHOD FOR CONTROLLED ACCESS TO PRESSURIZED FLUID LINES AND TO EXHAUSTED LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13788617
|
Filing Dt:
|
03/07/2013
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
SERIALIZED ERROR INJECTION INTO A FUNCTION UNDER TEST
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2015
|
Application #:
|
13788689
|
Filing Dt:
|
03/07/2013
|
Publication #:
|
|
Pub Dt:
|
11/28/2013
| | | | |
Title:
|
STRUCTURE AND METHOD TO MODULATE THRESHOLD VOLTAGE FOR HIGH-K METAL GATE FIELD EFFECT TRANSISTORS (FETs)
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
13788744
|
Filing Dt:
|
03/07/2013
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
Title:
|
BITLINE DELETION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13788776
|
Filing Dt:
|
03/07/2013
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
WAFER FILL PATTERNS AND USES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
13788980
|
Filing Dt:
|
03/07/2013
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
HIGH CAPACITANCE TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
13789018
|
Filing Dt:
|
03/07/2013
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
REPLACEMENT METAL GATE STRUCTURES PROVIDING INDEPENDENT CONTROL ON WORK FUNCTION AND GATE LEAKAGE CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13789792
|
Filing Dt:
|
03/08/2013
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
Self-aligned Contacts For Replacement Metal Gate Transistors
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13789891
|
Filing Dt:
|
03/08/2013
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
3D CHIP STACK HAVING ENCAPSULATED CHIP-IN-CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
13790399
|
Filing Dt:
|
03/08/2013
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
ELECTRONIC FUSE WITH RESISTIVE HEATER
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13790734
|
Filing Dt:
|
03/08/2013
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
TRENCH ISOLATION AND METHOD OF FABRICATING TRENCH ISOLATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13790910
|
Filing Dt:
|
03/08/2013
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICES FABRICATED BY DOPED MATERIAL LAYER AS DOPANT SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2015
|
Application #:
|
13791502
|
Filing Dt:
|
03/08/2013
|
Publication #:
|
|
Pub Dt:
|
08/15/2013
| | | | |
Title:
|
AIRGAP-CONTAINING INTERCONNECT STRUCTURE WITH PATTERNABLE LOW-K MATERIAL AND METHOD OF FABRICATING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13791520
|
Filing Dt:
|
03/08/2013
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
SELF-ALIGNED CONTACTS FOR HIGH K/METAL GATE PROCESS FLOW
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13791545
|
Filing Dt:
|
03/08/2013
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13791877
|
Filing Dt:
|
03/08/2013
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
Communicating Control Information for a Data Communications Link Via a Line Being Calibrated
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13792933
|
Filing Dt:
|
03/11/2013
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM
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|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13793185
|
Filing Dt:
|
03/11/2013
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13793363
|
Filing Dt:
|
03/11/2013
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
HETEROGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13793662
|
Filing Dt:
|
03/11/2013
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
FINFET CIRCUITS WITH VARIOUS FIN HEIGHTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2015
|
Application #:
|
13793804
|
Filing Dt:
|
03/11/2013
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13795030
|
Filing Dt:
|
03/12/2013
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
FLUID DISTRIBUTION METHOD FACILITATING COOLING OF ELECTRONICS RACK(S) AND SIMULATING HEATED AIRFLOW EXHAUST OF ELECTRONICS RACK(S)
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|
|
Patent #:
|
|
Issue Dt:
|
02/17/2015
|
Application #:
|
13795513
|
Filing Dt:
|
03/12/2013
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
MASK DESIGN METHOD, PROGRAM, AND MASK DESIGN SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13796154
|
Filing Dt:
|
03/12/2013
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13796259
|
Filing Dt:
|
03/12/2013
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
DISTRIBUTING SPARE LATCH CIRCUITS IN INTEGRATED CIRCUIT DESIGNS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13796278
|
Filing Dt:
|
03/12/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
NON-REPLACEMENT GATE NANOMESH FIELD EFFECT TRANSISTOR WITH PAD REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13796418
|
Filing Dt:
|
03/12/2013
|
Title:
|
NON-REPLACEMENT GATE NANOMESH FIELD EFFECT TRANSISTOR WITH EPITIXIALLY GROWN SOURCE AND DRAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13797001
|
Filing Dt:
|
03/12/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF INCREASING SPACE FOR CONTACT ELEMENTS BY USING A SACRIFICIAL LINER AND THE RESULTING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
13798446
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
HIGH DENSITY MULTI-ELECTRODE ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
13798449
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
08/15/2013
| | | | |
Title:
|
Method and System for Improving Alignment Precision of Parts in MEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13798573
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
HIGH THRESHOLD VOLTAGE NMOS TRANSISTORS FOR LOW POWER IC TECHNOLOGY
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|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
|
Application #:
|
13798643
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13799148
|
Filing Dt:
|
03/13/2013
|
Title:
|
THERMALLY ASSISTED MRAM WITH MULTILAYER STRAP AND TOP CONTACT FOR LOW THERMAL CONDUCTIVITY
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|
|
Patent #:
|
|
Issue Dt:
|
12/22/2015
|
Application #:
|
13800091
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FABRICATING BIPOLAR JUNCTION TRANSISTORS WITH REDUCED EPITAXIAL BASE FACETS EFFECT FOR LOW PARASITIC COLLECTOR-BASE CAPACITANCE
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13800201
|
Filing Dt:
|
03/13/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METAL PLATING SYSTEM INCLUDING GAS BUBBLE REMOVAL UNIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
13803281
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
HIGHLY SCALABLE TRENCH CAPACITOR
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13803364
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
STRUCTURE FOR NANO-SCALE METALLIZATION AND METHOD FOR FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13803470
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
PROGRAMMABLE FETS USING VT-SHIFT EFFECT AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
13803856
|
Filing Dt:
|
03/14/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
BACK-GATED SUBSTRATE AND SEMICONDUCTOR DEVICE, AND RELATED METHOD OF FABRICATION
|
|
|
Patent #:
|
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Issue Dt:
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07/14/2015
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Application #:
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13826316
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Filing Dt:
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03/14/2013
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Publication #:
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Pub Dt:
|
09/18/2014
| | | | |
Title:
|
DYNAMIC PEAK TRACKING IN X-RAY PHOTOELECTRON SPECTROSCOPY MEASUREMENT TOOL
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Patent #:
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Issue Dt:
|
12/09/2014
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Application #:
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13826628
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Filing Dt:
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03/14/2013
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Publication #:
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Pub Dt:
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09/18/2014
| | | | |
Title:
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ELECTRICAL LEAKAGE REDUCTION IN STACKED INTEGRATED CIRCUITS HAVING THROUGH-SILICON-VIA (TSV) STRUCTURES
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Patent #:
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Issue Dt:
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02/02/2016
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Application #:
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13826631
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Filing Dt:
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03/14/2013
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Publication #:
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Pub Dt:
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08/08/2013
| | | | |
Title:
|
ALIGNMENT NET INSERTION FOR STRAIGHTENING THE DATAPATH IN A FORCE-DIRECTED PLACER
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Patent #:
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Issue Dt:
|
10/01/2013
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Application #:
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13826830
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Filing Dt:
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03/14/2013
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Publication #:
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Pub Dt:
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08/08/2013
| | | | |
Title:
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THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-COPPER BONDING
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Patent #:
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|
Issue Dt:
|
02/25/2014
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Application #:
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13826874
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Filing Dt:
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03/14/2013
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Publication #:
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Pub Dt:
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08/08/2013
| | | | |
Title:
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METHOD FOR FORMING SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP
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Patent #:
|
|
Issue Dt:
|
12/01/2015
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Application #:
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13826936
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Filing Dt:
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03/14/2013
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Publication #:
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Pub Dt:
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08/01/2013
| | | | |
Title:
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STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
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13827401
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Filing Dt:
|
03/14/2013
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Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
|
COMPUTER READABLE MEDIUM ENCODED WITH A PROGRAM FOR FABRICATING A 3D INTEGRATED CIRCUIT STRUCTURE
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|
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Patent #:
|
|
Issue Dt:
|
09/02/2014
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Application #:
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13827690
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Filing Dt:
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03/14/2013
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Publication #:
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|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
IMPLEMENTING Z DIRECTIONAL MACRO PORT ASSIGNMENT
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|
|
Patent #:
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NONE
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Issue Dt:
|
|
Application #:
|
13828249
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Filing Dt:
|
03/14/2013
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Publication #:
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|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
TITANIUM NITRIDE REMOVAL
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|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
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Application #:
|
13828276
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Filing Dt:
|
03/14/2013
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Title:
|
DOPING OF FINFET STRUCTURES
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13828340
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Filing Dt:
|
03/14/2013
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Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
WAFER-TO-WAFER FUSION BONDING CHUCK
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|
|
Patent #:
|
|
Issue Dt:
|
06/30/2015
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Application #:
|
13828650
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Filing Dt:
|
03/14/2013
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Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
SELECTIVE ETCH CHEMISTRY FOR GATE ELECTRODE MATERIALS
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|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13828936
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Filing Dt:
|
03/14/2013
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Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
DUAL THREE-DIMENSIONAL (3D) RESISTOR AND METHODS OF FORMING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
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Application #:
|
13832929
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Filing Dt:
|
03/15/2013
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Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
Title:
|
LOW HARMONIC RF SWITCH IN SOI
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
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Application #:
|
13833139
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Filing Dt:
|
03/15/2013
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Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
POST-FABRICATION SELF-ALIGNED INITIALIZATION OF INTEGRATED DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
10/04/2016
|
Application #:
|
13833317
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Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
WET STRIP PROCESS FOR AN ANTIREFLECTIVE COATING LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
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Application #:
|
13833656
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Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHOD AND STRUCTURE FOR PFET JUNCTION PROFILE WITH SIGE CHANNEL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13833713
|
Filing Dt:
|
03/15/2013
|
Title:
|
FACILITATING THE DESIGN OF A CLOCK GRID IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13833735
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Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2016
|
Application #:
|
13835166
|
Filing Dt:
|
03/15/2013
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Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
PASSIVE COMPRESSED GAS STORAGE CONTAINER TEMPERATURE STABILIZER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2016
|
Application #:
|
13835358
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
SEMICONDUCTOR TEST WAFER AND METHODS FOR USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2016
|
Application #:
|
13835463
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/08/2013
| | | | |
Title:
|
EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13837810
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Filing Dt:
|
03/15/2013
|
Title:
|
SELF ALIGNED CAPACITOR FABRICATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13838695
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
11/21/2013
| | | | |
Title:
|
CRYSTALLINE THIN-FILM TRANSISTORS AND METHODS OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13838890
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
Title:
|
HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13838956
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/29/2013
| | | | |
Title:
|
HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13839020
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
Title:
|
HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13839100
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
11/28/2013
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
|
Application #:
|
13839161
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
11/28/2013
| | | | |
Title:
|
METHODS OF FORMING CONTACT REGIONS USING SACRIFICIAL LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
13839213
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
Title:
|
THIN FILM HYBRID JUNCTION FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13839275
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
11/28/2013
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTORS WITH THIN EPITAXIAL CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13839626
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13839802
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2016
|
Application #:
|
13840132
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
CAPACITOR USING BARRIER LAYER METALLURGY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13841984
|
Filing Dt:
|
03/15/2013
|
Title:
|
GATE ELECTRODE OPTIMIZED FOR LOW VOLTAGE OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13842217
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
Title:
|
REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13842564
|
Filing Dt:
|
03/15/2013
|
Publication #:
|
|
Pub Dt:
|
08/29/2013
| | | | |
Title:
|
MICRO-ELECTRO-MECHANICAL SYSTEM TILTABLE LENS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13845394
|
Filing Dt:
|
03/18/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
REPLACEMENT GATE ELECTRODE WITH A SELF-ALIGNED DIELECTRIC SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13845506
|
Filing Dt:
|
03/18/2013
|
Publication #:
|
|
Pub Dt:
|
09/05/2013
| | | | |
Title:
|
EMBEDDED DRAM FOR EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
13845560
|
Filing Dt:
|
03/18/2013
|
Publication #:
|
|
Pub Dt:
|
08/22/2013
| | | | |
Title:
|
METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13845931
|
Filing Dt:
|
03/18/2013
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
Title:
|
ANALYZING TIMING REQUIREMENTS OF A HIERARCHICAL INTEGRATED CIRCUIT DESIGN
|
|