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Patent #:
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|
Issue Dt:
|
10/17/2017
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Application #:
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15455588
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Filing Dt:
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03/10/2017
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Title:
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JUNCTION FORMATION WITH REDUCED CEFF FOR 22NM FDSOI DEVICES
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Patent #:
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Issue Dt:
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02/27/2018
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Application #:
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15457017
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Filing Dt:
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03/13/2017
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Publication #:
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Pub Dt:
|
01/25/2018
| | | | |
Title:
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FIN-TYPE FIELD-EFFECT TRANSISTORS WITH STRAINED CHANNELS
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Patent #:
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Issue Dt:
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10/16/2018
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Application #:
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15457384
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Filing Dt:
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03/13/2017
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Publication #:
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Pub Dt:
|
10/05/2017
| | | | |
Title:
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SEMICONDUCTOR STRUCTURE INCLUDING A TRENCH CAPPING LAYER
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Patent #:
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Issue Dt:
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02/13/2018
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Application #:
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15458124
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Filing Dt:
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03/14/2017
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Title:
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METHOD AND DEVICE FOR MEASURING PLATING RING ASSEMBLY DIMENSIONS
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Patent #:
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Issue Dt:
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06/19/2018
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Application #:
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15458140
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Filing Dt:
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03/14/2017
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Publication #:
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Pub Dt:
|
06/29/2017
| | | | |
Title:
|
METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER AND IN ADJACENT INTERCONNECTING LAYERS OF AN IC DEVICE
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Patent #:
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Issue Dt:
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06/12/2018
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Application #:
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15458316
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Filing Dt:
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03/14/2017
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Publication #:
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Pub Dt:
|
08/03/2017
| | | | |
Title:
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METHODS TO UTILIZE PIEZOELECTRIC MATERIALS AS GATE DIELECTRIC IN HIGH FREQUENCY RBTs IN AN IC DEVICE
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Patent #:
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Issue Dt:
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01/16/2018
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Application #:
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15459450
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Filing Dt:
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03/15/2017
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Publication #:
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Pub Dt:
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08/31/2017
| | | | |
Title:
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SERIAL CAPACITOR DEVICE WITH MIDDLE ELECTRODE CONTACT
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Patent #:
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Issue Dt:
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07/03/2018
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Application #:
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15460914
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Filing Dt:
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03/16/2017
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Title:
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ON-CHIP RESISTORS WITH A TUNABLE TEMPERATURE COEFFICIENT OF RESISTANCE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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15460976
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Filing Dt:
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03/16/2017
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Publication #:
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Pub Dt:
|
06/29/2017
| | | | |
Title:
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METHODS AND DEVICES FOR METAL FILLING PROCESSES
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Patent #:
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Issue Dt:
|
09/04/2018
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Application #:
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15461538
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Filing Dt:
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03/17/2017
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Publication #:
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Pub Dt:
|
06/29/2017
| | | | |
Title:
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PROCESS FLOW FOR A COMBINED CA AND TSV OXIDE DEPOSITION
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Patent #:
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Issue Dt:
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05/29/2018
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Application #:
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15462644
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Filing Dt:
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03/17/2017
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Publication #:
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Pub Dt:
|
07/06/2017
| | | | |
Title:
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REPLACEMENT LOW-K SPACER
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Patent #:
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|
Issue Dt:
|
02/13/2018
|
Application #:
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15462657
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Filing Dt:
|
03/17/2017
|
Publication #:
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|
Pub Dt:
|
07/06/2017
| | | | |
Title:
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REPLACEMENT LOW-K SPACER
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|
Patent #:
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|
Issue Dt:
|
07/24/2018
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Application #:
|
15463316
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Filing Dt:
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03/20/2017
|
Title:
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PROGRAMMABLE LOGIC ELEMENTS AND METHODS OF OPERATING THE SAME
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|
Patent #:
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|
Issue Dt:
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05/08/2018
|
Application #:
|
15463394
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Filing Dt:
|
03/20/2017
|
Title:
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STORAGE STRUCTURE WITH NON-VOLATILE STORAGE CAPABILITY AND A METHOD OF OPERATING THE SAME
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Patent #:
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Issue Dt:
|
02/13/2018
|
Application #:
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15464397
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Filing Dt:
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03/21/2017
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Title:
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TRANSMISSION SYSTEM HAVING DUPLICATE TRANSMISSION SYSTEMS FOR INDIVIDUALIZED PRECHARGE AND OUTPUT TIMING
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Patent #:
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Issue Dt:
|
06/19/2018
|
Application #:
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15464591
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Filing Dt:
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03/21/2017
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Title:
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SUB-FIN DOPING METHOD
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Patent #:
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Issue Dt:
|
12/26/2017
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Application #:
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15467589
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Filing Dt:
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03/23/2017
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Title:
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PEAKING AMPLIFIER FREQUENCY TUNING
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|
Patent #:
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|
Issue Dt:
|
07/24/2018
|
Application #:
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15467610
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Filing Dt:
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03/23/2017
|
Title:
|
PEAKING AMPLIFIER FREQUENCY TUNING
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|
Patent #:
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|
Issue Dt:
|
05/01/2018
|
Application #:
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15467617
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Filing Dt:
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03/23/2017
|
Title:
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PEAKING AMPLIFIER FREQUENCY TUNING
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|
Patent #:
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Issue Dt:
|
06/26/2018
|
Application #:
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15469983
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Filing Dt:
|
03/27/2017
|
Title:
|
LAMINATED SPACERS FOR FIELD-EFFECT TRANSISTORS
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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15470006
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Filing Dt:
|
03/27/2017
|
Publication #:
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Pub Dt:
|
07/20/2017
| | | | |
Title:
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SELF-ALIGNED DEVICE LEVEL CONTACT STRUCTURES
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Patent #:
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Issue Dt:
|
09/26/2017
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Application #:
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15471733
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Filing Dt:
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03/28/2017
|
Publication #:
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Pub Dt:
|
07/13/2017
| | | | |
Title:
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SELF ALIGNED GATE SHAPE PREVENTING VOID FORMATION
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Patent #:
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Issue Dt:
|
04/03/2018
|
Application #:
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15472556
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Filing Dt:
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03/29/2017
|
Publication #:
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|
Pub Dt:
|
07/13/2017
| | | | |
Title:
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METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH FILLED GATE LINE END RECESSES
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|
Patent #:
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Issue Dt:
|
09/04/2018
|
Application #:
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15472924
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Filing Dt:
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03/29/2017
|
Publication #:
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|
Pub Dt:
|
07/13/2017
| | | | |
Title:
|
METHODS, APPARATUS AND SYSTEM FOR PROVIDING SOURCE-DRAIN EPITAXY LAYER WITH LATERAL OVER-GROWTH SUPPRESSION
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|
Patent #:
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Issue Dt:
|
05/14/2019
|
Application #:
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15473371
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Filing Dt:
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03/29/2017
|
Publication #:
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|
Pub Dt:
|
07/20/2017
| | | | |
Title:
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METHOD, APPARATUS, AND SYSTEM FOR OFFSET METAL POWER RAIL FOR CELL DESIGN
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|
Patent #:
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Issue Dt:
|
10/30/2018
|
Application #:
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15474408
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Filing Dt:
|
03/30/2017
|
Publication #:
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Pub Dt:
|
07/20/2017
| | | | |
Title:
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SAMPLING FOR OPC MODEL BUILDING
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|
Patent #:
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Issue Dt:
|
07/23/2019
|
Application #:
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15476158
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Filing Dt:
|
03/31/2017
|
Publication #:
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Pub Dt:
|
07/20/2017
| | | | |
Title:
|
STRUCTURES WITH THINNED DIELECTRIC MATERIAL
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|
Patent #:
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|
Issue Dt:
|
12/25/2018
|
Application #:
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15478385
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Filing Dt:
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04/04/2017
|
Publication #:
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|
Pub Dt:
|
07/20/2017
| | | | |
Title:
|
METHOD FOR FORMING BEOL METAL LEVELS WITH MULTIPLE DIELECTRIC LAYERS FOR IMPROVED DIELECTRIC TO METAL ADHESION
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Patent #:
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Issue Dt:
|
10/10/2017
|
Application #:
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15478820
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Filing Dt:
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04/04/2017
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Publication #:
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Pub Dt:
|
07/20/2017
| | | | |
Title:
|
DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY
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|
Patent #:
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|
Issue Dt:
|
12/19/2017
|
Application #:
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15479801
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Filing Dt:
|
04/05/2017
|
Title:
|
STACKED NANOSHEET FIELD-EFFECT TRANSISTOR WITH DIODE ISOLATION
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|
Patent #:
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|
Issue Dt:
|
08/21/2018
|
Application #:
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15480931
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Filing Dt:
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04/06/2017
|
Title:
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CURRENT MIRROR DEVICES USING CASCODE WITH BACK-GATE BIAS
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Patent #:
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Issue Dt:
|
12/04/2018
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Application #:
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15481202
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Filing Dt:
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04/06/2017
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Publication #:
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Pub Dt:
|
01/25/2018
| | | | |
Title:
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METHODS FOR AN ESD PROTECTION CIRCUIT INCLUDING TRIGGER-VOLTAGE TUNABLE CASCODE TRANSISTORS
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Patent #:
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Issue Dt:
|
04/03/2018
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Application #:
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15482040
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Filing Dt:
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04/07/2017
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Publication #:
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Pub Dt:
|
08/24/2017
| | | | |
Title:
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FIN CUT FOR TAPER DEVICE
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|
Patent #:
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|
Issue Dt:
|
08/07/2018
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Application #:
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15482938
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Filing Dt:
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04/10/2017
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Publication #:
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Pub Dt:
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07/27/2017
| | | | |
Title:
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ELECTRODEPOSITION SYSTEMS AND METHODS THAT MINIMIZE ANODE AND/OR PLATING SOLUTION DEGRADATION
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Patent #:
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Issue Dt:
|
05/15/2018
|
Application #:
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15483344
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Filing Dt:
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04/10/2017
|
Title:
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FIN STRUCTURE IN SUBLITHO DIMENSION FOR HIGH PERFORMANCE CMOS APPLICATION
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|
Patent #:
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Issue Dt:
|
05/29/2018
|
Application #:
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15483346
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Filing Dt:
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04/10/2017
|
Publication #:
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Pub Dt:
|
07/27/2017
| | | | |
Title:
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FIN CUT FOR TAPER DEVICE
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|
Patent #:
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|
Issue Dt:
|
03/23/2021
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Application #:
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15484173
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Filing Dt:
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04/11/2017
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Publication #:
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Pub Dt:
|
08/03/2017
| | | | |
Title:
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GATE CUT WITH HIGH SELECTIVITY TO PRESERVE INTERLEVEL DIELECTRIC LAYER
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Patent #:
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Issue Dt:
|
03/19/2019
|
Application #:
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15484309
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Filing Dt:
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04/11/2017
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Publication #:
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Pub Dt:
|
08/03/2017
| | | | |
Title:
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SELF-ALIGNED LOCAL INTERCONNECT TECHNOLOGY
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Patent #:
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Issue Dt:
|
11/14/2017
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Application #:
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15486387
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Filing Dt:
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04/13/2017
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Title:
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GATE CUT METHOD FOR REPLACEMENT METAL GATE INTEGRATION
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Patent #:
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Issue Dt:
|
07/03/2018
|
Application #:
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15487636
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Filing Dt:
|
04/14/2017
|
Title:
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FIN-TYPE FIELD EFFECT TRANSISTORS WITH SINGLE-DIFFUSION BREAKS AND METHOD
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|
Patent #:
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|
Issue Dt:
|
11/28/2017
|
Application #:
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15489404
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Filing Dt:
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04/17/2017
|
Publication #:
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Pub Dt:
|
08/03/2017
| | | | |
Title:
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METHOD, APPARATUS, AND SYSTEM FOR E-FUSE IN ADVANCED CMOS TECHNOLOGIES
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Patent #:
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Issue Dt:
|
06/26/2018
|
Application #:
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15490180
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Filing Dt:
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04/18/2017
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Publication #:
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Pub Dt:
|
08/03/2017
| | | | |
Title:
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EPI FACET HEIGHT UNIFORMITY IMPROVEMENT FOR FDSOI TECHNOLOGIES
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Patent #:
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|
Issue Dt:
|
05/08/2018
|
Application #:
|
15490181
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Filing Dt:
|
04/18/2017
|
Title:
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PRE-SPACER SELF-ALIGNED CUT FORMATION
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|
Patent #:
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|
Issue Dt:
|
05/01/2018
|
Application #:
|
15490255
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Filing Dt:
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04/18/2017
|
Title:
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METHOD OF FORMING VERTICAL FIELD EFFECT TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES AND THE RESULTING INTEGRATED CIRCUIT STRUCTURE
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Patent #:
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Issue Dt:
|
08/21/2018
|
Application #:
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15490702
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Filing Dt:
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04/18/2017
|
Publication #:
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Pub Dt:
|
08/03/2017
| | | | |
Title:
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TRANSISTOR CONTACTS SELF-ALIGNED IN TWO DIMENSIONS
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Patent #:
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|
Issue Dt:
|
03/20/2018
|
Application #:
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15491222
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Filing Dt:
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04/19/2017
|
Title:
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EMBEDDED SILICON CARBIDE BLOCK PATTERNING
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|
Patent #:
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|
Issue Dt:
|
07/03/2018
|
Application #:
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15491420
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Filing Dt:
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04/19/2017
|
Title:
|
AIR GAP ADJACENT A BOTTOM SOURCE/DRAIN REGION OF VERTICAL TRANSISTOR DEVICE
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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15491465
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Filing Dt:
|
04/19/2017
|
Publication #:
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|
Pub Dt:
|
08/03/2017
| | | | |
Title:
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SEMICONDUCTOR STRUCTURE(S) WITH EXTENDED SOURCE/DRAIN CHANNEL INTERFACES AND METHODS OF FABRICATION
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Patent #:
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Issue Dt:
|
08/21/2018
|
Application #:
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15494119
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Filing Dt:
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04/21/2017
|
Title:
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INTEGRATION SCHEME FOR GATE HEIGHT CONTROL AND VOID FREE RMG FILL
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|
Patent #:
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|
Issue Dt:
|
02/27/2018
|
Application #:
|
15494803
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Filing Dt:
|
04/24/2017
|
Title:
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SELF-ALIGNED NON-MANDREL CUT FORMATION FOR TONE INVERSION
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|
Patent #:
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|
Issue Dt:
|
06/19/2018
|
Application #:
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15496049
|
Filing Dt:
|
04/25/2017
|
Publication #:
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|
Pub Dt:
|
08/10/2017
| | | | |
Title:
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MODIFIED TUNNELING FIELD EFFECT TRANSISTORS AND FABRICATION METHODS
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|
Patent #:
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|
Issue Dt:
|
04/24/2018
|
Application #:
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15497828
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Filing Dt:
|
04/26/2017
|
Title:
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LINER REPLACEMENTS FOR INTERCONNECT OPENINGS
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|
Patent #:
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|
Issue Dt:
|
05/21/2019
|
Application #:
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15497924
|
Filing Dt:
|
04/26/2017
|
Publication #:
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|
Pub Dt:
|
08/10/2017
| | | | |
Title:
|
ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERTICAL GATE FIN-TYPE FIELD EFFECT DIODE
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|
Patent #:
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|
Issue Dt:
|
07/24/2018
|
Application #:
|
15498652
|
Filing Dt:
|
04/27/2017
|
Publication #:
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|
Pub Dt:
|
09/21/2017
| | | | |
Title:
|
FINFET BASED FLASH MEMORY CELL
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
15499222
|
Filing Dt:
|
04/27/2017
|
Publication #:
|
|
Pub Dt:
|
08/10/2017
| | | | |
Title:
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FIELD EFFECT TRANSISTORS WITH VARYING THRESHOLD VOLTAGES
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|
|
Patent #:
|
|
Issue Dt:
|
01/08/2019
|
Application #:
|
15531458
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Filing Dt:
|
05/29/2017
|
Publication #:
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|
Pub Dt:
|
09/21/2017
| | | | |
Title:
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A SYSTEM AND METHOD FOR ACTIVE POWER FACTOR CORRECTION AND CURRENT REGULATION IN LED CIRCUIT
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
15531459
|
Filing Dt:
|
05/29/2017
|
Publication #:
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|
Pub Dt:
|
09/21/2017
| | | | |
Title:
|
DYNAMIC BLEED SYSTEM AND METHOD FOR DYNAMIC LOADING OF A DIMMER USING EVENT DRIVEN ARCHITECTURE
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|
Patent #:
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|
Issue Dt:
|
07/09/2019
|
Application #:
|
15531460
|
Filing Dt:
|
05/29/2017
|
Publication #:
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|
Pub Dt:
|
10/11/2018
| | | | |
Title:
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SYSTEM AND METHOD TO REGULATE PRIMARY SIDE CURRENT USING AN EVENT DRIVEN ARCHITECTURE IN LED CIRCUIT
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|
Patent #:
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|
Issue Dt:
|
02/06/2018
|
Application #:
|
15581510
|
Filing Dt:
|
04/28/2017
|
Title:
|
METHODS FOR PROVIDING VARIABLE FEATURE WIDTHS IN A SELF-ALIGNED SPACER-MASK PATTERNING PROCESS
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|
|
Patent #:
|
|
Issue Dt:
|
02/06/2018
|
Application #:
|
15585800
|
Filing Dt:
|
05/03/2017
|
Title:
|
METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL ON THE SOURCE/DRAIN REGIONS OF A FINFET DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
11/14/2017
|
Application #:
|
15585972
|
Filing Dt:
|
05/03/2017
|
Publication #:
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|
Pub Dt:
|
08/17/2017
| | | | |
Title:
|
METHOD WHEREIN TEST CELLS AND DUMMY CELLS ARE INCLUDED INTO A LAYOUT OF AN INTEGRATED CIRCUIT
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|
Patent #:
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|
Issue Dt:
|
03/06/2018
|
Application #:
|
15586621
|
Filing Dt:
|
05/04/2017
|
Title:
|
VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH A DAMASCENE GATE STRAP
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|
|
Patent #:
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|
Issue Dt:
|
06/26/2018
|
Application #:
|
15589139
|
Filing Dt:
|
05/08/2017
|
Title:
|
METHOD FOR FORMING SEMICONDUCTOR DEVICE HAVING CONTINUOUS FIN DIFFUSION BREAK
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|
|
Patent #:
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|
Issue Dt:
|
04/03/2018
|
Application #:
|
15589292
|
Filing Dt:
|
05/08/2017
|
Title:
|
FIN-TYPE FIELD EFFECT TRANSISTORS WITH SINGLE-DIFFUSION BREAKS AND METHOD
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|
|
Patent #:
|
|
Issue Dt:
|
07/03/2018
|
Application #:
|
15589312
|
Filing Dt:
|
05/08/2017
|
Title:
|
METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE USING EXTREME ULTRAVIOLET PHOTOLITHOGRAPHY TECHNIQUE AND RELATED INTEGRATED CIRCUIT STRUCTURE
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Patent #:
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Issue Dt:
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07/17/2018
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Application #:
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15589829
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Filing Dt:
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05/08/2017
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Publication #:
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Pub Dt:
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08/24/2017
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Title:
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METHOD, APPARATUS, AND SYSTEM FOR MOL INTERCONNECTS WITHOUT TITANIUM LINER
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Patent #:
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Issue Dt:
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07/09/2019
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Application #:
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15590459
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Filing Dt:
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05/09/2017
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Publication #:
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Pub Dt:
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12/21/2017
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Title:
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DEVICE FOR IMPROVING PERFORMANCE THROUGH GATE CUT LAST PROCESS
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Patent #:
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Issue Dt:
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08/07/2018
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Application #:
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15591814
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Filing Dt:
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05/10/2017
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Title:
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METHOD TO REDUCE FINFET SHORT CHANNEL GATE HEIGHT
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Patent #:
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Issue Dt:
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02/20/2018
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Application #:
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15592597
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Filing Dt:
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05/11/2017
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Publication #:
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Pub Dt:
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08/31/2017
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Title:
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INCREASED CONTACT AREA FOR FINFETS
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Patent #:
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Issue Dt:
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07/03/2018
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Application #:
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15593496
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Filing Dt:
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05/12/2017
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Publication #:
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Pub Dt:
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08/31/2017
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Title:
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ELECTRONIC DEVICE INCLUDING MOAT POWER METALLIZATION IN TRENCH
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Patent #:
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NONE
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Issue Dt:
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Application #:
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15594059
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Filing Dt:
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05/12/2017
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Publication #:
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Pub Dt:
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11/09/2017
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Title:
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LASER SCRIBE STRUCTURES FOR A WAFER
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Patent #:
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Issue Dt:
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03/27/2018
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Application #:
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15594757
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Filing Dt:
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05/15/2017
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Publication #:
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Pub Dt:
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08/31/2017
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Title:
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ETCH STOP FOR AIRGAP PROTECTION
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Patent #:
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Issue Dt:
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05/05/2020
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Application #:
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15597650
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Filing Dt:
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05/17/2017
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Publication #:
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Pub Dt:
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01/04/2018
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Title:
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SURFACE AREA AND SCHOTTKY BARRIER HEIGHT ENGINEERING FOR CONTACT TRENCH EPITAXY
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Patent #:
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Issue Dt:
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02/27/2018
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Application #:
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15598447
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Filing Dt:
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05/18/2017
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Title:
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SELF-ALIGNED CONTACT ETCH FOR FABRICATING A FINFET
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Patent #:
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Issue Dt:
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06/16/2020
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Application #:
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15598905
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Filing Dt:
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05/18/2017
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Publication #:
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Pub Dt:
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09/14/2017
| | | | |
Title:
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VERTICAL NANOWIRES FORMED ON UPPER FIN SURFACE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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15599026
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Filing Dt:
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05/18/2017
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Publication #:
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Pub Dt:
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09/07/2017
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Title:
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METHODS TO FORM MULTI THRESHOLD-VOLTAGE DUAL CHANNEL WITHOUT CHANNEL DOPING
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Patent #:
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Issue Dt:
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08/20/2019
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Application #:
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15599427
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Filing Dt:
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05/18/2017
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Publication #:
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Pub Dt:
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11/23/2017
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Title:
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LIGHT EMITTING DIODES (LEDS) WITH STACKED MULTI-COLOR PIXELS FOR DISPLAYS
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Patent #:
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Issue Dt:
|
04/10/2018
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Application #:
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15599438
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Filing Dt:
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05/18/2017
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Publication #:
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Pub Dt:
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11/23/2017
| | | | |
Title:
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LIGHT EMITTING DIODES (LEDs) WITH INTEGRATED CMOS CIRCUITS
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Patent #:
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Issue Dt:
|
04/10/2018
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Application #:
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15599458
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Filing Dt:
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05/18/2017
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Publication #:
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Pub Dt:
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11/23/2017
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Title:
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LEDS WITH THREE COLOR RGB PIXELS FOR DISPLAYS
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Patent #:
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Issue Dt:
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07/31/2018
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Application #:
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15599465
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Filing Dt:
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05/18/2017
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Publication #:
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Pub Dt:
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12/14/2017
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Title:
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INTEGRATED DISPLAY SYSTEM WITH MULTI-COLOR LIGHT EMITTING DIODES (LEDS)
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Patent #:
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Issue Dt:
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04/03/2018
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Application #:
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15599581
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Filing Dt:
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05/19/2017
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Title:
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SRAM CELL HAVING DUAL PASS GATE TRANSISTORS AND METHOD OF MAKING THE SAME
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Patent #:
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NONE
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Issue Dt:
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Application #:
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15599751
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Filing Dt:
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05/19/2017
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Publication #:
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Pub Dt:
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09/07/2017
| | | | |
Title:
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METHOD OF FORMING SUPER STEEP RETROGRADE WELLS ON FINFET
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|
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Patent #:
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Issue Dt:
|
05/01/2018
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Application #:
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15600837
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Filing Dt:
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05/22/2017
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Publication #:
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Pub Dt:
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09/14/2017
| | | | |
Title:
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EXPITAXIALLY REGROWN HETEROSTRUCTURE NANOWIRE LATERAL TUNNEL FIELD EFFECT TRANSISTOR
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Patent #:
|
|
Issue Dt:
|
04/17/2018
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Application #:
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15600874
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Filing Dt:
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05/22/2017
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Title:
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METHODS OF FORMING A GATE CONTACT FOR A TRANSISTOR ABOVE AN ACTIVE REGION AND THE RESULTING DEVICE
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Patent #:
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Issue Dt:
|
05/15/2018
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Application #:
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15604803
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Filing Dt:
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05/25/2017
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Publication #:
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Pub Dt:
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09/21/2017
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Title:
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THREE-DIMENSIONAL HYBRID PACKAGING WITH THROUGH-SILICON-VIAS AND TAPE-AUTOMATED-BONDING
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Patent #:
|
|
Issue Dt:
|
10/09/2018
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Application #:
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15608283
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Filing Dt:
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05/30/2017
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Publication #:
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Pub Dt:
|
09/14/2017
| | | | |
Title:
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FINFET SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SAME
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|
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Patent #:
|
|
Issue Dt:
|
02/13/2018
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Application #:
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15609295
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Filing Dt:
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05/31/2017
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Publication #:
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|
Pub Dt:
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10/12/2017
| | | | |
Title:
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RECESS LINER FOR SILICON GERMANIUM FIN FORMATION
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|
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Patent #:
|
|
Issue Dt:
|
07/31/2018
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Application #:
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15609603
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Filing Dt:
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05/31/2017
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Title:
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INTEGRATED SINGLE-GATED VERTICAL FIELD EFFECT TRANSISTOR (VFET) AND INDEPENDENT DOUBLE-GATED VFET
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|
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Patent #:
|
|
Issue Dt:
|
03/20/2018
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Application #:
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15611184
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Filing Dt:
|
06/01/2017
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Title:
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SWITCHES WITH DEEP TRENCH DEPLETION AND ISOLATION STRUCTURES
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|
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Patent #:
|
|
Issue Dt:
|
06/26/2018
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Application #:
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15612335
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Filing Dt:
|
06/02/2017
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Title:
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ENLARGED SACRIFICIAL GATE CAPS FOR FORMING SELF-ALIGNED CONTACTS
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|
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Patent #:
|
|
Issue Dt:
|
01/02/2018
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Application #:
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15614925
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Filing Dt:
|
06/06/2017
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Title:
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MIDDLE OF THE LINE (MOL) METAL CONTACTS
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|
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Patent #:
|
|
Issue Dt:
|
10/02/2018
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Application #:
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15615072
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Filing Dt:
|
06/06/2017
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Publication #:
|
|
Pub Dt:
|
09/21/2017
| | | | |
Title:
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METHODS OF PREDICTING UNITY GAIN FREQUENCY WITH DIRECT CURRENT AND/OR LOW FREQUENCY PARAMETERS
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|
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Patent #:
|
|
Issue Dt:
|
09/04/2018
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Application #:
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15615660
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Filing Dt:
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06/06/2017
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Publication #:
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Pub Dt:
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09/21/2017
| | | | |
Title:
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METHODS, APPARATUS, AND SYSTEM FOR GLOBAL HEALING OF WRITE-LIMITED DIE THROUGH BIAS TEMPERATURE INSTABILITY
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|
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Patent #:
|
|
Issue Dt:
|
05/01/2018
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Application #:
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15616653
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Filing Dt:
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06/07/2017
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Publication #:
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Pub Dt:
|
01/25/2018
| | | | |
Title:
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FIN-BASED RF DIODES
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|
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Patent #:
|
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Issue Dt:
|
05/01/2018
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Application #:
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15618197
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Filing Dt:
|
06/09/2017
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Publication #:
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|
Pub Dt:
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09/28/2017
| | | | |
Title:
|
SYSTEM AND METHOD TO ADJUST VEHICLE TEMPERATURE BASED ON DRIVER LOCATION
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|
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Patent #:
|
|
Issue Dt:
|
04/10/2018
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Application #:
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15618880
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Filing Dt:
|
06/09/2017
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Publication #:
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Pub Dt:
|
09/28/2017
| | | | |
Title:
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GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
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|
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Patent #:
|
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Issue Dt:
|
02/27/2018
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Application #:
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15620082
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Filing Dt:
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06/12/2017
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Publication #:
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Pub Dt:
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09/28/2017
| | | | |
Title:
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STRESS MEMORIZATION AND DEFECT SUPPRESSION TECHNIQUES FOR NMOS TRANSISTOR DEVICES
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|
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Patent #:
|
|
Issue Dt:
|
05/21/2019
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Application #:
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15621529
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Filing Dt:
|
06/13/2017
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Publication #:
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Pub Dt:
|
09/28/2017
| | | | |
Title:
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PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTAGE BINNING
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|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
15622549
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Filing Dt:
|
06/14/2017
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Publication #:
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Pub Dt:
|
11/16/2017
| | | | |
Title:
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AIR GAPS FORMED BY POROUS SILICON REMOVAL
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|
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Patent #:
|
|
Issue Dt:
|
03/06/2018
|
Application #:
|
15622949
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Filing Dt:
|
06/14/2017
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Title:
|
METHOD OF FORMING FIELD EFFECT TRANSISTORS WITH REPLACEMENT METAL GATES AND CONTACTS AND RESULTING STRUCTURE
|
|