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09/18/2012
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12901825
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10/11/2010
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02/03/2011
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09/04/2012
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12901937
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10/11/2010
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02/03/2011
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08/23/2011
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12901997
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10/11/2010
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02/03/2011
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04/28/2015
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10/11/2010
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02/03/2011
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04/16/2013
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10/12/2010
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04/12/2012
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ATOMIC LAYER DEPOSITION OF CRYSTALLINE PRCAMNO (PCMO) AND RELATED METHODS
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08/23/2011
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10/12/2010
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04/14/2011
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03/27/2012
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10/12/2010
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02/03/2011
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12/06/2011
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10/12/2010
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02/03/2011
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CLOCK JITTER COMPENSATED CLOCK CIRCUITS AND METHODS FOR GENERATING JITTER COMPENSATED CLOCK SIGNALS
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02/19/2013
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12903264
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10/13/2010
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04/19/2012
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Title:
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MEMORY ARRAYS WHERE A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT ONE END OF A SUBSTANTIALLY VERTICAL PORTION IS GREATER THAN A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT AN OPPOSING END OF THE SUBSTANTIALLY VERTICAL PORTION AND FORMATION THEREOF
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10/18/2011
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12903936
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10/13/2010
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02/10/2011
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SYSTEMS AND DEVICES INCLUDING MEMORY WITH BUILT-IN SELF TEST AND METHODS OF MAKING AND USING THE SAME
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10/11/2011
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12904038
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10/13/2010
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02/17/2011
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02/21/2012
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12904314
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10/14/2010
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02/03/2011
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SYSTEM WITH SEMICONDUCTOR COMPONENTS HAVING ENCAPSULATED THROUGH WIRE INTERCONNECTS (TWI)
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10/30/2018
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12904807
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10/14/2010
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04/19/2012
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NONVOLATILE STORAGE USING LOW LATENCY AND HIGH LATENCY MEMORY
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07/02/2013
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12905534
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10/15/2010
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02/10/2011
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PHASE CHANGE MEMORY ADAPTIVE PROGRAMMING
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05/31/2011
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12905708
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10/15/2010
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02/10/2011
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DIE STACKING WITH AN ANNULAR VIA HAVING A RECESSED SOCKET
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06/18/2013
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12905754
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10/15/2010
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04/19/2012
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READ DISTRIBUTION MANAGEMENT FOR PHASE CHANGE MEMORY
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03/20/2012
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12906497
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10/18/2010
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02/10/2011
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02/21/2012
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12906764
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10/18/2010
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02/10/2011
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JTAG CONTROLLED SELF-REPAIR AFTER PACKAGING
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04/03/2012
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12906799
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10/18/2010
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02/10/2011
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METHOD AND ALGORITHM FOR RANDOM HALF PITCHED INTERCONNECT LAYOUT WITH CONSTANT SPACING
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02/07/2012
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12906806
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10/18/2010
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02/10/2011
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DEVICES AND METHODS FOR A THRESHOLD VOLTAGE DIFFERENCE COMPENSATED SENSE AMPLIFIER
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12/24/2019
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12908206
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10/20/2010
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02/10/2011
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PITCH MULTIPLICATION USING SELF-ASSEMBLING MATERIALS
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09/04/2012
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12908438
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10/20/2010
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02/17/2011
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INTEGRATED CIRCUIT COMPARATOR OR AMPLIFIER
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05/01/2012
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12909414
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10/21/2010
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02/10/2011
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METHODS OF ERASE VERIFICATION FOR A FLASH MEMORY DEVICE
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06/24/2014
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12909650
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10/21/2010
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04/26/2012
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INTEGRATED CIRCUITRY COMPRISING NONVOLATILE MEMORY CELLS HAVING PLATELIKE ELECTRODE AND ION CONDUCTIVE MATERIAL LAYER
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07/17/2018
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12909678
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10/21/2010
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04/26/2012
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MEMORIES AND METHODS FOR PERFORMING VECTOR ATOMIC MEMORY OPERATIONS WITH MASK CONTROL AND VARIABLE DATA LENGTH AND DATA UNIT SIZE
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01/15/2013
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12910204
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10/22/2010
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04/28/2011
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SEMICONDUCTOR DEVICE HAVING OPEN BIT LINE ARCHITECTURE
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06/12/2012
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12910215
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10/22/2010
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02/17/2011
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MULTISAMPLING WITH REDUCED BIT SAMPLES
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06/10/2014
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12910404
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10/22/2010
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04/26/2012
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Title:
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GETTERING AGENTS IN MEMORY CHARGE STORAGE STRUCTURES
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10/02/2012
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12910496
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10/22/2010
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04/28/2011
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SEMICONDUCTOR DEVICE HAVING HIERARCHICAL DATA LINE STRUCTURE AND CONTROL METHOD THEREOF
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12911008
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10/25/2010
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Pub Dt:
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02/10/2011
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Title:
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MEMORY DEVICES AND METHOD FOR DRIVING A SIGNAL LINE TO A KNOWN SIGNAL LEVEL
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11/22/2011
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12911595
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10/25/2010
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02/24/2011
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CAPTURING READ DATA
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01/31/2012
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12912027
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10/26/2010
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03/10/2011
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MITIGATION OF DATA CORRUPTION FROM BACK PATTERN AND PROGRAM DISTURB IN A NON-VOLATILE MEMORY DEVICE
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12/13/2011
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12912829
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10/27/2010
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02/17/2011
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FABRICATING BIPOLAR JUNCTION SELECT TRANSISTORS FOR SEMICONDUCTOR MEMORIES
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10/23/2012
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12913158
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10/27/2010
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05/05/2011
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SEMICONDUCTOR DEVICE
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05/08/2012
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12914309
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10/28/2010
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02/17/2011
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APPARATUS AND METHOD FOR INCREASING DATA LINE NOISE TOLERANCE
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08/09/2011
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12914814
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10/28/2010
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02/17/2011
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Title:
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METHODS OF ETCHING NANODOTS, METHODS OF REMOVING NANODOTS FROM SUBSTRATES, METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES, METHODS OF ETCHING A LAYER COMPRISING A LATE TRANSITION METAL, AND METHODS OF REMOVING A LAYER COMPRISING A LATE TRANSITION METAL FROM A SU
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08/07/2012
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12915578
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10/29/2010
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02/17/2011
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APPARATUS HAVING A LANTHANUM-METAL OXIDE SEMICONDUCTOR DEVICE
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05/22/2012
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12915650
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10/29/2010
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02/24/2011
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MEMORY CELL WITH A VERTICALLY ORIENTED TRANSISTOR COUPLED TO A DIGIT LINE AND METHOD OF FORMING THE SAME
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05/15/2012
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12915665
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10/29/2010
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02/17/2011
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METHOD AND APPARATUS PROVIDING AUTOMATIC COLOR BALANCING FOR DIGITAL IMAGING SYSTEMS
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09/17/2013
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12916421
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10/29/2010
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11/03/2011
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INDEXED REGISTER ACCESS FOR MEMORY DEVICE
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02/14/2012
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12917241
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11/01/2010
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02/24/2011
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NON-VOLATILE MEMORY CELL READ FAILURE REDUCTION
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07/05/2011
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12917249
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11/01/2010
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02/24/2011
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MASKS FOR MICROLITHOGRAPHY AND METHODS OF MAKING AND USING SUCH MASKS
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12/18/2012
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12917339
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11/01/2010
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05/03/2012
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METHODS OF FORMING CONDUCTIVE CONTACTS IN THE FABRICATION OF INTEGRATED CIRCUITRY
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01/29/2013
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12917346
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11/01/2010
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05/03/2012
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MEMORY CELLS, ARRAYS OF MEMORY CELLS, AND METHODS OF FORMING MEMORY CELLS
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08/05/2014
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12917348
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11/01/2010
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05/03/2012
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NONVOLATILE MEMORY CELLS AND METHODS OF FORMING NONVOLATILE MEMORY CELL
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09/03/2013
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12917361
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11/01/2010
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05/03/2012
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MEMORY CELLS, METHODS OF PROGRAMMING MEMORY CELLS, AND METHODS OF FORMING MEMORY CELLS
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06/21/2011
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12917394
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11/01/2010
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02/24/2011
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FORMATION OF CARBON-CONTAINING MATERIAL
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07/12/2011
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12917571
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11/02/2010
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02/24/2011
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METHOD TO RECOVER THE EXPOSURE SENSITIVITY OF CHEMICALLY AMPLIFIED RESINS FROM POST COAT DELAY EFFECT
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03/25/2014
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12917930
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11/02/2010
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05/03/2012
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METHOD OF FORMING A CHALCOGENIDE MATERIAL AND METHODS OF FORMING A RESISTIVE RANDOM ACCESS MEMORY DEVICE INCLUDING A CHALCOGENIDE MATERIAL
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04/24/2012
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12923071
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08/31/2010
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03/17/2011
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SEMICONDUCTOR DEVICE HAVING LEVEL SHIFT CIRCUIT, CONTROL METHOD THEREOF, AND DATA PROCESSING SYSTEM
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08/28/2012
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12923168
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09/07/2010
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Pub Dt:
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03/10/2011
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Title:
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SEMICONDUCTOR MEMORY DEVICE HAVING PAD ELECTRODES ARRANGED IN PLURAL ROWS
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02/26/2013
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12923248
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09/10/2010
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03/17/2011
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SEMICONDUCTOR DEVICE USING PLURAL INTERNAL OPERATION VOLTAGES AND DATA PROCESSING SYSTEM USING THE SAME
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03/05/2013
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12926996
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12/22/2010
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06/30/2011
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Title:
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SEMICONDUCTOR DEVICE CAPABLE OF DETECTING DEFECT OF COLUMN SELECTION LINE
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01/08/2013
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12929327
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01/14/2011
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07/21/2011
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Title:
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SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM
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05/01/2012
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12938114
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11/02/2010
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02/24/2011
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Title:
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GATE STACKS AND SEMICONDUCTOR CONSTRUCTIONS
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04/29/2014
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12938130
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11/02/2010
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Pub Dt:
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05/03/2012
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DATA PATHS USING A FIRST SIGNAL TO CAPTURE DATA AND A SECOND SIGNAL TO OUTPUT DATA AND METHODS FOR PROVIDING DATA
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Issue Dt:
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11/26/2013
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12938208
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11/02/2010
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Publication #:
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Pub Dt:
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02/24/2011
| | | | |
Title:
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CONNECTION VERIFICATION TECHNIQUE
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Patent #:
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Issue Dt:
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12/11/2012
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Application #:
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12938845
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Filing Dt:
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11/03/2010
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Publication #:
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Pub Dt:
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05/03/2012
| | | | |
Title:
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METHODS OF FORMING DOPED REGIONS IN SEMICONDUCTOR SUBSTRATES
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Patent #:
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Issue Dt:
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08/30/2011
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Application #:
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12939869
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Filing Dt:
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11/04/2010
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Publication #:
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Pub Dt:
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05/05/2011
| | | | |
Title:
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BALANCED PHASE DETECTOR
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Patent #:
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Issue Dt:
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05/29/2012
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Application #:
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12940515
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Filing Dt:
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11/05/2010
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Publication #:
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Pub Dt:
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03/03/2011
| | | | |
Title:
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SYSTEM AND METHOD FOR OPTIMIZING INTERCONNECTIONS OF MEMORY DEVICES IN A MULTICHIP MODULE
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Patent #:
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Issue Dt:
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10/16/2012
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Application #:
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12940802
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Filing Dt:
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11/05/2010
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Publication #:
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Pub Dt:
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05/10/2012
| | | | |
Title:
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METHODS OF FORMING PATTERNED MASKS
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Patent #:
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Issue Dt:
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10/28/2014
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Application #:
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12940852
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Filing Dt:
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11/05/2010
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Publication #:
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Pub Dt:
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05/10/2012
| | | | |
Title:
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CIRCUITS AND METHODS FOR PROVIDING DATA TO AND FROM ARRAYS OF MEMORY CELLS
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Patent #:
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Issue Dt:
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06/26/2012
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Application #:
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12940948
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Filing Dt:
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11/05/2010
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Publication #:
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Pub Dt:
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02/24/2011
| | | | |
Title:
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MEMORY DEVICE COMPRISING AN ARRAY PORTION AND A LOGIC PORTION
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Patent #:
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Issue Dt:
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06/11/2013
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Application #:
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12941458
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Filing Dt:
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11/08/2010
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Publication #:
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Pub Dt:
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11/10/2011
| | | | |
Title:
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METHODS OF OPERATING MEMORY CELL HAVING ASYMMETRIC BAND-GAP TUNNEL INSULATOR USING DIRECT TUNNELING
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Patent #:
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Issue Dt:
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06/18/2013
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Application #:
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12941722
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Filing Dt:
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11/08/2010
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Publication #:
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Pub Dt:
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03/03/2011
| | | | |
Title:
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METHOD AND SYSTEM FOR GENERATING OBJECT CODE TO FACILITATE PREDICTIVE MEMORY RETRIEVAL
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Patent #:
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Issue Dt:
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10/04/2016
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Application #:
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12942044
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Filing Dt:
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11/09/2010
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Publication #:
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Pub Dt:
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03/10/2011
| | | | |
Title:
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PIXEL WITH STRAINED SILICON LAYER FOR IMPROVING CARRIER MOBILITY AND BLUE RESPONSE IN IMAGERS
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Patent #:
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Issue Dt:
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10/21/2014
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Application #:
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12942132
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Filing Dt:
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11/09/2010
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Publication #:
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Pub Dt:
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05/10/2012
| | | | |
Title:
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POST DEPOSITION ADJUSTMENT OF CHALCOGENIDE COMPOSITION IN CHALCOGENIDE CONTAINING SEMICONDUCTORS
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|
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Patent #:
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Issue Dt:
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09/15/2015
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Application #:
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12942152
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Filing Dt:
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11/09/2010
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Publication #:
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Pub Dt:
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05/10/2012
| | | | |
Title:
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SENSE OPERATION FLAGS IN A MEMORY DEVICE
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|
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Patent #:
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Issue Dt:
|
09/20/2011
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Application #:
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12943082
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Filing Dt:
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11/10/2010
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Publication #:
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Pub Dt:
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05/19/2011
| | | | |
Title:
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METHOD AND APPARATUS FOR DARK CURRENT AND BLOOMING SUPPRESSION IN 4T CMOS IMAGER PIXEL
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|
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Patent #:
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Issue Dt:
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02/19/2013
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Application #:
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12943370
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Filing Dt:
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11/10/2010
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Publication #:
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Pub Dt:
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05/10/2012
| | | | |
Title:
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METHODS OF FORMING A CRYSTALLINE PR1--XCAXMNO-3 (PCMO) MATERIAL AND METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES COMPRISING CRYSTALLINE PCMO
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Patent #:
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Issue Dt:
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12/03/2013
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Application #:
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12943551
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Filing Dt:
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11/10/2010
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Publication #:
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Pub Dt:
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12/15/2011
| | | | |
Title:
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ANALYZING DATA USING A HIERARCHICAL STRUCTURE
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|
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Patent #:
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Issue Dt:
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04/01/2014
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Application #:
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12943830
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Filing Dt:
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11/10/2010
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Publication #:
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Pub Dt:
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03/10/2011
| | | | |
Title:
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MEMORY CONTROLLER METHOD AND SYSTEM COMPENSATING FOR MEMORY CELL DATA LOSSES
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|
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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12944134
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Filing Dt:
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11/11/2010
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Publication #:
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Pub Dt:
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05/17/2012
| | | | |
Title:
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FORMING HEATERS FOR PHASE CHANGE MEMORIES
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|
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Patent #:
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Issue Dt:
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04/17/2012
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Application #:
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12944527
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Filing Dt:
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11/11/2010
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Publication #:
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Pub Dt:
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03/03/2011
| | | | |
Title:
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MEGASONIC CLEANING WITH CONTROLLED BOUNDARY LAYER THICKNESS AND ASSOCIATED SYSTEMS AND METHODS
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|
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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12944529
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Filing Dt:
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11/11/2010
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Publication #:
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Pub Dt:
|
03/10/2011
| | | | |
Title:
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SEMICONDUCTOR STRUCTURES INCLUDING DUAL FINS
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|
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Patent #:
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Issue Dt:
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11/27/2012
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Application #:
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12946592
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Filing Dt:
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11/15/2010
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Publication #:
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Pub Dt:
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03/10/2011
| | | | |
Title:
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STACKED DEVICE REMAPPING AND REPAIR
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|
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Patent #:
|
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Issue Dt:
|
10/11/2011
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Application #:
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12946596
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Filing Dt:
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11/15/2010
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Publication #:
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Pub Dt:
|
03/10/2011
| | | | |
Title:
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RESISTIVE MEMORY
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|
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Patent #:
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Issue Dt:
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01/28/2014
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Application #:
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12946620
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Filing Dt:
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11/15/2010
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Publication #:
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Pub Dt:
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03/24/2011
| | | | |
Title:
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CAPACITORS AND METHODS WITH PRASEODYMIUM OXIDE INSULATORS
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|
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Patent #:
|
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Issue Dt:
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11/12/2013
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Application #:
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12947771
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Filing Dt:
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11/16/2010
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Publication #:
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Pub Dt:
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05/17/2012
| | | | |
Title:
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METHOD AND APPARATUS TO PERFORM CONCURRENT READ AND WRITE MEMORY OPERATIONS
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|
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Patent #:
|
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Issue Dt:
|
02/04/2014
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Application #:
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12947781
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Filing Dt:
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11/16/2010
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Publication #:
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Pub Dt:
|
05/17/2012
| | | | |
Title:
|
INTERRUPTION OF WRITE MEMORY OPERATIONS TO PROVIDE FASTER READ ACCESS IN A SERIAL INTERFACE MEMORY
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|
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Patent #:
|
|
Issue Dt:
|
12/23/2014
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Application #:
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12947785
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Filing Dt:
|
11/16/2010
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Publication #:
|
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Pub Dt:
|
05/17/2012
| | | | |
Title:
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MULTI-INTERFACE MEMORY WITH ACCESS CONTROL
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|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
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Application #:
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12948469
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Filing Dt:
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11/17/2010
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Publication #:
|
|
Pub Dt:
|
03/10/2011
| | | | |
Title:
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SENSING MEMORY CELLS
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|
|
Patent #:
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NONE
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Issue Dt:
|
|
Application #:
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12948655
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Filing Dt:
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11/17/2010
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Publication #:
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Pub Dt:
|
03/17/2011
| | | | |
Title:
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STRUCTURE AND METHOD FOR COUPLING SIGNALS TO AND/OR FROM STACKED SEMICONDUCTOR DIES
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|
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Patent #:
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Issue Dt:
|
07/08/2014
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Application #:
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12948897
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Filing Dt:
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11/18/2010
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Publication #:
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Pub Dt:
|
05/24/2012
| | | | |
Title:
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Filling Cavities in Semiconductor Structures Having Adhesion Promoting Layer in the Cavities
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|
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Patent #:
|
|
Issue Dt:
|
02/26/2013
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Application #:
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12948952
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Filing Dt:
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11/18/2010
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Publication #:
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Pub Dt:
|
03/17/2011
| | | | |
Title:
|
MEMORY ADAPTED TO PROGRAM A NUMBER OF BITS TO A MEMORY CELL AND READ A DIFFERENT NUMBER OF BITS FROM THE MEMORY CELL
|
|
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Patent #:
|
|
Issue Dt:
|
10/01/2013
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Application #:
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12949117
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Filing Dt:
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11/18/2010
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Publication #:
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Pub Dt:
|
11/10/2011
| | | | |
Title:
|
ROBOT ARM FOR DELIVERING A WAFER AND WAFER-OPERATING MACHINE
|
|
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Patent #:
|
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Issue Dt:
|
02/28/2012
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Application #:
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12949347
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Filing Dt:
|
11/18/2010
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Publication #:
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Pub Dt:
|
03/17/2011
| | | | |
Title:
|
FRACTIONAL BITS IN MEMORY CELLS
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|
|
Patent #:
|
|
Issue Dt:
|
06/19/2012
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Application #:
|
12949558
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Filing Dt:
|
11/18/2010
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Publication #:
|
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Pub Dt:
|
03/17/2011
| | | | |
Title:
|
DEVICE HAVING COMPLEX OXIDE NANODOTS
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|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
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Application #:
|
12949728
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Filing Dt:
|
11/18/2010
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Publication #:
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Pub Dt:
|
05/24/2012
| | | | |
Title:
|
MEMORY INSTRUCTION INCLUDING PARAMETER TO AFFECT OPERATING CONDITION OF MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
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Application #:
|
12949844
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Filing Dt:
|
11/19/2010
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Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
PHASE CHANGE MEMORY STRUCTURE WITH MULTIPLE RESISTANCE STATES AND METHODS OF PROGRAMMING AND SENSING SAME
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|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
12949876
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Filing Dt:
|
11/19/2010
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Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
PROGRAM VERIFY OPERATION IN A MEMORY DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
01/24/2012
|
Application #:
|
12950088
|
Filing Dt:
|
11/19/2010
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Publication #:
|
|
Pub Dt:
|
05/26/2011
| | | | |
Title:
|
MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES
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|
|
Patent #:
|
|
Issue Dt:
|
11/22/2011
|
Application #:
|
12950459
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Filing Dt:
|
11/19/2010
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Publication #:
|
|
Pub Dt:
|
04/14/2011
| | | | |
Title:
|
METHODS OF FORMING NON-VOLATILE MEMORY STRUCTURE WITH CRESTED BARRIER TUNNEL LAYER
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|
|
Patent #:
|
|
Issue Dt:
|
09/18/2012
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Application #:
|
12950654
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Filing Dt:
|
11/19/2010
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Publication #:
|
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Pub Dt:
|
03/17/2011
| | | | |
Title:
|
STACKED DIE PACKAGE FOR PERIPHERAL AND CENTER DEVICE PAD LAYOUT DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
12950761
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Filing Dt:
|
11/19/2010
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Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
VERTICALLY STACKED FIN TRANSISTORS AND METHODS OF FABRICATING AND OPERATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
12950774
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Filing Dt:
|
11/19/2010
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Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
METHOD OF FABRICATING A FINFET HAVING CROSS-HAIR CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2017
|
Application #:
|
12950787
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Filing Dt:
|
11/19/2010
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Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
DOUBLE GATED FIN TRANSISTORS AND METHODS OF FABRICATING AND OPERATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
12950797
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Filing Dt:
|
11/19/2010
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
DOUBLE GATED 4F2 DRAM CHC CELL AND METHODS OF FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
12951196
|
Filing Dt:
|
11/22/2010
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
METHODS OF FORMING INTERMEDIATE SEMICONDUCTOR DEVICE STRUCTURES USING SPIN-ON, PHOTOPATTERNABLE, INTERLAYER DIELECTRIC MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
|
Application #:
|
12951461
|
Filing Dt:
|
11/22/2010
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
TRENCH MEMORY STRUCTURE OPERATION
|
|