|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
12951583
|
Filing Dt:
|
11/22/2010
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
NON-VOLATILE MEMORY DEVICE ADAPTED TO IDENTIFY ITSELF AS A BOOT MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
12952240
|
Filing Dt:
|
11/23/2010
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
FORMING THREE DIMENSIONAL ISOLATION STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
|
Application #:
|
12953776
|
Filing Dt:
|
11/24/2010
|
Publication #:
|
|
Pub Dt:
|
03/24/2011
| | | | |
Title:
|
DIODES, AND METHODS OF FORMING DIODES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2016
|
Application #:
|
12954344
|
Filing Dt:
|
11/24/2010
|
Publication #:
|
|
Pub Dt:
|
03/24/2011
| | | | |
Title:
|
Unsymmetrical Ligand Sources, Reduced Symmetry Metal-Containing Compounds, and Systems and Methods Including Same
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
12955359
|
Filing Dt:
|
11/29/2010
|
Publication #:
|
|
Pub Dt:
|
03/31/2011
| | | | |
Title:
|
METHOD OF FORMING VIAS IN SEMICONDUCTOR SUBSTRATES AND RESULTING STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
12955419
|
Filing Dt:
|
11/29/2010
|
Publication #:
|
|
Pub Dt:
|
03/24/2011
| | | | |
Title:
|
SENSING AGAINST A REFERENCE CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
12955448
|
Filing Dt:
|
11/29/2010
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
MEMORY DEVICES HAVING SELECT GATES WITH P TYPE BODIES, MEMORY STRINGS HAVING SEPARATE SOURCE LINES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2019
|
Application #:
|
12955494
|
Filing Dt:
|
11/29/2010
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
CROSS-POINT MEMORY WITH SELF-DEFINED MEMORY ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
12955635
|
Filing Dt:
|
11/29/2010
|
Publication #:
|
|
Pub Dt:
|
06/02/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING ANALOG CIRCUIT AND DIGITAL CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2012
|
Application #:
|
12955666
|
Filing Dt:
|
11/29/2010
|
Publication #:
|
|
Pub Dt:
|
03/24/2011
| | | | |
Title:
|
MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2011
|
Application #:
|
12955780
|
Filing Dt:
|
11/29/2010
|
Publication #:
|
|
Pub Dt:
|
03/24/2011
| | | | |
Title:
|
COMMUNICATION METHODS, METHODS OF FORMING AN INTERCONNECT, SIGNAL INTERCONNECTS, INTEGRATED CIRCUIT STRUCTURES, CIRCUITS, AND DATA APPARATUSES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2011
|
Application #:
|
12956570
|
Filing Dt:
|
11/30/2010
|
Publication #:
|
|
Pub Dt:
|
03/24/2011
| | | | |
Title:
|
METHODS OF FORMING AND OPERATING BACK-SIDE TRAP NON-VOLATILE MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
12956660
|
Filing Dt:
|
11/30/2010
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
CODE PATCHING FOR NON-VOLATILE MEMORY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12956742
|
Filing Dt:
|
11/30/2010
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
RELIABLE WRITE FOR NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12956791
|
Filing Dt:
|
11/30/2010
|
Publication #:
|
|
Pub Dt:
|
03/24/2011
| | | | |
Title:
|
SYSTEM AND METHOD FOR CONTROLLING TIMING OF OUTPUT SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
12956853
|
Filing Dt:
|
11/30/2010
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
VERIFY OR READ PULSE FOR PHASE CHANGE MEMORY AND SWITCH
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2013
|
Application #:
|
12956977
|
Filing Dt:
|
11/30/2010
|
Publication #:
|
|
Pub Dt:
|
03/24/2011
| | | | |
Title:
|
DATA PATH FOR MULTI-LEVEL CELL MEMORY, METHODS FOR STORING AND METHODS FOR UTILIZING A MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2012
|
Application #:
|
12957081
|
Filing Dt:
|
11/30/2010
|
Publication #:
|
|
Pub Dt:
|
03/24/2011
| | | | |
Title:
|
USB DEVICE COMMUNICATION APPARATUS, SYSTEMS, AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
|
Application #:
|
12957286
|
Filing Dt:
|
11/30/2010
|
Publication #:
|
|
Pub Dt:
|
06/02/2011
| | | | |
Title:
|
MEMORY INCLUDING A SELECTOR SWITCH ON A VARIABLE RESISTANCE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2017
|
Application #:
|
12957364
|
Filing Dt:
|
11/30/2010
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
PRESERVING DATA INTEGRITY IN A MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
12958259
|
Filing Dt:
|
12/01/2010
|
Publication #:
|
|
Pub Dt:
|
03/31/2011
| | | | |
Title:
|
ON-DIE SYSTEM AND METHOD FOR CONTROLLING TERMINATION IMPEDANCE OF MEMORY DEVICE DATA BUS TERMINALS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
12958974
|
Filing Dt:
|
12/02/2010
|
Publication #:
|
|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
ASSEMBLIES INCLUDING HEAT SINK ELEMENTS AND METHODS OF ASSEMBLING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2016
|
Application #:
|
12959015
|
Filing Dt:
|
12/02/2010
|
Publication #:
|
|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
Array Of Nonvolatile Memory Cells Having At Least Five Memory Cells Per Unit Cell, Having A Plurality Of Unit Cells Which Individually Comprise Three Elevational Regions Of Programmable Material, And/Or Having A Continuous Volume Having A combination Of A Plurality Of Vertically Oriented Memory Cells And A Plurality Of Horizontally Oriented Memory Cells; Array Of Vertically Stacked Tiers Of Nonvolatile Memory Cells
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
12959678
|
Filing Dt:
|
12/03/2010
|
Publication #:
|
|
Pub Dt:
|
03/24/2011
| | | | |
Title:
|
SEMICONDUCTOR PROCESSING METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
12960204
|
Filing Dt:
|
12/03/2010
|
Publication #:
|
|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
TRANSACTION LOG RECOVERY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2011
|
Application #:
|
12960260
|
Filing Dt:
|
12/03/2010
|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
Title:
|
MEMORY CELL PROGRAMMING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2012
|
Application #:
|
12960291
|
Filing Dt:
|
12/03/2010
|
Publication #:
|
|
Pub Dt:
|
03/31/2011
| | | | |
Title:
|
MEMORY DEVICE BIT LINE SENSING SYSTEM AND METHOD THAT COMPENSATES FOR BIT LINE RESISTANCE VARIATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12960301
|
Filing Dt:
|
12/03/2010
|
Publication #:
|
|
Pub Dt:
|
03/31/2011
| | | | |
Title:
|
SYMMETRICALLY OPERATING SINGLE-ENDED INPUT BUFFER DEVICES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2015
|
Application #:
|
12960308
|
Filing Dt:
|
12/03/2010
|
Publication #:
|
|
Pub Dt:
|
03/31/2011
| | | | |
Title:
|
CONSTANT DELAY ZERO STANDBY DIFFERENTIAL LOGIC RECEIVER AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2011
|
Application #:
|
12960862
|
Filing Dt:
|
12/06/2010
|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
Title:
|
METHODS OF FABRICATING AN ACCESS TRANSISTOR HAVING A POLYSILICON-COMPRISING PLUG ON INDIVIDUAL OF OPPOSING SIDES OF GATE MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
12961262
|
Filing Dt:
|
12/06/2010
|
Publication #:
|
|
Pub Dt:
|
03/31/2011
| | | | |
Title:
|
HIGH SPEED RING/BUS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
12961291
|
Filing Dt:
|
12/06/2010
|
Publication #:
|
|
Pub Dt:
|
03/31/2011
| | | | |
Title:
|
MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2012
|
Application #:
|
12961307
|
Filing Dt:
|
12/06/2010
|
Publication #:
|
|
Pub Dt:
|
03/31/2011
| | | | |
Title:
|
TRANSMITTER APPARATUS, SYSTEMS, AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2012
|
Application #:
|
12961370
|
Filing Dt:
|
12/06/2010
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
EPITAXIAL FORMATION SUPPORT STRUCTURES AND ASSOCIATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
12965225
|
Filing Dt:
|
12/10/2010
|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
Title:
|
METHODS OF REDUCING DEFECT FORMATION ON SILICON DIOXIDE FORMED BY ATOMIC LAYER DEPOSITION (ALD) PROCESSES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12965301
|
Filing Dt:
|
12/10/2010
|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
Title:
|
MICROFEATURE WORKPIECES AND METHODS FOR FORMING INTERCONNECTS IN MICROFEATURE WORKPIECES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2013
|
Application #:
|
12965322
|
Filing Dt:
|
12/10/2010
|
Publication #:
|
|
Pub Dt:
|
05/19/2011
| | | | |
Title:
|
ACTIVE PIXEL SENSOR WITH MIXED ANALOG AND DIGITAL SIGNAL INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
12966430
|
Filing Dt:
|
12/13/2010
|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
Title:
|
METHOD FOR ERASING A SEMICONDUCTOR MAGNETIC MEMORY INTEGRATING A MAGNETIC TUNNELING JUNCTION ABOVE A FLOATING-GATE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
12966582
|
Filing Dt:
|
12/13/2010
|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
Title:
|
MEMORY HAVING A VERTICAL ACCESS DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
12967733
|
Filing Dt:
|
12/14/2010
|
Publication #:
|
|
Pub Dt:
|
06/21/2012
| | | | |
Title:
|
APPARATUSES AND DEVICES FOR ABSORBING ELECTROMAGNETIC RADIATION, AND METHODS OF FORMING THE APPARATUSES AND DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
12968512
|
Filing Dt:
|
12/15/2010
|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
Title:
|
REMOVABLE STORAGE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
12968529
|
Filing Dt:
|
12/15/2010
|
Publication #:
|
|
Pub Dt:
|
04/07/2011
| | | | |
Title:
|
DYNAMICALLY CONFIGURABLE MLC STATE ASSIGNMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
12968714
|
Filing Dt:
|
12/15/2010
|
Publication #:
|
|
Pub Dt:
|
06/21/2012
| | | | |
Title:
|
METHODS FOR SEGMENTED PROGRAMMING AND MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
12968747
|
Filing Dt:
|
12/15/2010
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2013
|
Application #:
|
12969418
|
Filing Dt:
|
12/15/2010
|
Publication #:
|
|
Pub Dt:
|
04/14/2011
| | | | |
Title:
|
Methods of Forming Field Effect Transistors on Substrates
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
|
Application #:
|
12970086
|
Filing Dt:
|
12/16/2010
|
Publication #:
|
|
Pub Dt:
|
06/21/2012
| | | | |
Title:
|
PHASE INTERPOLATORS AND PUSH-PULL BUFFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
12970694
|
Filing Dt:
|
12/16/2010
|
Publication #:
|
|
Pub Dt:
|
04/14/2011
| | | | |
Title:
|
METHODS OF MANUFACTURING A HYBRID ELECTRICAL CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
12970726
|
Filing Dt:
|
12/16/2010
|
Publication #:
|
|
Pub Dt:
|
06/21/2012
| | | | |
Title:
|
SOLID STATE LIGHTING DEVICES WITH ACCESSIBLE ELECTRODES AND METHODS OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12971587
|
Filing Dt:
|
12/17/2010
|
Publication #:
|
|
Pub Dt:
|
04/21/2011
| | | | |
Title:
|
EXPANDED PROGRAMMING WINDOW FOR NON-VOLATILE MULTILEVEL MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
12972232
|
Filing Dt:
|
12/17/2010
|
Publication #:
|
|
Pub Dt:
|
04/14/2011
| | | | |
Title:
|
ADDITIONAL METAL ROUTING IN SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2012
|
Application #:
|
12973110
|
Filing Dt:
|
12/20/2010
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
Title:
|
PROGRAMMING A FLASH MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12973607
|
Filing Dt:
|
12/20/2010
|
Publication #:
|
|
Pub Dt:
|
04/14/2011
| | | | |
Title:
|
PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
12974939
|
Filing Dt:
|
12/21/2010
|
Publication #:
|
|
Pub Dt:
|
09/08/2011
| | | | |
Title:
|
TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE HAVING HIERARCHICAL BIT LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
12975494
|
Filing Dt:
|
12/22/2010
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
SINGLE CHECK MEMORY DEVICES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
12975761
|
Filing Dt:
|
12/22/2010
|
Publication #:
|
|
Pub Dt:
|
04/21/2011
| | | | |
Title:
|
BURIED DECOUPLING CAPACITORS, DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
12976454
|
Filing Dt:
|
12/22/2010
|
Publication #:
|
|
Pub Dt:
|
04/21/2011
| | | | |
Title:
|
REFRESH ALGORITHM FOR MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
12976712
|
Filing Dt:
|
12/22/2010
|
Publication #:
|
|
Pub Dt:
|
04/21/2011
| | | | |
Title:
|
PROGRAMMING MANAGEMENT DATA FOR A MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
12977969
|
Filing Dt:
|
12/23/2010
|
Publication #:
|
|
Pub Dt:
|
04/21/2011
| | | | |
Title:
|
TRANSISTOR GATE FORMING METHODS AND TRANSISTOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
12978722
|
Filing Dt:
|
12/27/2010
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
ARRAY ASSEMBLIES WITH HIGH VOLTAGE SOLID STATE LIGHTING DIES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
12979142
|
Filing Dt:
|
12/27/2010
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND LAYOUT DESIGN APPARATUS OF SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2013
|
Application #:
|
12979189
|
Filing Dt:
|
12/27/2010
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
METHODS OF FORMING A NONVOLATILE MEMORY CELL AND METHODS OF FORMING AN ARRAY OF NONVOLATILE MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2016
|
Application #:
|
12979461
|
Filing Dt:
|
12/28/2010
|
Publication #:
|
|
Pub Dt:
|
06/28/2012
| | | | |
Title:
|
PHASE CHANGE MEMORY DEVICE WITH VOLTAGE CONTROL ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
12980141
|
Filing Dt:
|
12/28/2010
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
DUAL RESISTANCE HEATER FOR PHASE CHANGE DEVICES AND MANUFACTURING METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
12980766
|
Filing Dt:
|
12/29/2010
|
Publication #:
|
|
Pub Dt:
|
08/18/2011
| | | | |
Title:
|
TECHNIQUES FOR CONTROLLING A SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2015
|
Application #:
|
12981330
|
Filing Dt:
|
12/29/2010
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
Title:
|
LOW-RESISTANCE INTERCONNECTS AND METHODS OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/01/2015
|
Application #:
|
12981330
|
Filing Dt:
|
12/29/2010
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
Title:
|
LOW-RESISTANCE INTERCONNECTS AND METHODS OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12981688
|
Filing Dt:
|
12/30/2010
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
Title:
|
MULTI LEVEL INHIBIT SCHEME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
|
Application #:
|
12981842
|
Filing Dt:
|
12/30/2010
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
Title:
|
MITIGATION OF RUNAWAY PROGRAMMING OF A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
12981892
|
Filing Dt:
|
12/30/2010
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
Title:
|
MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2012
|
Application #:
|
12982111
|
Filing Dt:
|
12/30/2010
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
Title:
|
SHARING PHYSICAL MEMORY LOCATIONS IN MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12982296
|
Filing Dt:
|
12/30/2010
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
Title:
|
STACKABLE SEMICONDUCTOR ASSEMBLIES AND METHODS OF MANUFACTURING SUCH ASSEMBLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
12982847
|
Filing Dt:
|
12/30/2010
|
Publication #:
|
|
Pub Dt:
|
07/05/2012
| | | | |
Title:
|
MEMORY DEVICE USING EXTENDED INTERFACE COMMANDS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2012
|
Application #:
|
12984370
|
Filing Dt:
|
01/04/2011
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
Title:
|
FRACTIONAL-RATE DECISION FEEDBACK EQUALIZATION USEFUL IN A DATA TRANSMISSION SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2012
|
Application #:
|
12984711
|
Filing Dt:
|
01/05/2011
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
Title:
|
SYSTEM, APPARATUS, AND METHOD FOR MODIFYING THE ORDER OF MEMORY ACCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
12985191
|
Filing Dt:
|
01/05/2011
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
TECHNIQUES FOR REFRESHING A SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
12985236
|
Filing Dt:
|
01/05/2011
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
Title:
|
MEMORY DEVICES HAVING REDUNDANT ARRAYS FOR REPAIR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
12985570
|
Filing Dt:
|
01/06/2011
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
Title:
|
METHODS FOR FABRICATING AND FILLING CONDUCTIVE VIAS AND CONDUCTIVE VIAS SO FORMED
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
12985787
|
Filing Dt:
|
01/06/2011
|
Publication #:
|
|
Pub Dt:
|
07/12/2012
| | | | |
Title:
|
MEMORY ADDRESS TRANSLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
12986280
|
Filing Dt:
|
01/07/2011
|
Publication #:
|
|
Pub Dt:
|
07/12/2012
| | | | |
Title:
|
RECURSIVE SUMMATION ALGORITHMS USEFUL FOR STATISTICAL SIGNAL ANALYSIS OF TRANSMISSION OF SIGNALS IN A COMPUTER SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
12986422
|
Filing Dt:
|
01/07/2011
|
Publication #:
|
|
Pub Dt:
|
05/05/2011
| | | | |
Title:
|
APPARATUS AND METHOD FOR ELIMINATING ARTIFACTS IN ACTIVE PIXEL SENSOR (APS) IMAGERS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12986487
|
Filing Dt:
|
01/07/2011
|
Publication #:
|
|
Pub Dt:
|
04/28/2011
| | | | |
Title:
|
SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12986663
|
Filing Dt:
|
01/07/2011
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM INCLUDING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
12986681
|
Filing Dt:
|
01/07/2011
|
Publication #:
|
|
Pub Dt:
|
07/21/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM INCLUDING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
12986770
|
Filing Dt:
|
01/07/2011
|
Publication #:
|
|
Pub Dt:
|
07/12/2012
| | | | |
Title:
|
SOLUTIONS FOR CLEANING SEMICONDUCTOR STRUCTURES AND RELATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
12986806
|
Filing Dt:
|
01/07/2011
|
Publication #:
|
|
Pub Dt:
|
07/12/2012
| | | | |
Title:
|
METHODS OF FORMING A PATTERNED, SILICON-ENRICHED DEVELOPABLE ANTIREFLECTIVE MATERIAL AND SEMICONDUCTOR DEVICE STRUCTURES INCLUDING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
12986836
|
Filing Dt:
|
01/07/2011
|
Publication #:
|
|
Pub Dt:
|
07/12/2012
| | | | |
Title:
|
IMAGING DEVICES, METHODS OF FORMING SAME, AND METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
12986947
|
Filing Dt:
|
01/07/2011
|
Publication #:
|
|
Pub Dt:
|
05/05/2011
| | | | |
Title:
|
SYSTEM AND METHOD FOR OPTIMIZING INTERCONNECTIONS OF COMPONENTS IN A MULTICHIP MEMORY MODULE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
12986973
|
Filing Dt:
|
01/07/2011
|
Publication #:
|
|
Pub Dt:
|
05/05/2011
| | | | |
Title:
|
DELAY LINES, METHODS FOR DELAYING A SIGNAL, AND DELAY LOCK LOOPS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
12987890
|
Filing Dt:
|
01/10/2011
|
Publication #:
|
|
Pub Dt:
|
05/05/2011
| | | | |
Title:
|
PACKAGED MICRODEVICES AND METHODS FOR MANUFACTURING PACKAGED MICRODEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
12992062
|
Filing Dt:
|
03/02/2011
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
Title:
|
REVERSING A POTENTIAL POLARITY FOR READING PHASE-CHANGE CELLS TO SHORTEN A RECOVERY DELAY AFTER PROGRAMMING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2011
|
Application #:
|
13004967
|
Filing Dt:
|
01/12/2011
|
Publication #:
|
|
Pub Dt:
|
05/12/2011
| | | | |
Title:
|
METHODS OF UTILIZING SILICON DIOXIDE-CONTAINING MASKING STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
13005291
|
Filing Dt:
|
01/12/2011
|
Publication #:
|
|
Pub Dt:
|
05/05/2011
| | | | |
Title:
|
M+N BIT PROGRAMMING AND M+L BIT READ FOR M BIT MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2012
|
Application #:
|
13005453
|
Filing Dt:
|
01/12/2011
|
Publication #:
|
|
Pub Dt:
|
05/05/2011
| | | | |
Title:
|
LOW VOLTAGE SENSING SCHEME HAVING REDUCED ACTIVE POWER DOWN STANDBY CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
13006111
|
Filing Dt:
|
01/13/2011
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
POWER SUPPLY INDUCED SIGNAL JITTER COMPENSATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13006240
|
Filing Dt:
|
01/13/2011
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
DETERMINING LOCATION OF ERROR DETECTION DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
13006762
|
Filing Dt:
|
01/14/2011
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
STRINGS OF MEMORY CELLS HAVING STRING SELECT GATES, MEMORY DEVICES INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
13007002
|
Filing Dt:
|
01/14/2011
|
Publication #:
|
|
Pub Dt:
|
05/12/2011
| | | | |
Title:
|
INTERCONNECT STRUCTURES FOR STACKED DIES, INCLUDING PENETRATING STRUCTURES FOR THROUGH-SILICON VIAS, AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2013
|
Application #:
|
13007274
|
Filing Dt:
|
01/14/2011
|
Publication #:
|
|
Pub Dt:
|
07/19/2012
| | | | |
Title:
|
METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
13007307
|
Filing Dt:
|
01/14/2011
|
Publication #:
|
|
Pub Dt:
|
05/12/2011
| | | | |
Title:
|
MULTI-PHASE DUTY-CYCLE CORRECTED CLOCK SIGNAL GENERATOR AND MEMORY HAVING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2011
|
Application #:
|
13007340
|
Filing Dt:
|
01/14/2011
|
Publication #:
|
|
Pub Dt:
|
05/12/2011
| | | | |
Title:
|
CONTROL VOLTAGE TRACKING CIRCUITS, METHODS FOR RECORDING A CONTROL VOLTAGE FOR A CLOCK SYNCHRONIZATION CIRCUIT AND METHODS FOR SETTING A VOLTAGE CONTROLLED DELAY
|
|