|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
|
Application #:
|
08937626
|
Filing Dt:
|
09/26/1997
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Title:
|
SYSTEM FOR EVALUATING AND REPORTING SEMICONDUCTOR TEST PROCESSES
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|
|
Patent #:
|
|
Issue Dt:
|
01/25/2000
|
Application #:
|
08937860
|
Filing Dt:
|
09/25/1997
|
Title:
|
SIMULATION "BUS CONTENTION" DETECTION
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|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08937874
|
Filing Dt:
|
09/29/1997
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Title:
|
METHOD AND APPARATUS EMPLOYING A DYNAMIC ENCRYPTION INTERFACE BETWEEN A PROCESSOR AND A MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08938491
|
Filing Dt:
|
09/30/1997
|
Title:
|
CIRCUIT AND METHOD FOR CONFIGURING AND REGISTERING A CRYPTOGRAPHIC DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/1999
|
Application #:
|
08939732
|
Filing Dt:
|
10/06/1997
|
Title:
|
CIRCUIT AND METHOD FOR AN OPEN BIT LINE MEMORY CELL WITH A VERTICAL TRANSISTOR AND TRENCH PLATE TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2000
|
Application #:
|
08939742
|
Filing Dt:
|
10/06/1997
|
Title:
|
CIRCUIT AND METHOD FOR A FOLDED BIT LINE MEMORY CELL WITH VERTICAL TRANSISTOR AND TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/1998
|
Application #:
|
08939982
|
Filing Dt:
|
09/29/1997
|
Title:
|
METHOD OF FORMING WAFER ALIGNMENT PATTERNS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/1999
|
Application #:
|
08940115
|
Filing Dt:
|
09/29/1997
|
Title:
|
NEADING CIRCUIT FOR SEMICONDUCTOR MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08940214
|
Filing Dt:
|
09/30/1997
|
Title:
|
ATTACHMENT OR INTEGRATION OF A BIOS DEVICE INTO A COMPUTER SYSTEM USING LOCAL BUS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
08940215
|
Filing Dt:
|
09/30/1997
|
Title:
|
METHOD FOR ATTACHMENT OR INTEGRATION OF A BIOS DEVICE INTO A COMPUTER SYSTEM USING A LOCAL BUS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08940278
|
Filing Dt:
|
09/30/1997
|
Title:
|
FLOATING GATE MOS TRANSISTOR CHARGE INJECTION CIRCUIT AND COMPUTATION DEVICES INCORPORATING IT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
08940306
|
Filing Dt:
|
09/30/1997
|
Title:
|
FLIP-CHIP ON LEADS DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/1998
|
Application #:
|
08940310
|
Filing Dt:
|
09/30/1997
|
Title:
|
METHOD AND APPARATUS FOR STRESS TESTING A SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2000
|
Application #:
|
08940587
|
Filing Dt:
|
09/30/1997
|
Title:
|
METHOD TO PERMIT HIGH TEMPERATURE ASSEMBLY PROCESSES FOR MAGNETICALLY SENSITIVE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
08940743
|
Filing Dt:
|
09/30/1997
|
Title:
|
METHOD FOR ATTACHMENT OF A BIOS DEVICE INTO A COMPUTER SYSTEM USING THE SYSTEM MEMORY DATA BUS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
08940845
|
Filing Dt:
|
09/30/1997
|
Title:
|
GRAPHICAL USER INTERFACE FOR MANAGING SECURITY IN A DATABASE SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2000
|
Application #:
|
08940856
|
Filing Dt:
|
09/29/1997
|
Title:
|
FLOATING GATE NON-VOLATILE MEMORY CELL WITH LOW ERASING VOLTAGE AND MANUFACTURING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
08941599
|
Filing Dt:
|
09/30/1997
|
Title:
|
MERGING DUMMY STRUCTURE REPRESENTATIONS FOR IMPROVED DISTRIBUTION OF ARTIFACTS IN A SEMICONDUCTOR LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
08941619
|
Filing Dt:
|
09/30/1997
|
Title:
|
ATTACHMENT OR INTEGRATION OF A BIOS DEVICE INTO A COMPUTER SYSTEM USING THE SYSTEM MEMORY DATA BUS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
08941663
|
Filing Dt:
|
09/30/1997
|
Title:
|
METHOD FOR ATTACHMENT OR INTERGATION OF A BIOS DEVICE INTO A COMPUTER SYSTEM USING THE SYSTEM MEMORY ADDRESS AND DATA BUS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
08941664
|
Filing Dt:
|
09/30/1997
|
Title:
|
METHOD FOR ATTACHMENT OR INTEGRATION OF A BIOS DEVICE INTO A COMPUTER SYSTEM USING THE SYSTEM MEMORY ADDRESS AND DATA BUS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/1999
|
Application #:
|
08941882
|
Filing Dt:
|
09/30/1997
|
Title:
|
METHOD AND CIRCUIT FOR CHECKING MULTILEVEL PROGRAMMING OF FLOATING-GATE NONVOLATILE MEMORY CELLS PARTICULARLY FLASH CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
08941995
|
Filing Dt:
|
10/01/1997
|
Title:
|
THREE BUS SERVER ARCHITECTURE WITH A LEGACY PCI BUS AND MIRRORED I/O PCI BUSES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2000
|
Application #:
|
08942811
|
Filing Dt:
|
10/02/1997
|
Title:
|
IMPROVED METAL FILL BY TREATMENT OF MOBILITY LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2000
|
Application #:
|
08942878
|
Filing Dt:
|
10/02/1997
|
Title:
|
SELF-TERMINATING ELECTRICAL SOCKET
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2000
|
Application #:
|
08943782
|
Filing Dt:
|
10/03/1997
|
Title:
|
SEMICONDUCTOR WIREBOND MACHINE LEADRAME THERMAL MAP SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
08944135
|
Filing Dt:
|
10/06/1997
|
Title:
|
CHEMICAL DISPENSING SYSTEM FOR SEMICONDUCTOR WAFER PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/1999
|
Application #:
|
08944255
|
Filing Dt:
|
10/06/1997
|
Title:
|
METHOD FOR ALLOWING DATA TRANSFERS WITH A MEMORY HAVING DEFECTIVE STORAGE LOCATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
08944312
|
Filing Dt:
|
10/06/1997
|
Title:
|
CIRCUIT AND METHOD FOR A FOLDED BIT LINE MEMORY USING TRENCH PLATE CAPACITOR CELLS WITH BODY BIAS CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
08944598
|
Filing Dt:
|
10/06/1997
|
Title:
|
METHOD AND APPARATUS FOR CAPACITIVELY TESTING A SEMICONDUCTOR DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
08944601
|
Filing Dt:
|
10/06/1997
|
Title:
|
METHOD FOR SEECTING, DETECTING AND/OR REPROGRAMMING SYSTEM BIOS IN A COMPUTER SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/1998
|
Application #:
|
08944649
|
Filing Dt:
|
10/06/1997
|
Title:
|
CLOCKED SENSE AMPLIFIER WITH WORDLINE TRACKING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08944684
|
Filing Dt:
|
09/30/1997
|
Title:
|
LASER MARKING TECHNIQUES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
08944743
|
Filing Dt:
|
10/06/1997
|
Title:
|
INCREASING THE GAP BETWEEN A LEAD FRAME AND A SEMICONDUCTOR DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
08946027
|
Filing Dt:
|
10/07/1997
|
Title:
|
A METHOD FOR STORING INFORMATION IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
08946034
|
Filing Dt:
|
10/07/1997
|
Title:
|
INTEGRATED CIRCUITRY AND METHOD OF FORMING A CONTACT LANDING PAD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
08946107
|
Filing Dt:
|
10/02/1997
|
Title:
|
INTEGRATED CIRCUIT CARTRIDGE EXTRACTING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
08946109
|
Filing Dt:
|
10/02/1997
|
Title:
|
INTEGRATED CIRCUIT CARTRIDGE EXTRACTING TOOL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/1998
|
Application #:
|
08946275
|
Filing Dt:
|
10/07/1997
|
Title:
|
CAPACITOR CONSTRUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08946331
|
Filing Dt:
|
10/07/1997
|
Title:
|
MOVING SEQUENTIAL SECTORS WITHIN A BLOCK OF INFORMATION IN A FLASH MEMORY MASS STORAGE ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08946462
|
Filing Dt:
|
10/07/1997
|
Title:
|
METHOD FOR REDUCING PHOTOLITHOGRAPHIC STEPS IN A SEMICONDUCTOR INTERCONNECT PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
08946626
|
Filing Dt:
|
10/07/1997
|
Title:
|
APPARATUS AND METHOD FOR REDUCING DAMAGE TO WAFER CUTTING BLADES DURING WAFER DICING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
08946727
|
Filing Dt:
|
10/08/1997
|
Title:
|
POSITIVE CHARGE PUMP
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
08947011
|
Filing Dt:
|
10/08/1997
|
Title:
|
COATED SEMICONDUCTOR DIE/LEADFRAME ASSEMBLY AND METHOD FOR COATING THE ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
08947061
|
Filing Dt:
|
10/08/1997
|
Title:
|
RAPID ANNEALING OF POWDER PHOSPHORS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08947559
|
Filing Dt:
|
10/09/1997
|
Title:
|
AMMONIUM HYDROXIDE ETCH OF PHOTORESIST MASKED GILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
08948120
|
Filing Dt:
|
10/09/1997
|
Title:
|
CHIP LEADS CONSTRAINED IN DIELECTRIC MEDIA
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2003
|
Application #:
|
08948179
|
Filing Dt:
|
10/09/1997
|
Title:
|
USE OF HEAVY HALOGENS FOR ENHANCED FACET ETCHING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
08948372
|
Filing Dt:
|
10/09/1997
|
Title:
|
METHODS OF FORMING INSULATING MATERIALS AND METHODS OF FORMING INSULATING MATERIALS AROUND A CONDUCTIVE COMPONENT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/1998
|
Application #:
|
08948386
|
Filing Dt:
|
10/10/1997
|
Title:
|
DIFFERENTIAL VOLTAGE REGULATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
08948712
|
Filing Dt:
|
10/10/1997
|
Title:
|
METHOD AND APPARATUS FOR COUPLING SIGNALS BETWEEN TWO CIRCUITS OPERATING IN DIFFERENT CLOCK DOMAINS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08948834
|
Filing Dt:
|
10/10/1997
|
Title:
|
REDUCED TERMINAL TESTING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08948889
|
Filing Dt:
|
10/10/1997
|
Title:
|
STATIC MEMORY CELL AND METHOD OF MANUFACTURING A STATIC MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08949072
|
Filing Dt:
|
10/10/1997
|
Title:
|
METHOD AND APPARATUS FOR IMPROVED COATING OF A SEMICONDUCTOR WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2000
|
Application #:
|
08949383
|
Filing Dt:
|
10/14/1997
|
Title:
|
TEMPORARY SEMICONDUCTOR PACKAGE HAVING DENSE ARRAY EXTERNAL CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08949419
|
Filing Dt:
|
10/14/1997
|
Title:
|
INTEGRATED CIRCUIT WITH VOLTAGE OVER-STRESS INDICATING CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
08949524
|
Filing Dt:
|
10/14/1997
|
Title:
|
MOUSE BUTTONS DESIGNED FOR IMPROVED AVAILABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2000
|
Application #:
|
08949997
|
Filing Dt:
|
10/14/1997
|
Title:
|
GRADED LDD IMPLANT PROCESS FOR SUB-HALF-MICRON MOS DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/1998
|
Application #:
|
08950012
|
Filing Dt:
|
10/14/1997
|
Title:
|
PROGRAMMABLE DEVICE FOR REDUNDANT ELEMENT CANCEL IN A MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1999
|
Application #:
|
08950549
|
Filing Dt:
|
10/15/1997
|
Title:
|
APPARATUS TO INCREASE GAS RESIDENCE TIME IN A REACTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
08950938
|
Filing Dt:
|
10/15/1997
|
Title:
|
METHOD AND APPARATUS FOR GENERATING A REMOTE PRINTABLE REPORT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
08951176
|
Filing Dt:
|
10/15/1997
|
Title:
|
METHODS OF TREATING A SEMICONDUCTOR WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
08951709
|
Filing Dt:
|
10/16/1997
|
Title:
|
SYNCHRONOUS SRAM HAVING GLOBAL WRITE ENABLE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
08951903
|
Filing Dt:
|
10/16/1997
|
Title:
|
METHOD AND APPARATUS FOR MANAGING TRAINING ACTIVITIES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
08951993
|
Filing Dt:
|
10/16/1997
|
Title:
|
INTER-MODULE DATA MANAGEMENT METHODOLOGY FOR CIRCUIT SYNTHESIS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08954222
|
Filing Dt:
|
10/20/1997
|
Title:
|
A METHOD FOR VIEWING AND PROVIDING TO A USER PARAMETER-SPECIFIC INFORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2000
|
Application #:
|
08954407
|
Filing Dt:
|
10/20/1997
|
Title:
|
SYSTEM FOR PROVIDING A USER WITH PARAMETER-SPECIFIC INFORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/1999
|
Application #:
|
08954450
|
Filing Dt:
|
10/20/1997
|
Title:
|
METHOD OF FORMING A SUPPORT STRUCTURE FOR AIR BRIDGE WIRING OF AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08954933
|
Filing Dt:
|
10/21/1997
|
Title:
|
METHOD AND APPARATUS FOR FAST RESET OF A ONE-SHOT CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/1998
|
Application #:
|
08954970
|
Filing Dt:
|
10/20/1997
|
Title:
|
METHOD OF FORMING A RESISTOR AND INTEGRATED CIRCUITRY HAVING A RESISTOR CONSTRUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
08955220
|
Filing Dt:
|
10/21/1997
|
Title:
|
METHOD OF LASER ABLATION OF SEMICONDUCTOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
08955517
|
Filing Dt:
|
10/21/1997
|
Title:
|
METHOD FOR FABRICATING A COBALT SILICIDE OXIDE METALIZATION STRUCTURE ON A SEMICONDUCTOR SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
08955793
|
Filing Dt:
|
10/22/1997
|
Title:
|
SILICON NITRIDE DEPOSITION METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
08956095
|
Filing Dt:
|
10/23/1997
|
Title:
|
METHOD AND APPARATUS FOR TESTING OF DIELECTRIC DEFECTS IN A PACKAGED SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
08956142
|
Filing Dt:
|
10/22/1997
|
Title:
|
SILICON NITRIDE DEPOSITION METHOD FOR USE IN FORMING A MEMORY CELL DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/1999
|
Application #:
|
08956143
|
Filing Dt:
|
10/22/1997
|
Title:
|
APPARATUS FOR PACKAGING FLIP CHIP BARE DIE ON PRINTED CIRCUIT BOARDS ON PRINTED CIRCUIT BOARDS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
08956180
|
Filing Dt:
|
10/22/1997
|
Title:
|
METHOD AND SYSTEM FOR TRACKING EMPLOYEE PRODUCTIVITY VIA ELECTRONIC MAIL
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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08956759
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Filing Dt:
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10/22/1997
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Title:
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ARCHITECTURE FOR STATE MACHINE FOR CONTROLLING INTERNAL OPERATIONS OF FLASH MEMORY
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Patent #:
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Issue Dt:
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02/09/1999
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Application #:
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08957666
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Filing Dt:
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10/24/1997
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Title:
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MEMORY WITH IMPROVED READING TIME
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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08957685
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Filing Dt:
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10/24/1997
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Title:
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CIRCUIT FOR SELECTIVELY ENABLING ONE AMONG A PLURALITY OF CIRCUIT ALTERNATIVES OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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04/11/2000
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Application #:
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08957715
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Filing Dt:
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10/24/1997
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Title:
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ELECTRICALLY MODIFIABLE MULTILEVEL NON-VOLATILE MEMORY COMPRISING INTERNAL REFRESH MEANS
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Patent #:
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Issue Dt:
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04/06/1999
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Application #:
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08957888
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Filing Dt:
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10/27/1997
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Title:
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SEMICONDUCTOR MEMORY WITH TEST CIRCUIT
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Patent #:
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Issue Dt:
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07/20/1999
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Application #:
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08958023
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Filing Dt:
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10/27/1997
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Title:
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GRADED ANTI-REFLECTIVE COATING FOR IC LITHOGRAPHY
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Patent #:
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Issue Dt:
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08/03/1999
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Application #:
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08958275
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Filing Dt:
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10/27/1997
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Title:
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METHOD FOR COUNTING PARTS
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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08958290
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Filing Dt:
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10/27/1997
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Title:
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UNDOPED SILICON DIOXIDE AS ETCH MASK FOR PATTERNING OF DOPED SILICON DIOXIDE
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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08958298
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Filing Dt:
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10/27/1997
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Title:
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PARTS COUNTING APPARATUS
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Patent #:
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Issue Dt:
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08/17/1999
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Application #:
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08958553
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Filing Dt:
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10/29/1997
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Title:
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METHOD FOR COUNTING PARTS IN A TRAY
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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08959231
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Filing Dt:
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10/28/1997
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Title:
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SYSTEM FOR IDENTIFYING A COMPONENT WITH PHYSICAL CHARACTERIZATION
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Patent #:
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Issue Dt:
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01/05/1999
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Application #:
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08959238
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Filing Dt:
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10/28/1997
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Title:
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SECOND IMPLANTED MATRIX FOR AGGLOMERATION CONTROL AND THERMAL STABILITY
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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08959239
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Filing Dt:
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10/28/1997
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Title:
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METHOD FOR IDENTIFYING A COMPONENT WITH PHYSICAL CHARACTERIZATION
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Patent #:
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Issue Dt:
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08/17/1999
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Application #:
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08959698
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Filing Dt:
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10/29/1997
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Title:
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APPARATUS FOR COUNTING PARTS IN A TRAY
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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08960494
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Filing Dt:
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10/29/1997
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Publication #:
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Pub Dt:
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03/21/2002
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Title:
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LOW RESISTANCE CONTACTS FABRICATED IN HIGH ASPECT RATIO OPENINGS BY RESPUTTERING
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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08960644
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Filing Dt:
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10/30/1997
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Title:
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METHOD AND CIRCUIT FOR RAPIDLY EQUILIBRATING PAIRED DIGIT LINES OF A MEMORY DEVICE DURING TESTING
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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08960776
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Filing Dt:
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10/30/1997
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Title:
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METHOD FOR SYNCHRONIZING DATA WITH A BI-DIRECTIONAL BUFFER
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Patent #:
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Issue Dt:
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04/25/2000
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Application #:
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08960777
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Filing Dt:
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10/30/1997
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Title:
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BI-DIRECTIONAL SYNCHRONIZING BUFFER SYSTEM
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Patent #:
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Issue Dt:
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07/25/2000
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Application #:
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08960854
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Filing Dt:
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10/30/1997
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Title:
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METHOD AND APPARATUS FOR ENABLING ACCESS TO COMPUTER SYSTEM RESOURCES
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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08960926
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Filing Dt:
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10/30/1997
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Title:
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SELF-REGULATED EQUALIZER, PARTICULARLY FOR SENSE AMPLIFIERS
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08960946
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Filing Dt:
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10/30/1997
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Title:
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METHOD FOR INDICATING POWER-CONSUMPTION STATUS
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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08961341
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Filing Dt:
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10/30/1997
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Title:
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INPUT/OUTPUT ELECTROSTATIC DISCHARGE PROTECTION FOR DEVICES WITH MULTIPLE INDIVIDUAL POWER GROUPS
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Patent #:
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Issue Dt:
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10/19/1999
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Application #:
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08961350
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Filing Dt:
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10/30/1997
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Title:
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METHOD FOR FABRICATING LITHOGRAPHIC STENCIL MASKS
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