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Reel/Frame:	036550/0001			Pages:	983
		Recorded:	09/03/2015
Attorney Dkt #:	3718.266
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14793
Page 145 of 148
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Patent #:	9332384	Issue Dt:	05/03/2016	Application #:	14503878	Filing Dt:	10/01/2014
Publication #:	US20150099535	Pub Dt:	04/09/2015
Title:	OBTAINING A GEOGRAPHICAL POSITION OF A MOBILE DEVICE

Patent #:	NONE	Issue Dt:		Application #:	14504122	Filing Dt:	10/01/2014
Publication #:	US20150110119	Pub Dt:	04/23/2015
Title:	VIRTUAL GATEWAY FOR MACHINE TO MACHINE CAPILLARY NETWORK

Patent #:	9405596	Issue Dt:	08/02/2016	Application #:	14504832	Filing Dt:	10/02/2014
Publication #:	US20150113229	Pub Dt:	04/23/2015
Title:	CODE VERSIONING FOR ENABLING TRANSACTIONAL MEMORY PROMOTION

Patent #:	9171844	Issue Dt:	10/27/2015	Application #:	14504997	Filing Dt:	10/02/2014
Publication #:	US20150014782	Pub Dt:	01/15/2015
Title:	GATE STRUCTURES AND METHODS OF MANUFACTURE

Patent #:	9406790	Issue Dt:	08/02/2016	Application #:	14505018	Filing Dt:	10/02/2014
Publication #:	US20150053913	Pub Dt:	02/26/2015
Title:	SUSPENDED RING-SHAPED NANOWIRE STRUCTURE

Patent #:	9490202	Issue Dt:	11/08/2016	Application #:	14505087	Filing Dt:	10/02/2014
Publication #:	US20150054122	Pub Dt:	02/26/2015
Title:	SELF-ALIGNED AIRGAP INTERCONNECT STRUCTURES

Patent #:	10008597	Issue Dt:	06/26/2018	Application #:	14505536	Filing Dt:	10/03/2014
Publication #:	US20150054094	Pub Dt:	02/26/2015
Title:	SEMICONDUCTOR DEVICES WITH ASYMMETRIC HALO IMPLANTATION AND METHOD OF MANUFACTURE

Patent #:	9418234	Issue Dt:	08/16/2016	Application #:	14505734	Filing Dt:	10/03/2014
Publication #:	US20150106952	Pub Dt:	04/16/2015
Title:	PROVIDING ISOLATED ENTROPY ELEMENTS

Patent #:	9582388	Issue Dt:	02/28/2017	Application #:	14506331	Filing Dt:	10/03/2014
Publication #:	US20160098332	Pub Dt:	04/07/2016
Title:	DYNAMIC MULTI-PURPOSE EXTERNAL ACCESS POINTS CONNECTED TO CORE INTERFACES WITHIN A SYSTEM ON CHIP (SOC)

Patent #:	9269435	Issue Dt:	02/23/2016	Application #:	14507144	Filing Dt:	10/06/2014
Publication #:	US20150023094	Pub Dt:	01/22/2015
Title:	DRIFT MITIGATION FOR MULTI-BITS PHASE CHANGE MEMORY

Patent #:	9524244	Issue Dt:	12/20/2016	Application #:	14507234	Filing Dt:	10/06/2014
Publication #:	US20150121008	Pub Dt:	04/30/2015
Title:	WRITE CACHE DESTAGING

Patent #:	NONE	Issue Dt:		Application #:	14507242	Filing Dt:	10/06/2014
Publication #:	US20150162446	Pub Dt:	06/11/2015
Title:	CMOS DEVICES WITH STRESSED CHANNEL REGIONS, AND METHODS FOR FABRICATING THE SAME

Patent #:	9076810	Issue Dt:	07/07/2015	Application #:	14508011	Filing Dt:	10/07/2014
Publication #:	US20150024570	Pub Dt:	01/22/2015
Title:	SCALING OF BIPOLAR TRANSISTORS

Patent #:	9059173	Issue Dt:	06/16/2015	Application #:	14508471	Filing Dt:	10/07/2014
Publication #:	US20150021736	Pub Dt:	01/22/2015
Title:	ELECTRONIC FUSE LINE WITH MODIFIED CAP

Patent #:	9224797	Issue Dt:	12/29/2015	Application #:	14508644	Filing Dt:	10/07/2014
Publication #:	US20150021737	Pub Dt:	01/22/2015
Title:	METAL-INSULATOR-METAL (MIM) CAPACITOR WITH DEEP TRENCH (DT) STRUCTURE AND METHOD IN A SILICON-ON-INSULATOR (SOI)

Patent #:	9595943	Issue Dt:	03/14/2017	Application #:	14509242	Filing Dt:	10/08/2014
Publication #:	US20160105161	Pub Dt:	04/14/2016
Title:	IMPLEMENTING BROADBAND RESONATOR FOR RESONANT CLOCK DISTRIBUTION

Patent #:	9373697	Issue Dt:	06/21/2016	Application #:	14509392	Filing Dt:	10/08/2014
Publication #:	US20150024568	Pub Dt:	01/22/2015
Title:	SPACER REPLACEMENT FOR REPLACEMENT METAL GATE SEMICONDUCTOR DEVICES

Patent #:	9140669	Issue Dt:	09/22/2015	Application #:	14510309	Filing Dt:	10/09/2014
Publication #:	US20150021605	Pub Dt:	01/22/2015
Title:	MAPPING DENSITY AND TEMPERATURE OF A CHIP, IN SITU

Patent #:	NONE	Issue Dt:		Application #:	14510381	Filing Dt:	10/09/2014
Publication #:	US20150024989	Pub Dt:	01/22/2015
Title:	CLEANING COMPOSITION AND PROCESS FOR CLEANING SEMICONDUCTOR DEVICES AND/OR TOOLING DURING MANUFACTURING THEREOF

Patent #:	NONE	Issue Dt:		Application #:	14510426	Filing Dt:	10/09/2014
Publication #:	US20150037971	Pub Dt:	02/05/2015
Title:	CHIP CONNECTION STRUCTURE AND METHOD OF FORMING

Patent #:	9230929	Issue Dt:	01/05/2016	Application #:	14511259	Filing Dt:	10/10/2014
Publication #:	US20150021793	Pub Dt:	01/22/2015
Title:	SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE

Patent #:	NONE	Issue Dt:		Application #:	14512404	Filing Dt:	10/11/2014
Publication #:	US20150032285	Pub Dt:	01/29/2015
Title:	Cooling System Management

Patent #:	NONE	Issue Dt:		Application #:	14512554	Filing Dt:	10/13/2014
Publication #:	US20160105179	Pub Dt:	04/14/2016
Title:	LEVEL SHIFTING AN I/O SIGNAL INTO MULTIPLE VOLTAGE DOMAINS

Patent #:	9473141	Issue Dt:	10/18/2016	Application #:	14512626	Filing Dt:	10/13/2014
Publication #:	US20160105180	Pub Dt:	04/14/2016
Title:	RECEIVING AN I/O SIGNAL IN MULTIPLE VOLTAGE DOMAINS

Patent #:	NONE	Issue Dt:		Application #:	14512718	Filing Dt:	10/13/2014
Publication #:	US20150031201	Pub Dt:	01/29/2015
Title:	TRENCH PATTERNING WITH BLOCK FIRST SIDEWALL IMAGE TRANSFER

Patent #:	9236398	Issue Dt:	01/12/2016	Application #:	14513709	Filing Dt:	10/14/2014
Publication #:	US20150054027	Pub Dt:	02/26/2015
Title:	PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES

Patent #:	9418995	Issue Dt:	08/16/2016	Application #:	14513725	Filing Dt:	10/14/2014
Publication #:	US20160104707	Pub Dt:	04/14/2016
Title:	METHOD AND STRUCTURE FOR TRANSISTORS USING GATE STACK DOPANTS WITH MINIMAL NITROGEN PENETRATION

Patent #:	9294329	Issue Dt:	03/22/2016	Application #:	14514592	Filing Dt:	10/15/2014
Publication #:	US20150110218	Pub Dt:	04/23/2015
Title:	EMPHASIZED SIGNAL POINT ARRANGEMENT OPERATION FOR COMPENSATING DC IMBALANCE

Patent #:	9252080	Issue Dt:	02/02/2016	Application #:	14514640	Filing Dt:	10/15/2014
Title:	DIELECTRIC COVER FOR A THROUGH SILICON VIA

Patent #:	9312274	Issue Dt:	04/12/2016	Application #:	14514900	Filing Dt:	10/15/2014
Publication #:	US20160111447	Pub Dt:	04/21/2016
Title:	MERGED FIN STRUCTURES FOR FINFET DEVICES

Patent #:	9104834	Issue Dt:	08/11/2015	Application #:	14514919	Filing Dt:	10/15/2014
Publication #:	US20150033199	Pub Dt:	01/29/2015
Title:	SYSTEMS AND METHODS FOR SINGLE CELL PRODUCT PATH DELAY ANALYSIS

Patent #:	9245854	Issue Dt:	01/26/2016	Application #:	14515597	Filing Dt:	10/16/2014
Publication #:	US20150033554	Pub Dt:	02/05/2015
Title:	ORGANIC MODULE EMI SHIELDING STRUCTURES AND METHODS

Patent #:	10173889	Issue Dt:	01/08/2019	Application #:	14515681	Filing Dt:	10/16/2014
Publication #:	US20150041932	Pub Dt:	02/12/2015
Title:	PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES

Patent #:	9362229	Issue Dt:	06/07/2016	Application #:	14515925	Filing Dt:	10/16/2014
Publication #:	US20150035158	Pub Dt:	02/05/2015
Title:	SEMICONDUCTOR DEVICES WITH ENHANCED ELECTROMIGRATION PERFORMANCE

Patent #:	9431535	Issue Dt:	08/30/2016	Application #:	14515981	Filing Dt:	10/16/2014
Publication #:	US20150054028	Pub Dt:	02/26/2015
Title:	SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING

Patent #:	9276111	Issue Dt:	03/01/2016	Application #:	14516000	Filing Dt:	10/16/2014
Publication #:	US20150037957	Pub Dt:	02/05/2015
Title:	SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING

Patent #:	9397174	Issue Dt:	07/19/2016	Application #:	14516623	Filing Dt:	10/17/2014
Publication #:	US20150035076	Pub Dt:	02/05/2015
Title:	Self-Aligned Gate Electrode Diffusion Barriers

Patent #:	NONE	Issue Dt:		Application #:	14516721	Filing Dt:	10/17/2014
Publication #:	US20150037941	Pub Dt:	02/05/2015
Title:	FINFET CONTACTING A CONDUCTIVE STRAP STRUCTURE OF A DRAM

Patent #:	10290637	Issue Dt:	05/14/2019	Application #:	14516744	Filing Dt:	10/17/2014
Publication #:	US20150037947	Pub Dt:	02/05/2015
Title:	WRAP-AROUND FIN FOR CONTACTING A CAPACITOR STRAP OF A DRAM

Patent #:	9355308	Issue Dt:	05/31/2016	Application #:	14516776	Filing Dt:	10/17/2014
Publication #:	US20150036882	Pub Dt:	02/05/2015
Title:	AUDITING VIDEO ANALYTICS THROUGH ESSENCE GENERATION

Patent #:	NONE	Issue Dt:		Application #:	14516815	Filing Dt:	10/17/2014
Publication #:	US20150113239	Pub Dt:	04/23/2015
Title:	Creation and Management of Logical Volume Snapshots Under Hierarchical Storage System

Patent #:	9576880	Issue Dt:	02/21/2017	Application #:	14517131	Filing Dt:	10/17/2014
Publication #:	US20150035155	Pub Dt:	02/05/2015
Title:	DUAL DAMASCENE STRUCTURE WITH LINER

Patent #:	9086810	Issue Dt:	07/21/2015	Application #:	14517162	Filing Dt:	10/17/2014
Publication #:	US20150116859	Pub Dt:	04/30/2015
Title:	WRITING AND READING DATA HAVING MULTIPLE ACCESS PATTERNS ON TAPE MEDIA

Patent #:	9293476	Issue Dt:	03/22/2016	Application #:	14518023	Filing Dt:	10/20/2014
Publication #:	US20150102359	Pub Dt:	04/16/2015
Title:	INTEGRATING ACTIVE MATRIX INORGANIC LIGHT EMITTING DIODES FOR DISPLAY DEVICES

Patent #:	NONE	Issue Dt:		Application #:	14518033	Filing Dt:	10/20/2014
Publication #:	US20150096176	Pub Dt:	04/09/2015
Title:	Concentrating Thin Film Absorber Device and Method of Manufacture

Patent #:	NONE	Issue Dt:		Application #:	14518704	Filing Dt:	10/20/2014
Publication #:	US20150035169	Pub Dt:	02/05/2015
Title:	VIA STRUCTURE FOR THREE-DIMENSIONAL CIRCUIT INTEGRATION

Patent #:	9406569	Issue Dt:	08/02/2016	Application #:	14519493	Filing Dt:	10/21/2014
Publication #:	US20150056760	Pub Dt:	02/26/2015
Title:	SEMICONDUCTOR DEVICE HAVING DIFFUSION BARRIER TO REDUCE BACK CHANNEL LEAKAGE

Patent #:	9640552	Issue Dt:	05/02/2017	Application #:	14519596	Filing Dt:	10/21/2014
Publication #:	US20150287809	Pub Dt:	10/08/2015
Title:	MULTI-HEIGHT FIN FIELD EFFECT TRANSISTORS

Patent #:	NONE	Issue Dt:		Application #:	14519614	Filing Dt:	10/21/2014
Publication #:	US20150056799	Pub Dt:	02/26/2015
Title:	INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE AND RELATED METHOD

Patent #:	9450072	Issue Dt:	09/20/2016	Application #:	14519615	Filing Dt:	10/21/2014
Publication #:	US20150372109	Pub Dt:	12/24/2015
Title:	REPLACEMENT GATE STRUCTURE FOR ENHANCING CONDUCTIVITY

Patent #:	9048217	Issue Dt:	06/02/2015	Application #:	14519622	Filing Dt:	10/21/2014
Publication #:	US20150035026	Pub Dt:	02/05/2015
Title:	MIDDLE-OF-LINE BORDERLESS CONTACT STRUCTURE AND METHOD OF FORMING

Patent #:	9236863	Issue Dt:	01/12/2016	Application #:	14519630	Filing Dt:	10/21/2014
Publication #:	US20150035559	Pub Dt:	02/05/2015
Title:	COMPENSATED IMPEDANCE CALIBRATION CIRCUIT

Patent #:	10459031	Issue Dt:	10/29/2019	Application #:	14520115	Filing Dt:	10/21/2014
Publication #:	US20150113346	Pub Dt:	04/23/2015
Title:	ELECTRONIC CIRCUIT HAVING SERIAL LATCH SCAN CHAINS

Patent #:	9324655	Issue Dt:	04/26/2016	Application #:	14520390	Filing Dt:	10/22/2014
Publication #:	US20150035115	Pub Dt:	02/05/2015
Title:	MODIFIED VIA BOTTOM FOR BEOL VIA EFUSE

Patent #:	9349852	Issue Dt:	05/24/2016	Application #:	14520445	Filing Dt:	10/22/2014
Publication #:	US20150035059	Pub Dt:	02/05/2015
Title:	METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS

Patent #:	NONE	Issue Dt:		Application #:	14520648	Filing Dt:	10/22/2014
Publication #:	US20150035112	Pub Dt:	02/05/2015
Title:	SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STRUCTURES AND DESIGN STRUCTURES THEREOF

Patent #:	NONE	Issue Dt:		Application #:	14520677	Filing Dt:	10/22/2014
Publication #:	US20150033556	Pub Dt:	02/05/2015
Title:	FLEXIBLE FILM CARRIER TO INCREASE INTERCONNECT DENSITY OF MODULES AND METHODS THEREOF

Patent #:	9293454	Issue Dt:	03/22/2016	Application #:	14521605	Filing Dt:	10/23/2014
Publication #:	US20150041957	Pub Dt:	02/12/2015
Title:	BIPOLAR JUNCTION TRANSISTOR HAVING MULTI-SIDED BASE CONTACT

Patent #:	9424173	Issue Dt:	08/23/2016	Application #:	14521739	Filing Dt:	10/23/2014
Publication #:	US20160117240	Pub Dt:	04/28/2016
Title:	PERFORMING SECURE ADDRESS RELOCATION WITHIN A MULTI-PROCESSOR SYSTEM SHARING A SAME PHYSICAL MEMORY CHANNEL TO EXTERNAL MEMORY

Patent #:	9087927	Issue Dt:	07/21/2015	Application #:	14521743	Filing Dt:	10/23/2014
Publication #:	US20150044853	Pub Dt:	02/12/2015
Title:	THERMALLY STABLE HIGH-K TETRAGONAL HFO2 LAYER WITHIN HIGH ASPECT RATIO DEEP TRENCHES

Patent #:	9552474	Issue Dt:	01/24/2017	Application #:	14521795	Filing Dt:	10/23/2014
Publication #:	US20150121493	Pub Dt:	04/30/2015
Title:	Method and Computer System for Dynamically Providing Multi-Dimensional Based Password/Challenge Authentication

Patent #:	NONE	Issue Dt:		Application #:	14521948	Filing Dt:	10/23/2014
Publication #:	US20150044426	Pub Dt:	02/12/2015
Title:	CATALYTIC ETCH WITH MAGNETIC DIRECTION CONTROL

Patent #:	9318217	Issue Dt:	04/19/2016	Application #:	14522017	Filing Dt:	10/23/2014
Publication #:	US20160118138	Pub Dt:	04/28/2016
Title:	PROGRAMMING AN ELECTRICAL FUSE WITH A SILICON-CONTROLLED RECTIFIER

Patent #:	9553054	Issue Dt:	01/24/2017	Application #:	14522083	Filing Dt:	10/23/2014
Publication #:	US20160118348	Pub Dt:	04/28/2016
Title:	STRAIN DETECTION STRUCTURES FOR BONDED WAFERS AND CHIPS

Patent #:	9276093	Issue Dt:	03/01/2016	Application #:	14522090	Filing Dt:	10/23/2014
Publication #:	US20150054123	Pub Dt:	02/26/2015
Title:	SELF-ALIGNED EMITTER-BASE REGION

Patent #:	9105606	Issue Dt:	08/11/2015	Application #:	14522119	Filing Dt:	10/23/2014
Publication #:	US20150041868	Pub Dt:	02/12/2015
Title:	SELF ALIGNED CONTACT WITH IMPROVED ROBUSTNESS

Patent #:	9293382	Issue Dt:	03/22/2016	Application #:	14522626	Filing Dt:	10/24/2014
Publication #:	US20150041809	Pub Dt:	02/12/2015
Title:	VOLTAGE CONTRAST INSPECTION OF DEEP TRENCH ISOLATION

Patent #:	9257336	Issue Dt:	02/09/2016	Application #:	14522633	Filing Dt:	10/24/2014
Publication #:	US20150056804	Pub Dt:	02/26/2015
Title:	BOTTOM-UP PLATING OF THROUGH-SUBSTRATE VIAS

Patent #:	9275907	Issue Dt:	03/01/2016	Application #:	14522649	Filing Dt:	10/24/2014
Publication #:	US20150041858	Pub Dt:	02/12/2015
Title:	3D TRANSISTOR CHANNEL MOBILITY ENHANCEMENT

Patent #:	9356014	Issue Dt:	05/31/2016	Application #:	14522652	Filing Dt:	10/24/2014
Publication #:	US20150041895	Pub Dt:	02/12/2015
Title:	HIGH-VOLTAGE METAL-INSULATOR-SEMICONDUCTOR FIELD EFFECT TRANSISTOR STRUCTURES

Patent #:	9087754	Issue Dt:	07/21/2015	Application #:	14522664	Filing Dt:	10/24/2014
Publication #:	US20150041977	Pub Dt:	02/12/2015
Title:	STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES

Patent #:	9777388	Issue Dt:	10/03/2017	Application #:	14522809	Filing Dt:	10/24/2014
Publication #:	US20160115616	Pub Dt:	04/28/2016
Title:	ELECTROPLATING SYSTEM AND METHOD OF USING ELECTROPLATING SYSTEM FOR CONTROLLING CONCENTRATION OF ORGANIC ADDITIVES IN ELECTROPLATING SOLUTION

Patent #:	NONE	Issue Dt:		Application #:	14522848	Filing Dt:	10/24/2014
Publication #:	US20150058542	Pub Dt:	02/26/2015
Title:	UPDATING TECHNIQUES FOR MEMORY OF A CHASSIS MANAGEMENT MODULE

Patent #:	9847415	Issue Dt:	12/19/2017	Application #:	14523076	Filing Dt:	10/24/2014
Publication #:	US20150041896	Pub Dt:	02/12/2015
Title:	FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE

Patent #:	9496394	Issue Dt:	11/15/2016	Application #:	14523083	Filing Dt:	10/24/2014
Publication #:	US20160118496	Pub Dt:	04/28/2016
Title:	SEMICONDUCTOR STRUCTURES WITH FIELD EFFECT TRANSISTOR(S) HAVING LOW-RESISTANCE SOURCE/DRAIN CONTACT(S)

Patent #:	9337041	Issue Dt:	05/10/2016	Application #:	14524079	Filing Dt:	10/27/2014
Publication #:	US20150111350	Pub Dt:	04/23/2015
Title:	ANISOTROPIC DIELECTRIC MATERIAL GATE SPACER FOR A FIELD EFFECT TRANSISTOR

Patent #:	9349650	Issue Dt:	05/24/2016	Application #:	14524246	Filing Dt:	10/27/2014
Publication #:	US20150380314	Pub Dt:	12/31/2015
Title:	LOW RESISTANCE AND DEFECT FREE EPITAXIAL SEMICONDUCTOR MATERIAL FOR PROVIDING MERGED FinFETs

Patent #:	10146895	Issue Dt:	12/04/2018	Application #:	14524413	Filing Dt:	10/27/2014
Publication #:	US20150120268	Pub Dt:	04/30/2015
Title:	METHOD AND APPARATUS FOR SIMULATING A DIGITAL CIRCUIT

Patent #:	9087805	Issue Dt:	07/21/2015	Application #:	14524637	Filing Dt:	10/27/2014
Publication #:	US20150044787	Pub Dt:	02/12/2015
Title:	SEMICONDUCTOR TEST AND MONITORING STRUCTURE TO DETECT BOUNDARIES OF SAFE EFFECTIVE MODULUS

Patent #:	9679796	Issue Dt:	06/13/2017	Application #:	14525254	Filing Dt:	10/28/2014
Publication #:	US20160118283	Pub Dt:	04/28/2016
Title:	ANODIZED METAL ON CARRIER WAFER

Patent #:	9728440	Issue Dt:	08/08/2017	Application #:	14525267	Filing Dt:	10/28/2014
Publication #:	US20160118287	Pub Dt:	04/28/2016
Title:	NON-TRANSPARENT MICROELECTRONIC GRADE GLASS AS A SUBSTRATE, TEMPORARY CARRIER OR WAFER

Patent #:	NONE	Issue Dt:		Application #:	14525320	Filing Dt:	10/28/2014
Publication #:	US20160117433	Pub Dt:	04/28/2016
Title:	INTEGRATED CIRCUIT TIMING VARIABILITY REDUCTION

Patent #:	9018052	Issue Dt:	04/28/2015	Application #:	14525559	Filing Dt:	10/28/2014
Publication #:	US20150064853	Pub Dt:	03/05/2015
Title:	INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC

Patent #:	9165850	Issue Dt:	10/20/2015	Application #:	14525682	Filing Dt:	10/28/2014
Publication #:	US20150044864	Pub Dt:	02/12/2015
Title:	COMPENSATING FOR WARPAGE OF A FLIP CHIP PACKAGE BY VARYING HEIGHTS OF A REDISTRIBUTION LAYER ON AN INTEGRATED CIRCUIT CHIP

Patent #:	10163892	Issue Dt:	12/25/2018	Application #:	14526580	Filing Dt:	10/29/2014
Publication #:	US20150048416	Pub Dt:	02/19/2015
Title:	SILICON CONTROLLED RECTIFIERS (SCR), METHODS OF MANUFACTURE AND DESIGN STRUCTURES

Patent #:	9373637	Issue Dt:	06/21/2016	Application #:	14526767	Filing Dt:	10/29/2014
Publication #:	US20150054081	Pub Dt:	02/26/2015
Title:	EPITAXIAL SEMICONDUCTOR RESISTOR WITH SEMICONDUCTOR STRUCTURES ON SAME SUBSTRATE

Patent #:	9318551	Issue Dt:	04/19/2016	Application #:	14527042	Filing Dt:	10/29/2014
Publication #:	US20150060950	Pub Dt:	03/05/2015
Title:	TRENCH ISOLATION STRUCTURES AND METHODS FOR BIPOLAR JUNCTION TRANSISTORS

Patent #:	9040225	Issue Dt:	05/26/2015	Application #:	14527813	Filing Dt:	10/30/2014
Publication #:	US20150050601	Pub Dt:	02/19/2015
Title:	DEVELOPABLE BOTTOM ANTIREFLECTIVE COATING COMPOSITION AND PATTERN FORMING METHOD USING THEREOF

Patent #:	9410261	Issue Dt:	08/09/2016	Application #:	14528028	Filing Dt:	10/30/2014
Publication #:	US20150060266	Pub Dt:	03/05/2015
Title:	TWO MASK PROCESS FOR ELECTROPLATING METAL EMPLOYING A NEGATIVE ELECTROPHORETIC PHOTORESIST

Patent #:	9362309	Issue Dt:	06/07/2016	Application #:	14528266	Filing Dt:	10/30/2014
Publication #:	US20150056792	Pub Dt:	02/26/2015
Title:	FINFET AND METHOD OF FABRICATION

Patent #:	9578775	Issue Dt:	02/21/2017	Application #:	14528316	Filing Dt:	10/30/2014
Publication #:	US20150118894	Pub Dt:	04/30/2015
Title:	LGA SOCKET TERMINAL DAMAGE PREVENTION

Patent #:	9070734	Issue Dt:	06/30/2015	Application #:	14528388	Filing Dt:	10/30/2014
Publication #:	US20150053982	Pub Dt:	02/26/2015
Title:	HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED PARASITIC CAPACITANCE

Patent #:	9564508	Issue Dt:	02/07/2017	Application #:	14528435	Filing Dt:	10/30/2014
Publication #:	US20150056777	Pub Dt:	02/26/2015
Title:	DEVICE ISOLATION WITH IMPROVED THERMAL CONDUCTIVITY

Patent #:	NONE	Issue Dt:		Application #:	14528466	Filing Dt:	10/30/2014
Publication #:	US20150054033	Pub Dt:	02/26/2015
Title:	FINFET WITH SELF-ALIGNED PUNCHTHROUGH STOPPER

Patent #:	9269629	Issue Dt:	02/23/2016	Application #:	14528830	Filing Dt:	10/30/2014
Publication #:	US20150064874	Pub Dt:	03/05/2015
Title:	DUMMY FIN FORMATION BY GAS CLUSTER ION BEAM

Patent #:	9417501	Issue Dt:	08/16/2016	Application #:	14529243	Filing Dt:	10/31/2014
Publication #:	US20150064817	Pub Dt:	03/05/2015
Title:	ELECTRICALLY CONTROLLED OPTICAL FUSE AND METHOD OF FABRICATION

Patent #:	9478549	Issue Dt:	10/25/2016	Application #:	14529332	Filing Dt:	10/31/2014
Publication #:	US20150064855	Pub Dt:	03/05/2015
Title:	FINFET WITH DIELECTRIC ISOLATION BY SILICON-ON-NOTHING AND METHOD OF FABRICATION

Patent #:	9501638	Issue Dt:	11/22/2016	Application #:	14529338	Filing Dt:	10/31/2014
Publication #:	US20150121538	Pub Dt:	04/30/2015
Title:	TECHNIQUES FOR MANAGING SECURITY MODES APPLIED TO APPLICATION PROGRAM EXECUTION

Patent #:	9673089	Issue Dt:	06/06/2017	Application #:	14529431	Filing Dt:	10/31/2014
Publication #:	US20150056806	Pub Dt:	02/26/2015
Title:	INTERCONNECT STRUCTURE WITH ENHANCED RELIABILITY

100

Patent #:	9219068	Issue Dt:	12/22/2015	Application #:	14529825	Filing Dt:	10/31/2014
Publication #:	US20150340288	Pub Dt:	11/26/2015
Title:	FINFET WITH DIELECTRIC ISOLATION BY SILICON-ON-NOTHING AND METHOD OF FABRICATION

Assignor

INTERNATIONAL BUSINESS MACHINES CORPORATION

Exec Dt:

06/29/2015

Assignee

GLOBALFOUNDRIES U.S. 2 LLC

2070 ROUTE 52

HOPEWELL JUNCTION, NEW YORK 12533

Correspondence name and address
	HESLIN ROTHENBERG FARLEY & MESITI P.C.
	5 COLUMBIA CIRCLE
	ALBANY, NY 12203

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