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Reel/Frame:	036550/0001			Pages:	983
		Recorded:	09/03/2015
Attorney Dkt #:	3718.266
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14793
Page 147 of 148
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Patent #:	9087868	Issue Dt:	07/21/2015	Application #:	14593282	Filing Dt:	01/09/2015
Publication #:	US20150115399	Pub Dt:	04/30/2015
Title:	BIPOLAR JUNCTION TRANSISTORS WITH SELF-ALIGNED TERMINALS

Patent #:	NONE	Issue Dt:		Application #:	14593306	Filing Dt:	01/09/2015
Publication #:	US20150115369	Pub Dt:	04/30/2015
Title:	CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES

Patent #:	9087916	Issue Dt:	07/21/2015	Application #:	14594745	Filing Dt:	01/12/2015
Publication #:	US20150126004	Pub Dt:	05/07/2015
Title:	Method for Keyhole Repair in Replacement Metal Gate Integration Through the Use of a Printable Dielectric

Patent #:	NONE	Issue Dt:		Application #:	14595311	Filing Dt:	01/13/2015
Publication #:	US20150155301	Pub Dt:	06/04/2015
Title:	SEMICONDUCTOR SUBSTRATE WITH MULTIPLE SiGe REGIONS HAVING DIFFERENT GERMANIUM CONCENTRATIONS BY A SINGLE EPITAXY PROCESS

Patent #:	9541935	Issue Dt:	01/10/2017	Application #:	14595850	Filing Dt:	01/13/2015
Publication #:	US20150123633	Pub Dt:	05/07/2015
Title:	PASSGATE STRENGTH CALIBRATION TECHNIQUES FOR VOLTAGE REGULATORS

Patent #:	9412620	Issue Dt:	08/09/2016	Application #:	14597327	Filing Dt:	01/15/2015
Publication #:	US20150147869	Pub Dt:	05/28/2015
Title:	THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE FABRICATION INCLUDING WAFER SCALE MEMBRANE

Patent #:	9367695	Issue Dt:	06/14/2016	Application #:	14598256	Filing Dt:	01/16/2015
Publication #:	US20150161395	Pub Dt:	06/11/2015
Title:	SOFTWARE VULNERABILITY NOTIFICATION VIA ICON DECORATIONS

Patent #:	9543253	Issue Dt:	01/10/2017	Application #:	14598258	Filing Dt:	01/16/2015
Publication #:	US20150136838	Pub Dt:	05/21/2015
Title:	METHOD FOR SHAPING A LAMINATE SUBSTRATE

Patent #:	NONE	Issue Dt:		Application #:	14598311	Filing Dt:	01/16/2015
Publication #:	US20150126025	Pub Dt:	05/07/2015
Title:	INTERFACE-FREE METAL GATE STACK

Patent #:	10020256	Issue Dt:	07/10/2018	Application #:	14599576	Filing Dt:	01/19/2015
Publication #:	US20150130019	Pub Dt:	05/14/2015
Title:	ELECTRONIC FUSE HAVING AN INSULATION LAYER

Patent #:	9425080	Issue Dt:	08/23/2016	Application #:	14600229	Filing Dt:	01/20/2015
Publication #:	US20150132896	Pub Dt:	05/14/2015
Title:	NON-VOLATILE MEMORY DEVICE EMPLOYING SEMICONDUCTOR NANOPARTICLES

Patent #:	9390969	Issue Dt:	07/12/2016	Application #:	14600273	Filing Dt:	01/20/2015
Publication #:	US20150140809	Pub Dt:	05/21/2015
Title:	INTEGRATED CIRCUIT AND INTERCONNECT, AND METHOD OF FABRICATING SAME

Patent #:	9225360	Issue Dt:	12/29/2015	Application #:	14601172	Filing Dt:	01/20/2015
Publication #:	US20150149860	Pub Dt:	05/28/2015
Title:	ITERATIVE DATA STORAGE READ CHANNEL ARCHITECTURE

Patent #:	NONE	Issue Dt:		Application #:	14601296	Filing Dt:	01/21/2015
Publication #:	US20150130064	Pub Dt:	05/14/2015
Title:	METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES AND A SEMICONDUCTOR STRUCTURE

Patent #:	9543403	Issue Dt:	01/10/2017	Application #:	14601655	Filing Dt:	01/21/2015
Publication #:	US20160211345	Pub Dt:	07/21/2016
Title:	BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE EMITTER FINGERS

Patent #:	9099493	Issue Dt:	08/04/2015	Application #:	14601745	Filing Dt:	01/21/2015
Publication #:	US20150132898	Pub Dt:	05/14/2015
Title:	Semiconductor Device With Raised Source/Drain And Replacement Metal Gate

Patent #:	9653204	Issue Dt:	05/16/2017	Application #:	14602567	Filing Dt:	01/22/2015
Publication #:	US20160217904	Pub Dt:	07/28/2016
Title:	SYMMETRIC MULTI-PORT INDUCTOR FOR DIFFERENTIAL MULTI-BAND RF CIRCUITS

Patent #:	9460760	Issue Dt:	10/04/2016	Application #:	14604009	Filing Dt:	01/23/2015
Publication #:	US20160217832	Pub Dt:	07/28/2016
Title:	DATA-DEPENDENT SELF-BIASED DIFFERENTIAL SENSE AMPLIFIER

Patent #:	NONE	Issue Dt:		Application #:	14605009	Filing Dt:	01/26/2015
Publication #:	US20150144886	Pub Dt:	05/28/2015
Title:	FINFET WITH MERGE-FREE FINS

Patent #:	NONE	Issue Dt:		Application #:	14605018	Filing Dt:	01/26/2015
Publication #:	US20150140762	Pub Dt:	05/21/2015
Title:	FINFET WITH MERGE-FREE FINS

Patent #:	9263442	Issue Dt:	02/16/2016	Application #:	14606224	Filing Dt:	01/27/2015
Publication #:	US20150137267	Pub Dt:	05/21/2015
Title:	REPLACEMENT GATE STRUCTURES AND METHODS OF MANUFACTURING

Patent #:	9355921	Issue Dt:	05/31/2016	Application #:	14607160	Filing Dt:	01/28/2015
Publication #:	US20150140697	Pub Dt:	05/21/2015
Title:	TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS

Patent #:	NONE	Issue Dt:		Application #:	14607161	Filing Dt:	01/28/2015
Publication #:	US20150140698	Pub Dt:	05/21/2015
Title:	TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS

Patent #:	9299617	Issue Dt:	03/29/2016	Application #:	14607191	Filing Dt:	01/28/2015
Publication #:	US20150147868	Pub Dt:	05/28/2015
Title:	LOCALLY ISOLATED PROTECTED BULK FINFET SEMICONDUCTOR DEVICE

Patent #:	NONE	Issue Dt:		Application #:	14607611	Filing Dt:	01/28/2015
Publication #:	US20150144887	Pub Dt:	05/28/2015
Title:	MANUFACTURABLE SUB-3 NANOMETER PALLADIUM GAP DEVICES FOR FIXED ELECTRODE TUNNELING RECOGNITION

Patent #:	NONE	Issue Dt:		Application #:	14607629	Filing Dt:	01/28/2015
Publication #:	US20150144888	Pub Dt:	05/28/2015
Title:	MANUFACTURABLE SUB-3 NANOMETER PALLADIUM GAP DEVICES FOR FIXED ELECTRODE TUNNELING RECOGNITION

Patent #:	NONE	Issue Dt:		Application #:	14607657	Filing Dt:	01/28/2015
Publication #:	US20150153320	Pub Dt:	06/04/2015
Title:	MANUFACTURABLE SUB-3 NANOMETER PALLADIUM GAP DEVICES FOR FIXED ELECTRODE TUNNELING RECOGNITION

Patent #:	NONE	Issue Dt:		Application #:	14607694	Filing Dt:	01/28/2015
Publication #:	US20150140716	Pub Dt:	05/21/2015
Title:	MANUFACTURABLE SUB-3 NANOMETER PALLADIUM GAP DEVICES FOR FIXED ELECTRODE TUNNELING RECOGNITION

Patent #:	9087921	Issue Dt:	07/21/2015	Application #:	14608365	Filing Dt:	01/29/2015
Publication #:	US20150147853	Pub Dt:	05/28/2015
Title:	CMOS WITH DUAL RAISED SOURCE AND DRAIN FOR NMOS AND PMOS

Patent #:	9263465	Issue Dt:	02/16/2016	Application #:	14608370	Filing Dt:	01/29/2015
Publication #:	US20150137147	Pub Dt:	05/21/2015
Title:	CMOS WITH DUAL RAISED SOURCE AND DRAIN FOR NMOS AND PMOS

Patent #:	9263466	Issue Dt:	02/16/2016	Application #:	14608374	Filing Dt:	01/29/2015
Publication #:	US20150140743	Pub Dt:	05/21/2015
Title:	CMOS WITH DUAL RAISED SOURCE AND DRAIN FOR NMOS AND PMOS

Patent #:	9299719	Issue Dt:	03/29/2016	Application #:	14608386	Filing Dt:	01/29/2015
Publication #:	US20150140744	Pub Dt:	05/21/2015
Title:	CMOS WITH DUAL RAISED SOURCE AND DRAIN FOR NMOS AND PMOS

Patent #:	9183878	Issue Dt:	11/10/2015	Application #:	14608508	Filing Dt:	01/29/2015
Publication #:	US20150146320	Pub Dt:	05/28/2015
Title:	READING METHOD FOR LINEAR TAPE OPEN

Patent #:	9290806	Issue Dt:	03/22/2016	Application #:	14608675	Filing Dt:	01/29/2015
Publication #:	US20150141299	Pub Dt:	05/21/2015
Title:	FABRICATING SELF-FORMED NANOMETER PORE ARRAY AT WAFER SCALE FOR DNA SEQUENCING

Patent #:	9097698	Issue Dt:	08/04/2015	Application #:	14608781	Filing Dt:	01/29/2015
Publication #:	US20150137069	Pub Dt:	05/21/2015
Title:	NANOGAP DEVICE WITH CAPPED NANOWIRE STRUCTURES

Patent #:	NONE	Issue Dt:		Application #:	14608807	Filing Dt:	01/29/2015
Publication #:	US20150155238	Pub Dt:	06/04/2015
Title:	MAKING AN EFUSE

Patent #:	NONE	Issue Dt:		Application #:	14610002	Filing Dt:	01/30/2015
Publication #:	US20150137366	Pub Dt:	05/21/2015
Title:	REACTIVE BONDING OF A FLIP CHIP PACKAGE

Patent #:	NONE	Issue Dt:		Application #:	14612639	Filing Dt:	02/03/2015
Publication #:	US20160225919	Pub Dt:	08/04/2016
Title:	DEVICE STRUCTURE WITH NEGATIVE RESISTANCE CHARACTERISTICS

Patent #:	9552455	Issue Dt:	01/24/2017	Application #:	14612683	Filing Dt:	02/03/2015
Publication #:	US20160224717	Pub Dt:	08/04/2016
Title:	Method for an Efficient Modeling of the Impact of Device-Level Self-Heating on Electromigration Limited Current Specifications

Patent #:	9673055	Issue Dt:	06/06/2017	Application #:	14613416	Filing Dt:	02/04/2015
Publication #:	US20160225634	Pub Dt:	08/04/2016
Title:	METHOD FOR QUADRUPLE FREQUENCY FINFETS WITH SINGLE-FIN REMOVAL

Patent #:	9852956	Issue Dt:	12/26/2017	Application #:	14613570	Filing Dt:	02/04/2015
Publication #:	US20160225680	Pub Dt:	08/04/2016
Title:	EXTRACTION OF RESISTANCE ASSOCIATED WITH LATERALLY DIFFUSED DOPANT PROFILES IN CMOS DEVICES

Patent #:	9178019	Issue Dt:	11/03/2015	Application #:	14613781	Filing Dt:	02/04/2015
Publication #:	US20150171164	Pub Dt:	06/18/2015
Title:	FIN ISOLATION IN MULTI-GATE FIELD EFFECT TRANSISTORS

Patent #:	9269407	Issue Dt:	02/23/2016	Application #:	14614470	Filing Dt:	02/05/2015
Title:	SYSTEM AND METHOD FOR MANAGING CIRCUIT PERFORMANCE AND POWER CONSUMPTION BY SELECTIVELY ADJUSTING SUPPLY VOLTAGE OVER TIME

Patent #:	NONE	Issue Dt:		Application #:	14616135	Filing Dt:	02/06/2015
Publication #:	US20150154331	Pub Dt:	06/04/2015
Title:	ESTIMATING DELAY DETERIORATION DUE TO DEVICE DEGRADATION IN INTEGRATED CIRCUITS

Patent #:	9269375	Issue Dt:	02/23/2016	Application #:	14616614	Filing Dt:	02/06/2015
Publication #:	US20150154984	Pub Dt:	06/04/2015
Title:	MULTI-FORMAT READ DRIVE

Patent #:	9818796	Issue Dt:	11/14/2017	Application #:	14616855	Filing Dt:	02/09/2015
Publication #:	US20160380026	Pub Dt:	12/29/2016
Title:	PLANAR QUBITS HAVING INCREASED COHERENCE TIMES

Patent #:	9373696	Issue Dt:	06/21/2016	Application #:	14617314	Filing Dt:	02/09/2015
Publication #:	US20150155366	Pub Dt:	06/04/2015
Title:	Techniques to Form Uniform and Stable Silicide

Patent #:	NONE	Issue Dt:		Application #:	14617647	Filing Dt:	02/09/2015
Publication #:	US20150200277	Pub Dt:	07/16/2015
Title:	NONVOLATILE MEMORY DEVICE USING SEMICONDUCTOR NANOCRYSTALS AND METHOD OF FORMING SAME

Patent #:	9373507	Issue Dt:	06/21/2016	Application #:	14618498	Filing Dt:	02/10/2015
Publication #:	US20150179453	Pub Dt:	06/25/2015
Title:	DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET

Patent #:	NONE	Issue Dt:		Application #:	14619152	Filing Dt:	02/11/2015
Publication #:	US20150155353	Pub Dt:	06/04/2015
Title:	BORDERLESS CONTACT FOR ULTRA-THIN BODY DEVICES

Patent #:	9305883	Issue Dt:	04/05/2016	Application #:	14620233	Filing Dt:	02/12/2015
Publication #:	US20150179576	Pub Dt:	06/25/2015
Title:	LOCALLY RAISED EPITAXY FOR IMPROVED CONTACT BY LOCAL SILICON CAPPING DURING TRENCH SILICIDE PROCESSINGS

Patent #:	9618566	Issue Dt:	04/11/2017	Application #:	14620273	Filing Dt:	02/12/2015
Publication #:	US20160238653	Pub Dt:	08/18/2016
Title:	SYSTEMS AND METHODS TO PREVENT INCORPORATION OF A USED INTEGRATED CIRCUIT CHIP INTO A PRODUCT

Patent #:	9162877	Issue Dt:	10/20/2015	Application #:	14621039	Filing Dt:	02/12/2015
Publication #:	US20150151961	Pub Dt:	06/04/2015
Title:	LATERAL ETCH STOP FOR NEMS RELEASE ETCH FOR HIGH DENSITY NEMS/CMOS MONOLITHIC INTEGRATION

Patent #:	9087876	Issue Dt:	07/21/2015	Application #:	14621785	Filing Dt:	02/13/2015
Publication #:	US20150162239	Pub Dt:	06/11/2015
Title:	TITANIUM OXYNITRIDE HARD MASK FOR LITHOGRAPHIC PATTERNING

Patent #:	10096609	Issue Dt:	10/09/2018	Application #:	14622997	Filing Dt:	02/16/2015
Publication #:	US20160240438	Pub Dt:	08/18/2016
Title:	MODIFIED TUNGSTEN SILICON

Patent #:	10192822	Issue Dt:	01/29/2019	Application #:	14623115	Filing Dt:	02/16/2015
Publication #:	US20160240478	Pub Dt:	08/18/2016
Title:	MODIFIED TUNGSTEN SILICON

Patent #:	9059267	Issue Dt:	06/16/2015	Application #:	14623720	Filing Dt:	02/17/2015
Publication #:	US20150162425	Pub Dt:	06/11/2015
Title:	III-V Device with Overlapped Extension Regions Using Replacement Gate

Patent #:	9064946	Issue Dt:	06/23/2015	Application #:	14623732	Filing Dt:	02/17/2015
Publication #:	US20150162426	Pub Dt:	06/11/2015
Title:	III-V FET Device with Overlapped Extension Regions Using Gate Last

Patent #:	NONE	Issue Dt:		Application #:	14623847	Filing Dt:	02/17/2015
Publication #:	US20150162898	Pub Dt:	06/11/2015
Title:	EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING

Patent #:	NONE	Issue Dt:		Application #:	14623916	Filing Dt:	02/17/2015
Publication #:	US20150162899	Pub Dt:	06/11/2015
Title:	EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING

Patent #:	NONE	Issue Dt:		Application #:	14624019	Filing Dt:	02/17/2015
Publication #:	US20150162903	Pub Dt:	06/11/2015
Title:	EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING

Patent #:	NONE	Issue Dt:		Application #:	14624026	Filing Dt:	02/17/2015
Publication #:	US20150162904	Pub Dt:	06/11/2015
Title:	EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING

Patent #:	9865564	Issue Dt:	01/09/2018	Application #:	14624601	Filing Dt:	02/18/2015
Publication #:	US20150162300	Pub Dt:	06/11/2015
Title:	LASER ASHING OF POLYIMIDE FOR SEMICONDUCTOR MANUFACTURING

Patent #:	9625325	Issue Dt:	04/18/2017	Application #:	14624907	Filing Dt:	02/18/2015
Publication #:	US20160240479	Pub Dt:	08/18/2016
Title:	SYSTEM AND METHOD FOR IDENTIFYING OPERATING TEMPERATURES AND MODIFYING OF INTEGRATED CIRCUITS

Patent #:	NONE	Issue Dt:		Application #:	14626945	Filing Dt:	02/20/2015
Publication #:	US20150162528	Pub Dt:	06/11/2015
Title:	POST-FABRICATION SELF-ALIGNED INITIALIZATION OF INTEGRATED DEVICES

Patent #:	9405186	Issue Dt:	08/02/2016	Application #:	14628446	Filing Dt:	02/23/2015
Publication #:	US20160246167	Pub Dt:	08/25/2016
Title:	SAMPLE PLAN CREATION FOR OPTICAL PROXIMITY CORRECTION WITH MINIMAL NUMBER OF CLIPS

Patent #:	9814982	Issue Dt:	11/14/2017	Application #:	14630774	Filing Dt:	02/25/2015
Publication #:	US20160243443	Pub Dt:	08/25/2016
Title:	MITIGATING COLLISIONS IN A PHYSICAL SPACE DURING GAMING

Patent #:	10091909	Issue Dt:	10/02/2018	Application #:	14632180	Filing Dt:	02/26/2015
Publication #:	US20150195955	Pub Dt:	07/09/2015
Title:	METHOD AND DEVICE FOR COOLING A HEAT GENERATING COMPONENT

Patent #:	10278306	Issue Dt:	04/30/2019	Application #:	14632194	Filing Dt:	02/26/2015
Publication #:	US20150176911	Pub Dt:	06/25/2015
Title:	METHOD AND DEVICE FOR COOLING A HEAT GENERATING COMPONENT

Patent #:	9378972	Issue Dt:	06/28/2016	Application #:	14632313	Filing Dt:	02/26/2015
Publication #:	US20150170927	Pub Dt:	06/18/2015
Title:	INTEGRATION OF DENSE AND VARIABLE PITCH FIN STRUCTURES

Patent #:	9337122	Issue Dt:	05/10/2016	Application #:	14633069	Filing Dt:	02/26/2015
Publication #:	US20150221575	Pub Dt:	08/06/2015
Title:	TRANSFERRING HEAT THROUGH AN OPTICAL LAYER OF INTEGRATED CIRCUITRY

Patent #:	9727684	Issue Dt:	08/08/2017	Application #:	14633477	Filing Dt:	02/27/2015
Publication #:	US20150248520	Pub Dt:	09/03/2015
Title:	METHOD AND APPARATUS FOR PHYSICAL-AWARE HOLD VIOLATION FIXING

Patent #:	NONE	Issue Dt:		Application #:	14634820	Filing Dt:	02/28/2015
Publication #:	US20150179536	Pub Dt:	06/25/2015
Title:	CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS

Patent #:	10008848	Issue Dt:	06/26/2018	Application #:	14635005	Filing Dt:	03/02/2015
Publication #:	US20160261109	Pub Dt:	09/08/2016
Title:	METHOD TO PROTECT SENSITIVE DEVICES FROM ELECTROSTATIC DISCHARGE DAMAGE

Patent #:	9851397	Issue Dt:	12/26/2017	Application #:	14635125	Filing Dt:	03/02/2015
Publication #:	US20160258998	Pub Dt:	09/08/2016
Title:	ELECTROMIGRATION TESTING OF INTERCONNECT ANALOGUES HAVING BOTTOM-CONNECTED SENSORY PINS

Patent #:	NONE	Issue Dt:		Application #:	14636679	Filing Dt:	03/03/2015
Publication #:	US20160260674	Pub Dt:	09/08/2016
Title:	REMOVAL OF INTEGRATED CIRCUIT CHIPS FROM A WAFER

Patent #:	9342466	Issue Dt:	05/17/2016	Application #:	14640047	Filing Dt:	03/06/2015
Publication #:	US20150178225	Pub Dt:	06/25/2015
Title:	MULTIPLE VOLUME ENCRYPTION OF STORAGE DEVICES USING SELF ENCRYPTING DRIVE (SED)

Patent #:	9196700	Issue Dt:	11/24/2015	Application #:	14640698	Filing Dt:	03/06/2015
Publication #:	US20150187901	Pub Dt:	07/02/2015
Title:	MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC

Patent #:	9252232	Issue Dt:	02/02/2016	Application #:	14640735	Filing Dt:	03/06/2015
Publication #:	US20150179459	Pub Dt:	06/25/2015
Title:	MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC

Patent #:	9276118	Issue Dt:	03/01/2016	Application #:	14640851	Filing Dt:	03/06/2015
Publication #:	US20150179789	Pub Dt:	06/25/2015
Title:	FinFET DEVICE HAVING A MERGE SOURCE DRAIN REGION UNDER CONTACT AREAS AND UNMERGED FINS BETWEEN CONTACT AREAS, AND A METHOD OF MANUFACTURING SAME

Patent #:	9401373	Issue Dt:	07/26/2016	Application #:	14641462	Filing Dt:	03/09/2015
Publication #:	US20150187815	Pub Dt:	07/02/2015
Title:	MULTI-FIN FINFETS WITH MERGED-FIN SOURCE/DRAINS AND REPLACEMENT GATES

Patent #:	9577099	Issue Dt:	02/21/2017	Application #:	14641917	Filing Dt:	03/09/2015
Publication #:	US20160268413	Pub Dt:	09/15/2016
Title:	DIAMOND SHAPED SOURCE DRAIN EPITAXY WITH UNDERLYING BUFFER LAYER

Patent #:	9379116	Issue Dt:	06/28/2016	Application #:	14642909	Filing Dt:	03/10/2015
Title:	FABRICATION OF A DEEP TRENCH MEMORY CELL

Patent #:	NONE	Issue Dt:		Application #:	14643224	Filing Dt:	03/10/2015
Publication #:	US20150187764	Pub Dt:	07/02/2015
Title:	STACKED CARBON-BASED FETS

Patent #:	NONE	Issue Dt:		Application #:	14643323	Filing Dt:	03/10/2015
Publication #:	US20160266332	Pub Dt:	09/15/2016
Title:	OPTICAL DIE PACKAGING

Patent #:	9865514	Issue Dt:	01/09/2018	Application #:	14643436	Filing Dt:	03/10/2015
Publication #:	US20150187667	Pub Dt:	07/02/2015
Title:	INLINE MEASUREMENT OF THROUGH-SILICON VIA DEPTH

Patent #:	9251825	Issue Dt:	02/02/2016	Application #:	14645350	Filing Dt:	03/11/2015
Publication #:	US20150187379	Pub Dt:	07/02/2015
Title:	BACKWARD COMPATIBLE HEAD FOR QUASI-STATIC TILTED READING AND/OR RECORDING

Patent #:	10032870	Issue Dt:	07/24/2018	Application #:	14645449	Filing Dt:	03/12/2015
Publication #:	US20160268123	Pub Dt:	09/15/2016
Title:	LOW DEFECT III-V SEMICONDUCTOR TEMPLATE ON POROUS SILICON

Patent #:	NONE	Issue Dt:		Application #:	14645477	Filing Dt:	03/12/2015
Publication #:	US20160268378	Pub Dt:	09/15/2016
Title:	INTEGRATED STRAINED FIN AND RELAXED FIN

Patent #:	9581644	Issue Dt:	02/28/2017	Application #:	14656790	Filing Dt:	03/13/2015
Publication #:	US20150276872	Pub Dt:	10/01/2015
Title:	DIGITAL IC SIMULATION

Patent #:	9170338	Issue Dt:	10/27/2015	Application #:	14657864	Filing Dt:	03/13/2015
Publication #:	US20150253438	Pub Dt:	09/10/2015
Title:	CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS

Patent #:	NONE	Issue Dt:		Application #:	14658975	Filing Dt:	03/16/2015
Publication #:	US20150187881	Pub Dt:	07/02/2015
Title:	CONTACT RESISTANCE REDUCTION IN FINFETS

Patent #:	9418745	Issue Dt:	08/16/2016	Application #:	14661383	Filing Dt:	03/18/2015
Title:	REBALANCING IN TWIN CELL MEMORY SCHEMES TO ENABLE MULTIPLE WRITES

Patent #:	9397158	Issue Dt:	07/19/2016	Application #:	14662468	Filing Dt:	03/19/2015
Publication #:	US20150194484	Pub Dt:	07/09/2015
Title:	Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion

Patent #:	9484402	Issue Dt:	11/01/2016	Application #:	14662743	Filing Dt:	03/19/2015
Publication #:	US20150194334	Pub Dt:	07/09/2015
Title:	Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion

Patent #:	NONE	Issue Dt:		Application #:	14663256	Filing Dt:	03/19/2015
Publication #:	US20150325647	Pub Dt:	11/12/2015
Title:	INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORs (FETs) AND METHOD OF MANUFACTURE

Patent #:	9295166	Issue Dt:	03/22/2016	Application #:	14663754	Filing Dt:	03/20/2015
Publication #:	US20150194408	Pub Dt:	07/09/2015
Title:	DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING

Patent #:	9095081	Issue Dt:	07/28/2015	Application #:	14663806	Filing Dt:	03/20/2015
Publication #:	US20150195920	Pub Dt:	07/09/2015
Title:	DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING

Patent #:	9343407	Issue Dt:	05/17/2016	Application #:	14664036	Filing Dt:	03/20/2015
Publication #:	US20150194385	Pub Dt:	07/09/2015
Title:	METHOD TO FABRICATE COPPER WIRING STRUCTURES AND STRUCTURES FORMED THEREBY

100

Patent #:	9337264	Issue Dt:	05/10/2016	Application #:	14664435	Filing Dt:	03/20/2015
Publication #:	US20150194487	Pub Dt:	07/09/2015
Title:	Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric

Assignor

INTERNATIONAL BUSINESS MACHINES CORPORATION

Exec Dt:

06/29/2015

Assignee

GLOBALFOUNDRIES U.S. 2 LLC

2070 ROUTE 52

HOPEWELL JUNCTION, NEW YORK 12533

Correspondence name and address
	HESLIN ROTHENBERG FARLEY & MESITI P.C.
	5 COLUMBIA CIRCLE
	ALBANY, NY 12203

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