|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14665432
|
Filing Dt:
|
03/23/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
LIQUID CRYSTAL INTEGRATED CIRCUIT AND METHOD TO FABRICATE SAME
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|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
14666469
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Filing Dt:
|
03/24/2015
|
Publication #:
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|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
SILICON-ON-NOTHING FINFETS
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14666590
|
Filing Dt:
|
03/24/2015
|
Publication #:
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|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
TAPE HEAD WITH TAPE-BEARING SURFACE EXHIBITING AN ARRAY OF PROTRUDING TOPOGRAPHIC FEATURES
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|
|
Patent #:
|
|
Issue Dt:
|
03/06/2018
|
Application #:
|
14668017
|
Filing Dt:
|
03/25/2015
|
Publication #:
|
|
Pub Dt:
|
09/29/2016
| | | | |
Title:
|
GLASS INTERPOSER WITH EMBEDDED THERMOELECTRIC DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
|
Application #:
|
14668018
|
Filing Dt:
|
03/25/2015
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
DENSE FINFET SRAM
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|
|
Patent #:
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|
Issue Dt:
|
02/28/2017
|
Application #:
|
14668031
|
Filing Dt:
|
03/25/2015
|
Publication #:
|
|
Pub Dt:
|
09/29/2016
| | | | |
Title:
|
METHOD OF FORMING A GLASS INTERPOSER WITH THERMAL VIAS
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|
|
Patent #:
|
|
Issue Dt:
|
01/12/2016
|
Application #:
|
14669043
|
Filing Dt:
|
03/26/2015
|
Title:
|
MEMORY CELLS WITH READ ACCESS SCHEMES
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|
|
Patent #:
|
|
Issue Dt:
|
07/26/2016
|
Application #:
|
14669775
|
Filing Dt:
|
03/26/2015
|
Title:
|
THERMAL HOT SPOT COOLING FOR SEMICONDUCTOR DEVICES
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|
|
Patent #:
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|
Issue Dt:
|
04/26/2016
|
Application #:
|
14671819
|
Filing Dt:
|
03/27/2015
|
Publication #:
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|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
HIGH DENSITY TIMING BASED SERVO FORMAT FOR USE WITH TILTED TRANSDUCER ARRAYS
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|
Patent #:
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|
Issue Dt:
|
06/28/2016
|
Application #:
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14672157
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Filing Dt:
|
03/28/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14672160
|
Filing Dt:
|
03/28/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS
|
|
|
Patent #:
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|
Issue Dt:
|
05/24/2016
|
Application #:
|
14672865
|
Filing Dt:
|
03/30/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
HIGH VOLTAGE LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LDMOSFET) HAVING A DEEP FULLY DEPLETED DRAIN DRIFT REGION
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|
|
Patent #:
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|
Issue Dt:
|
12/26/2017
|
Application #:
|
14673185
|
Filing Dt:
|
03/30/2015
|
Publication #:
|
|
Pub Dt:
|
10/06/2016
| | | | |
Title:
|
VIA LEAKAGE AND BREAKDOWN TESTING
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|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
14673958
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
FORMATION OF A HIGH ASPECT RATIO TRENCH IN A SEMICONDUCTOR SUBSTRATE AND A BIPOLAR SEMICONDUCTOR DEVICE HAVING A HIGH ASPECT RATIO TRENCH ISOLATION REGION
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14674242
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
LIQUID CRYSTAL INTEGRATED CIRCUIT AND METHOD TO FABRICATE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2016
|
Application #:
|
14674571
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
10/06/2016
| | | | |
Title:
|
PREDICTING PROCESS FAIL LIMITS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2017
|
Application #:
|
14674859
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
10/06/2016
| | | | |
Title:
|
ANONYMOUS VEHICLE COMMUNICATION PROTOCOL IN VEHICLE-TO-VEHICLE NETWORKS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2016
|
Application #:
|
14677303
|
Filing Dt:
|
04/02/2015
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
BIPOLAR JUNCTION TRANSISTORS WITH SELF-ALIGNED TERMINALS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
14678024
|
Filing Dt:
|
04/03/2015
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON CHANNELS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2016
|
Application #:
|
14680328
|
Filing Dt:
|
04/07/2015
|
Title:
|
DEFECT REDUCTION WITH ROTATED DOUBLE ASPECT RATIO TRAPPING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14681215
|
Filing Dt:
|
04/08/2015
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
ENGINEERING MULTIPLE THRESHOLD VOLTAGES IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14683995
|
Filing Dt:
|
04/10/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
SPLIT FLEX CABLE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2016
|
Application #:
|
14684533
|
Filing Dt:
|
04/13/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
DEEP TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2016
|
Application #:
|
14685061
|
Filing Dt:
|
04/13/2015
|
Publication #:
|
|
Pub Dt:
|
10/13/2016
| | | | |
Title:
|
ELECTRONIC PACKAGE THAT INCLUDES A PLURALITY OF INTEGRATED CIRCUIT DEVICES BONDED IN A THREE-DIMENSIONAL STACK ARRANGEMENT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14685736
|
Filing Dt:
|
04/14/2015
|
Publication #:
|
|
Pub Dt:
|
10/20/2016
| | | | |
Title:
|
Automatic Analytical Cloud Scaling of Hardware Using Resource Sub-Cloud
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14685973
|
Filing Dt:
|
04/14/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
SEPARATING BONDED WAFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2016
|
Application #:
|
14686260
|
Filing Dt:
|
04/14/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING SOURCE/DRAIN EPITAXIAL OVERGROWTH FOR FORMING SELF-ALIGNED CONTACTS WITHOUT SPACER LOSS AND A SEMICONDUCTOR DEVICE FORMED BY SAME
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|
|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
14686904
|
Filing Dt:
|
04/15/2015
|
Publication #:
|
|
Pub Dt:
|
10/20/2016
| | | | |
Title:
|
WHOLE WAFER EDGE SEAL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2016
|
Application #:
|
14686972
|
Filing Dt:
|
04/15/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
BARRIER TRENCH STRUCTURE AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2017
|
Application #:
|
14687002
|
Filing Dt:
|
04/15/2015
|
Publication #:
|
|
Pub Dt:
|
10/20/2016
| | | | |
Title:
|
ON CHIP ANTENNA WITH OPENING
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|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
14687049
|
Filing Dt:
|
04/15/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
ALTERING CAPACITANCE OF MIM CAPACITOR HAVING REACTIVE LAYER THEREIN
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|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
14687050
|
Filing Dt:
|
04/15/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
DATA STORAGE TAPE WITH RANDOM ACCESS DATA
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|
|
Patent #:
|
|
Issue Dt:
|
06/28/2016
|
Application #:
|
14687489
|
Filing Dt:
|
04/15/2015
|
Publication #:
|
|
Pub Dt:
|
10/15/2015
| | | | |
Title:
|
CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS
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|
|
Patent #:
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|
Issue Dt:
|
02/16/2016
|
Application #:
|
14688027
|
Filing Dt:
|
04/16/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14688215
|
Filing Dt:
|
04/16/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14689463
|
Filing Dt:
|
04/17/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
ALTERNATING OPEN-ENDED VIA CHAINS FOR TESTING VIA FORMATION AND DIELECTRIC INTEGRITY
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|
|
Patent #:
|
|
Issue Dt:
|
08/07/2018
|
Application #:
|
14691124
|
Filing Dt:
|
04/20/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
Laser Doping of Crystalline Semiconductors Using a Dopant-Containing Amorphous Silicon Stack for Dopant Source and Passivation
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14691326
|
Filing Dt:
|
04/20/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
FORMATION OF METAL NANOSPHERES AND MICROSPHERES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2017
|
Application #:
|
14692881
|
Filing Dt:
|
04/22/2015
|
Publication #:
|
|
Pub Dt:
|
10/27/2016
| | | | |
Title:
|
HIGH DENSITY CAPACITOR STRUCTURE AND METHOD
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|
|
Patent #:
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|
Issue Dt:
|
01/17/2017
|
Application #:
|
14694265
|
Filing Dt:
|
04/23/2015
|
Publication #:
|
|
Pub Dt:
|
09/24/2015
| | | | |
Title:
|
BURIED WAVEGUIDE PHOTODETECTOR
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|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
14694831
|
Filing Dt:
|
04/23/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
BOOSTING DECOMPRESSION IN THE PRESENCE OF REOCCURRING HUFFMAN TREES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14694838
|
Filing Dt:
|
04/23/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
DYNAMIC RECONFIGURATION-SWITCHING OF WINDINGS IN AN ELECTRIC MOTOR USED AS A GENERATOR IN AN ELECTRIC VEHICLE
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|
|
Patent #:
|
|
Issue Dt:
|
01/24/2017
|
Application #:
|
14695091
|
Filing Dt:
|
04/24/2015
|
Publication #:
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|
Pub Dt:
|
10/27/2016
| | | | |
Title:
|
SYSTEMS AND METHODS FOR CONTROLLING INTEGRATED CIRCUIT CHIP TEMPERATURE USING TIMING CLOSURE-BASED ADAPTIVE FREQUENCY SCALING
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|
|
Patent #:
|
|
Issue Dt:
|
09/12/2017
|
Application #:
|
14695112
|
Filing Dt:
|
04/24/2015
|
Publication #:
|
|
Pub Dt:
|
10/27/2016
| | | | |
Title:
|
PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTAGE BINNING
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14695113
|
Filing Dt:
|
04/24/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
ELECTRONIC FUSE WITH RESISTIVE HEATER
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14695215
|
Filing Dt:
|
04/24/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
DIRECTED SURFACE FUNCTIONALIZATION ON SELECTED SURFACE AREAS OF TOPOGRAPHICAL FEATURES WITH NANOMETER RESOLUTION
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|
|
Patent #:
|
|
Issue Dt:
|
07/12/2016
|
Application #:
|
14696034
|
Filing Dt:
|
04/24/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
DOUBLE MIRROR STRUCTURE FOR WAVELENGTH DIVISION MULTIPLEXING WITH POLYMER WAVEGUIDES
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|
|
Patent #:
|
|
Issue Dt:
|
08/02/2016
|
Application #:
|
14696534
|
Filing Dt:
|
04/27/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
FINFET DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2016
|
Application #:
|
14696605
|
Filing Dt:
|
04/27/2015
|
Publication #:
|
|
Pub Dt:
|
08/20/2015
| | | | |
Title:
|
A MANUFACTURING PROCESS FOR FINFET DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
07/12/2016
|
Application #:
|
14696693
|
Filing Dt:
|
04/27/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE
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|
|
Patent #:
|
|
Issue Dt:
|
11/01/2016
|
Application #:
|
14696736
|
Filing Dt:
|
04/27/2015
|
Publication #:
|
|
Pub Dt:
|
09/17/2015
| | | | |
Title:
|
MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2016
|
Application #:
|
14696843
|
Filing Dt:
|
04/27/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
WAVELENGTH DIVISION MULTIPLEXING WITH MULTI-CORE FIBER
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14697991
|
Filing Dt:
|
04/28/2015
|
Publication #:
|
|
Pub Dt:
|
08/20/2015
| | | | |
Title:
|
Self-Aligned III-V MOSFET Fabrication With In-Situ III-V Epitaxy And In-Situ Metal Epitaxy and Contact Formation
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|
|
Patent #:
|
|
Issue Dt:
|
08/30/2016
|
Application #:
|
14698948
|
Filing Dt:
|
04/29/2015
|
Title:
|
ALTERNATE DUAL DAMASCENE METHOD FOR FORMING INTERCONNECTS
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|
|
Patent #:
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|
Issue Dt:
|
06/27/2017
|
Application #:
|
14699015
|
Filing Dt:
|
04/29/2015
|
Publication #:
|
|
Pub Dt:
|
11/03/2016
| | | | |
Title:
|
PHOTODETECTOR AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2016
|
Application #:
|
14699034
|
Filing Dt:
|
04/29/2015
|
Title:
|
SERIES-CONNECTED NANOWIRE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
14699580
|
Filing Dt:
|
04/29/2015
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
Title:
|
TAPE HEAD WITH THERMAL TAPE-HEAD DISTANCE SENSOR
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14699859
|
Filing Dt:
|
04/29/2015
|
Publication #:
|
|
Pub Dt:
|
08/20/2015
| | | | |
Title:
|
FABRICATION OF FIELD-EFFECT TRANSISTORS WITH ATOMIC LAYER DOPING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2016
|
Application #:
|
14700147
|
Filing Dt:
|
04/30/2015
|
Publication #:
|
|
Pub Dt:
|
09/17/2015
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH ON CHIP PLANAR DIODE AND CMOS DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14700254
|
Filing Dt:
|
04/30/2015
|
Publication #:
|
|
Pub Dt:
|
11/03/2016
| | | | |
Title:
|
INTELLIGENT WARDROBE PROGRAM
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|
|
Patent #:
|
|
Issue Dt:
|
10/17/2017
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Application #:
|
14700402
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Filing Dt:
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04/30/2015
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Publication #:
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|
Pub Dt:
|
11/03/2016
| | | | |
Title:
|
ON-CHIP USABLE LIFE DEPLETION METER AND ASSOCIATED METHOD
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|
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Patent #:
|
|
Issue Dt:
|
03/29/2016
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Application #:
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14700744
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Filing Dt:
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04/30/2015
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Publication #:
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Pub Dt:
|
08/27/2015
| | | | |
Title:
|
TUNABLE FILTER STRUCTURES AND DESIGN STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
02/07/2017
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Application #:
|
14700850
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Filing Dt:
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04/30/2015
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Publication #:
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Pub Dt:
|
11/19/2015
| | | | |
Title:
|
AXIOCENTRIC SCRUBBING LAND GRID ARRAY CONTACTS AND METHODS FOR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2018
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Application #:
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14701371
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Filing Dt:
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04/30/2015
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Publication #:
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Pub Dt:
|
01/14/2016
| | | | |
Title:
|
MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
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14701605
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Filing Dt:
|
05/01/2015
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Publication #:
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Pub Dt:
|
08/20/2015
| | | | |
Title:
|
LATERAL-DIMENSION-REDUCING METALLIC HARD MASK ETCH
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|
|
Patent #:
|
|
Issue Dt:
|
03/15/2016
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Application #:
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14701910
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Filing Dt:
|
05/01/2015
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Publication #:
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Pub Dt:
|
10/15/2015
| | | | |
Title:
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PROVIDING ACCESS CONTROL FOR PUBLIC AND PRIVATE DOCUMENT FIELDS
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
14702794
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Filing Dt:
|
05/04/2015
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Publication #:
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Pub Dt:
|
08/20/2015
| | | | |
Title:
|
REDUNDANT VIA STRUCTURE FOR METAL FUSE APPLICATIONS
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|
|
Patent #:
|
|
Issue Dt:
|
02/21/2017
|
Application #:
|
14702984
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Filing Dt:
|
05/04/2015
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Publication #:
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|
Pub Dt:
|
11/10/2016
| | | | |
Title:
|
SILVER ALLOYING POST-CHIP JOIN
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2016
|
Application #:
|
14705397
|
Filing Dt:
|
05/06/2015
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Publication #:
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Pub Dt:
|
08/20/2015
| | | | |
Title:
|
ON-CHIP DIODE WITH FULLY DEPLETED SEMICONDUTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2016
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Application #:
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14705425
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Filing Dt:
|
05/06/2015
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Publication #:
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|
Pub Dt:
|
08/20/2015
| | | | |
Title:
|
HETEROGENEOUS INTEGRATION OF GROUP III NITRIDE ON SILICON FOR ADVANCED INTEGRATED CIRCUITS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14706495
|
Filing Dt:
|
05/07/2015
|
Publication #:
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|
Pub Dt:
|
08/27/2015
| | | | |
Title:
|
SOLID STATE NANOPORE DEVICES AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2017
|
Application #:
|
14707442
|
Filing Dt:
|
05/08/2015
|
Publication #:
|
|
Pub Dt:
|
11/10/2016
| | | | |
Title:
|
INDUCING DEVICE VARIATION FOR SECURITY APPLICATIONS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14707775
|
Filing Dt:
|
05/08/2015
|
Publication #:
|
|
Pub Dt:
|
09/03/2015
| | | | |
Title:
|
BURIED-CHANNEL FIELD-EFFECT TRANSISTORS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14707822
|
Filing Dt:
|
05/08/2015
|
Publication #:
|
|
Pub Dt:
|
09/03/2015
| | | | |
Title:
|
ENABLING ENHANCED RELIABILITY AND MOBILITY FOR REPLACEMENT GATE PLANAR AND FINFET STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2017
|
Application #:
|
14707923
|
Filing Dt:
|
05/08/2015
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
Title:
|
BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2016
|
Application #:
|
14708753
|
Filing Dt:
|
05/11/2015
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
Title:
|
PROACTIVE RISK ANALYSIS AND GOVERNANCE OF UPGRADE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2015
|
Application #:
|
14708755
|
Filing Dt:
|
05/11/2015
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
Title:
|
INTEGRATED CIRCUIT STRUCTURES HAVING OFF-AXIS IN-HOLE CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2015
|
Application #:
|
14710935
|
Filing Dt:
|
05/13/2015
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
Title:
|
METHOD OF SELF-CORRECTING POWER GRID FOR SEMICONDUCTOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
14711069
|
Filing Dt:
|
05/13/2015
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES WITH PAIR(S) OF VERTICAL FIELD EFFECT TRANSISTORS, EACH PAIR HAVING A SHARED SOURCE/DRAIN REGION AND METHODS OF FORMING THE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2017
|
Application #:
|
14711109
|
Filing Dt:
|
05/13/2015
|
Publication #:
|
|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
CHAMFERED CORNER CRACKSTOP FOR AN INTEGRATED CIRCUIT CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2016
|
Application #:
|
14711872
|
Filing Dt:
|
05/14/2015
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
Title:
|
SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2017
|
Application #:
|
14712092
|
Filing Dt:
|
05/14/2015
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
Title:
|
BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2017
|
Application #:
|
14712397
|
Filing Dt:
|
05/14/2015
|
Publication #:
|
|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
DUAL SHALLOW TRENCH ISOLATION (STI) STRUCTURE FOR FIELD EFFECT TRANSISTOR (FET)
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
14713327
|
Filing Dt:
|
05/15/2015
|
Publication #:
|
|
Pub Dt:
|
09/03/2015
| | | | |
Title:
|
INTEGRATED SEMICONDUCTOR DEVICES WITH SINGLE CRYSTALLINE BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2017
|
Application #:
|
14713626
|
Filing Dt:
|
05/15/2015
|
Publication #:
|
|
Pub Dt:
|
09/03/2015
| | | | |
Title:
|
CIRCUIT FOR DETECTING STRUCTURAL DEFECTS IN AN INTEGRATED CIRCUIT CHIP, METHODS OF USE AND MANUFACTURE AND DESIGN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2017
|
Application #:
|
14714779
|
Filing Dt:
|
05/18/2015
|
Publication #:
|
|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
SHALLOW TRENCH ISOLATION STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2016
|
Application #:
|
14715693
|
Filing Dt:
|
05/19/2015
|
Publication #:
|
|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
SILICON-ON-INSULATOR HEAT SINK
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
14716236
|
Filing Dt:
|
05/19/2015
|
Publication #:
|
|
Pub Dt:
|
10/01/2015
| | | | |
Title:
|
REDUCING WAFER BONDING MISALIGNMENT BY VARYING THERMAL TREATMENT PRIOR TO BONDING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2017
|
Application #:
|
14716300
|
Filing Dt:
|
05/19/2015
|
Publication #:
|
|
Pub Dt:
|
09/17/2015
| | | | |
Title:
|
SUBSTRATE BONDING WITH DIFFUSION BARRIER STRUCTURES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14716959
|
Filing Dt:
|
05/20/2015
|
Publication #:
|
|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
FACILITATING CHIP DICING FOR METAL-METAL BONDING AND HYBRID WAFER BONDING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2016
|
Application #:
|
14718128
|
Filing Dt:
|
05/21/2015
|
Publication #:
|
|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
EMBEDDED ON-CHIP SECURITY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2016
|
Application #:
|
14718331
|
Filing Dt:
|
05/21/2015
|
Publication #:
|
|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
FILE SYSTEM LEVEL DATA PROTECTION DURING POTENTIAL SECURITY BREACH
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2016
|
Application #:
|
14718466
|
Filing Dt:
|
05/21/2015
|
Publication #:
|
|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
CONTROLLED METAL EXTRUSION OPENING IN SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING
|
|