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Reel/Frame:049490/0001   Pages: 892
Recorded: 11/29/2018
Conveyance: SECURITY AGREEMENT
Total properties: 13706
Page 15 of 138
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138
1
Patent #:
7052575
Issue Dt:
05/30/2006
Application #:
09845454
Filing Dt:
04/30/2001
Title:
SYSTEM AND METHOD FOR ACTIVE CONTROL OF ETCH PROCESS
2
Patent #:
6753266
Issue Dt:
06/22/2004
Application #:
09845654
Filing Dt:
04/30/2001
Title:
METHOD OF ENHANCING GATE PATTERNING PROPERTIES WITH REFLECTIVE HARD MASK
3
Patent #:
6440806
Issue Dt:
08/27/2002
Application #:
09845859
Filing Dt:
04/30/2001
Title:
METHOD FOR PRODUCING METAL-SEMICONDUCTOR COMPOUND REGIONS ON SEMICONDUCTOR DEVICES
4
Patent #:
6458686
Issue Dt:
10/01/2002
Application #:
09845980
Filing Dt:
04/30/2001
Title:
INVERSE INTEGRATED CIRCUIT FABRICATION PROCESS
5
Patent #:
6506677
Issue Dt:
01/14/2003
Application #:
09846186
Filing Dt:
05/02/2001
Title:
METHOD OF FORMING CAPPED COPPER INTERCONNECTS WITH REDUCED HILLOCK FORMATION AND IMPROVED ELECTROMIGRATION RESISTANCE
6
Patent #:
6562416
Issue Dt:
05/13/2003
Application #:
09846187
Filing Dt:
05/02/2001
Publication #:
US20020162736
Pub Dt:
11/07/2002
Title:
METHOD OF FORMING LOW RESISTANCE VIAS
7
Patent #:
6611023
Issue Dt:
08/26/2003
Application #:
09846502
Filing Dt:
05/01/2001
Title:
FIELD EFFECT TRANSISTOR WITH SELF ALLIGNED DOUBLE GATE AND METHOD OF FORMING SAME
8
Patent #:
6432822
Issue Dt:
08/13/2002
Application #:
09846611
Filing Dt:
05/02/2001
Title:
METHOD OF IMPROVING ELECTROMIGRATION RESISTANCE OF CAPPED CU
9
Patent #:
6620671
Issue Dt:
09/16/2003
Application #:
09846813
Filing Dt:
05/01/2001
Title:
METHOD OF FABRICATING TRANSISTOR HAVING A SINGLE CRYSTALLINE GATE CONDUCTOR
10
Patent #:
6448613
Issue Dt:
09/10/2002
Application #:
09846958
Filing Dt:
05/01/2001
Title:
FABRICATION OF A FIELD EFFECT TRANSISTOR WITH MINIMIZED PARASITIC MILLER CAPACITANCE
11
Patent #:
6798028
Issue Dt:
09/28/2004
Application #:
09847622
Filing Dt:
05/02/2001
Publication #:
US20020056859
Pub Dt:
05/16/2002
Title:
FIELD EFFECT TRANSISTOR WITH REDUCED GATE DELAY AND METHOD OF FABRICATING THE SAME
12
Patent #:
6593037
Issue Dt:
07/15/2003
Application #:
09847803
Filing Dt:
05/02/2001
Title:
EUV MASK OR RETICLE HAVING REDUCED REFLECTIONS
13
Patent #:
6566718
Issue Dt:
05/20/2003
Application #:
09848085
Filing Dt:
05/03/2001
Publication #:
US20020056879
Pub Dt:
05/16/2002
Title:
FIELD EFFECT TRANSISTOR WITH AN IMPROVED GATE CONTACT
14
Patent #:
6780499
Issue Dt:
08/24/2004
Application #:
09848153
Filing Dt:
05/03/2001
Publication #:
US20020164891
Pub Dt:
11/07/2002
Title:
ORDERED TWO-PHASE DIELECTRIC FILM, AND SEMICONDUCTOR DEVICE CONTAINING THE SAME
15
Patent #:
6577154
Issue Dt:
06/10/2003
Application #:
09848454
Filing Dt:
05/03/2001
Publication #:
US20020163360
Pub Dt:
11/07/2002
Title:
CONSTANT IMPEDANCE DRIVER FOR HIGH SPEED INTERFACE
16
Patent #:
6521949
Issue Dt:
02/18/2003
Application #:
09848508
Filing Dt:
05/03/2001
Publication #:
US20020164841
Pub Dt:
11/07/2002
Title:
SOI TRANSISTOR WITH POLYSILICON SEED
17
Patent #:
6498397
Issue Dt:
12/24/2002
Application #:
09848979
Filing Dt:
05/04/2001
Title:
SEED LAYER WITH ANNEALED REGION FOR INTEGRATED CIRCUIT INTERCONNECTS
18
Patent #:
6410461
Issue Dt:
06/25/2002
Application #:
09849357
Filing Dt:
05/07/2001
Title:
METHOD OF DEPOSITING SION WITH REDUCED DEFECTS
19
Patent #:
6509613
Issue Dt:
01/21/2003
Application #:
09849494
Filing Dt:
05/04/2001
Title:
SELF-ALIGNED FLOATING BODY CONTROL FOR SOI DEVICE THROUGH LEAKAGE ENHANCED BURIED OXIDE
20
Patent #:
6821890
Issue Dt:
11/23/2004
Application #:
09849530
Filing Dt:
05/07/2001
Publication #:
US20010023987
Pub Dt:
09/27/2001
Title:
METHOD FOR IMPROVING ADHESION TO COPPER
21
Patent #:
6512244
Issue Dt:
01/28/2003
Application #:
09850392
Filing Dt:
05/07/2001
Title:
SOI DEVICE WITH STRUCTURE FOR ENHANCING CARRIER RECOMBINATION AND METHOD OF FABRICATING SAME
22
Patent #:
7122863
Issue Dt:
10/17/2006
Application #:
09850393
Filing Dt:
05/07/2001
Title:
SOI DEVICE WITH STRUCTURE FOR ENHANCING CARRIER RECOMBINATION AND METHOD OF FABRICATING SAME
23
Patent #:
6593227
Issue Dt:
07/15/2003
Application #:
09851199
Filing Dt:
05/08/2001
Title:
METHOD AND APPARATUS FOR PLANARIZING SURFACES OF SEMICONDUCTOR DEVICE CONDUCTIVE LAYERS
24
Patent #:
7065654
Issue Dt:
06/20/2006
Application #:
09852372
Filing Dt:
05/10/2001
Title:
SECURE EXECUTION BOX
25
Patent #:
6410410
Issue Dt:
06/25/2002
Application #:
09852535
Filing Dt:
05/10/2001
Publication #:
US20020061626
Pub Dt:
05/23/2002
Title:
METHOD OF FORMING LIGHTLY DOPED REGIONS IN A SEMICONDUCTOR DEVICE
26
Patent #:
6862641
Issue Dt:
03/01/2005
Application #:
09853234
Filing Dt:
05/11/2001
Title:
INTERRUPTABLE AND RE-ENTERABLE SYSTEM MANAGEMENT MODE PROGRAMMING CODE
27
Patent #:
6821715
Issue Dt:
11/23/2004
Application #:
09853345
Filing Dt:
05/10/2001
Publication #:
US20020167764
Pub Dt:
11/14/2002
Title:
FULLY UNDERCUT RESIST SYSTEMS USING E-BEAM LITHOGRAPHY FOR THE FABRICATION OF HIGH RESOLUTION MR SENSORS
28
Patent #:
7216362
Issue Dt:
05/08/2007
Application #:
09853395
Filing Dt:
05/11/2001
Title:
ENHANCED SECURITY AND MANAGEABILITY USING SECURE STORAGE IN A PERSONAL COMPUTER SYSTEM
29
Patent #:
6832317
Issue Dt:
12/14/2004
Application #:
09853437
Filing Dt:
05/11/2001
Title:
PERSONAL COMPUTER SECURITY MECHANSIM
30
Patent #:
6823451
Issue Dt:
11/23/2004
Application #:
09853447
Filing Dt:
05/11/2001
Title:
INTEGRATED CIRCUIT FOR SECURITY AND MANAGEABILITY
31
Patent #:
6469949
Issue Dt:
10/22/2002
Application #:
09854049
Filing Dt:
05/11/2001
Publication #:
US20020167855
Pub Dt:
11/14/2002
Title:
FUSE LATCH ARRAY SYSTEM FOR AN EMBEDDED DRAM HAVING A MICRO-CELL ARCHITECTURE
32
Patent #:
7035335
Issue Dt:
04/25/2006
Application #:
09854586
Filing Dt:
05/11/2001
Title:
TRANSPORT STREAM PARSER
33
Patent #:
6501675
Issue Dt:
12/31/2002
Application #:
09854987
Filing Dt:
05/14/2001
Publication #:
US20020176275
Pub Dt:
11/28/2002
Title:
ALTERNATING REFERENCE WORDLINE SCHEME FOR FAST DRAM
34
Patent #:
6941414
Issue Dt:
09/06/2005
Application #:
09855240
Filing Dt:
05/15/2001
Publication #:
US20020174291
Pub Dt:
11/21/2002
Title:
HIGH SPEED EMBEDDED DRAM WITH SRAM-LIKE INTERFACE
35
Patent #:
6823087
Issue Dt:
11/23/2004
Application #:
09855871
Filing Dt:
05/15/2001
Title:
PARALLEL EDGE FILTERS IN VIDEO CODEC
36
Patent #:
6726996
Issue Dt:
04/27/2004
Application #:
09858687
Filing Dt:
05/16/2001
Publication #:
US20020172811
Pub Dt:
11/21/2002
Title:
LAMINATED DIFFUSION BARRIER
37
Patent #:
6673287
Issue Dt:
01/06/2004
Application #:
09858919
Filing Dt:
05/16/2001
Publication #:
US20020172895
Pub Dt:
11/21/2002
Title:
VAPOR PHASE SURFACE MODIFICATION OF COMPOSITE SUBSTRATES TO FORM A MOLECULARLY THIN RELEASE LAYER
38
Patent #:
6808974
Issue Dt:
10/26/2004
Application #:
09859021
Filing Dt:
05/15/2001
Publication #:
US20020173105
Pub Dt:
11/21/2002
Title:
CMOS STRUCTURE WITH MAXIMIZED POLYSILICON GATE ACTIVATION AND A METHOD FOR SELECTIVELY MAXIMIZING DOPING ACTIVATION IN GATE, EXTENSION, AND SOURCE/DRAIN REGIONS
39
Patent #:
6519174
Issue Dt:
02/11/2003
Application #:
09859145
Filing Dt:
05/16/2001
Publication #:
US20020172067
Pub Dt:
11/21/2002
Title:
EARLY WRITE DRAM ARCHITECTURE WITH VERTICALLY FOLDED BITLINES
40
Patent #:
6493240
Issue Dt:
12/10/2002
Application #:
09859252
Filing Dt:
05/17/2001
Publication #:
US20010046129
Pub Dt:
11/29/2001
Title:
INTERPOSER FOR CONNECTING TWO SUBSTRATES AND RESULTING ASSEMBLY
41
Patent #:
6725337
Issue Dt:
04/20/2004
Application #:
09859290
Filing Dt:
05/16/2001
Title:
METHOD AND SYSTEM FOR SPECULATIVELY INVALIDATING LINES IN A CACHE
42
Patent #:
6399493
Issue Dt:
06/04/2002
Application #:
09860141
Filing Dt:
05/17/2001
Title:
METHOD OF SILICIDE FORMATION BY SILICON PRETREATMENT
43
Patent #:
6464563
Issue Dt:
10/15/2002
Application #:
09860226
Filing Dt:
05/18/2001
Title:
METHOD AND APPARATUS FOR DETECTING DISHING IN A POLISHED LAYER
44
Patent #:
6727873
Issue Dt:
04/27/2004
Application #:
09860264
Filing Dt:
05/18/2001
Publication #:
US20020171619
Pub Dt:
11/21/2002
Title:
REFLECTIVE ELECTROPHORETIC DISPLAY WITH STACKED COLOR CELLS
45
Patent #:
6680726
Issue Dt:
01/20/2004
Application #:
09860265
Filing Dt:
05/18/2001
Publication #:
US20020171620
Pub Dt:
11/21/2002
Title:
TRANSMISSIVE ELECTROPHORETIC DISPLAY WITH STACKED COLOR CELLS
46
Patent #:
6563736
Issue Dt:
05/13/2003
Application #:
09860736
Filing Dt:
05/18/2001
Publication #:
US20020171101
Pub Dt:
11/21/2002
Title:
FLASH MEMORY STRUCTURE HAVING DOUBLE CELLED ELEMENTS AND METHOD FOR FABRICATING THE SAME
47
Patent #:
6753252
Issue Dt:
06/22/2004
Application #:
09861253
Filing Dt:
05/18/2001
Publication #:
US20020173094
Pub Dt:
11/21/2002
Title:
CONTACT PLUG FORMATION FOR DEVICES WITH STACKED CAPACITORS
48
Patent #:
6486037
Issue Dt:
11/26/2002
Application #:
09861593
Filing Dt:
05/21/2001
Publication #:
US20010033002
Pub Dt:
10/25/2001
Title:
CONTROL OF BURIED OXIDE QUALITY IN LOW DOSE SIMOX
49
Patent #:
6602757
Issue Dt:
08/05/2003
Application #:
09861594
Filing Dt:
05/21/2001
Publication #:
US20020171106
Pub Dt:
11/21/2002
Title:
SELF-ADJUSTING THICKNESS UNIFORMITY IN SOI BY HIGH-TEMPERATURE OXIDATION OF SIMOX AND BONDED SOI
50
Patent #:
6541356
Issue Dt:
04/01/2003
Application #:
09861596
Filing Dt:
05/21/2001
Publication #:
US20020173123
Pub Dt:
11/21/2002
Title:
THE ULTIMATE SIMOX
51
Patent #:
6556477
Issue Dt:
04/29/2003
Application #:
09861788
Filing Dt:
05/21/2001
Publication #:
US20020172074
Pub Dt:
11/21/2002
Title:
INTEGRATED CHIP HAVING SRAM, DRAM AND FLASH MEMORY AND METHOD FOR FABRICATING THE SAME
52
Patent #:
6756646
Issue Dt:
06/29/2004
Application #:
09862372
Filing Dt:
05/22/2001
Publication #:
US20030190780
Pub Dt:
10/09/2003
Title:
OXYNITRIDE GATE DIELECTRIC AND METHOD OF FORMING
53
Patent #:
6832361
Issue Dt:
12/14/2004
Application #:
09862427
Filing Dt:
05/21/2001
Publication #:
US20020174409
Pub Dt:
11/21/2002
Title:
SYSTEM AND METHOD FOR ANALYZING POWER DISTRIBUTION USING STATIC TIMING ANALYSIS
54
Patent #:
6549990
Issue Dt:
04/15/2003
Application #:
09862687
Filing Dt:
05/21/2001
Publication #:
US20010037434
Pub Dt:
11/01/2001
Title:
STORE TO LOAD FORWARDING USING A DEPENDENCY LINK FILE
55
Patent #:
6777733
Issue Dt:
08/17/2004
Application #:
09862827
Filing Dt:
05/22/2001
Publication #:
US20020055224
Pub Dt:
05/09/2002
Title:
METHOD FOR FORMING DUAL WORKFUNCTION HIGH-PERFORMANCE SUPPORT MOSFETS IN EDRAM ARRAYS
56
Patent #:
6677170
Issue Dt:
01/13/2004
Application #:
09863596
Filing Dt:
05/23/2001
Title:
METHOD FOR DETERMINING PROCESS LAYER THICKNESS USING SCATTEROMETRY MEASUREMENTS
57
Patent #:
6657716
Issue Dt:
12/02/2003
Application #:
09863598
Filing Dt:
05/23/2001
Title:
METHOD AND APPARATUS FOR DETECTING NECKING OVER FIELD/ACTIVE TRANSITIONS
58
Patent #:
6341079
Issue Dt:
01/22/2002
Application #:
09863848
Filing Dt:
05/23/2001
Title:
Content addressable memory device
59
Patent #:
6728916
Issue Dt:
04/27/2004
Application #:
09863952
Filing Dt:
05/23/2001
Publication #:
US20020178416
Pub Dt:
11/28/2002
Title:
HIERARCHICAL BUILT-IN SELF-TEST FOR SYSTEM-ON-CHIP DESIGN
60
Patent #:
6498383
Issue Dt:
12/24/2002
Application #:
09863980
Filing Dt:
05/23/2001
Publication #:
US20020177270
Pub Dt:
11/28/2002
Title:
OXYNITRIDE SHALLOW TRENCH ISOLATION AND METHOD OF FORMATION
61
Patent #:
6725121
Issue Dt:
04/20/2004
Application #:
09864692
Filing Dt:
05/24/2001
Title:
METHOD AND APPARATUS FOR USING A DYNAMIC CONTROL MODEL TO COMPENSATE FOR A PROCESS INTERRUPT
62
Patent #:
6645867
Issue Dt:
11/11/2003
Application #:
09864974
Filing Dt:
05/24/2001
Publication #:
US20020175146
Pub Dt:
11/28/2002
Title:
STRUCTURE AND METHOD TO PRESERVE STI DURING ETCHING
63
Patent #:
6597233
Issue Dt:
07/22/2003
Application #:
09865830
Filing Dt:
05/25/2001
Publication #:
US20020175717
Pub Dt:
11/28/2002
Title:
DIFFERENTIAL SCSI DRIVER RISE TIME AND AMPLITUDE CONTROL CIRCUIT
64
Patent #:
6472740
Issue Dt:
10/29/2002
Application #:
09867902
Filing Dt:
05/30/2001
Title:
SELF-SUPPORTING AIR BRIDGE INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS
65
Patent #:
6438051
Issue Dt:
08/20/2002
Application #:
09870559
Filing Dt:
05/31/2001
Title:
STABILIZED DIRECT SENSING MEMORY ARCHITECTURE
66
Patent #:
6933752
Issue Dt:
08/23/2005
Application #:
09870623
Filing Dt:
05/31/2001
Publication #:
US20020180480
Pub Dt:
12/05/2002
Title:
METHOD AND APPARATUS FOR INTERFACE SIGNALING USING SINGLE-ENDED AND DIFFERENTIAL DATA SIGNALS
67
Patent #:
6552944
Issue Dt:
04/22/2003
Application #:
09870755
Filing Dt:
05/31/2001
Publication #:
US20020181307
Pub Dt:
12/05/2002
Title:
SINGLE BITLINE DIRECT SENSING ARCHITECTURE FOR HIGH SPEED MEMORY DEVICE
68
Patent #:
6458610
Issue Dt:
10/01/2002
Application #:
09871015
Filing Dt:
05/31/2001
Title:
METHOD AND APPARATUS FOR OPTICAL FILM STACK FAULT DETECTION
69
Patent #:
6528851
Issue Dt:
03/04/2003
Application #:
09871191
Filing Dt:
05/31/2001
Title:
POST-SILICIDATION IMPLANT FOR INTRODUCING RECOMBINATION CENTER IN BODY OF SOI MOSFET
70
Patent #:
6545226
Issue Dt:
04/08/2003
Application #:
09871556
Filing Dt:
05/31/2001
Publication #:
US20020179331
Pub Dt:
12/05/2002
Title:
PRINTED WIRING BOARD INTERPOSER SUB-ASSEMBLY
71
Patent #:
6746578
Issue Dt:
06/08/2004
Application #:
09871557
Filing Dt:
05/31/2001
Publication #:
US20020179450
Pub Dt:
12/05/2002
Title:
SELECTIVE SHIELD/MATERIAL FLOW MECHANISM
72
Patent #:
7224063
Issue Dt:
05/29/2007
Application #:
09871883
Filing Dt:
06/01/2001
Publication #:
US20020182855
Pub Dt:
12/05/2002
Title:
DUAL-DAMASCENE METALLIZATION INTERCONNECTION
73
Patent #:
6528884
Issue Dt:
03/04/2003
Application #:
09872328
Filing Dt:
06/01/2001
Title:
CONFORMAL ATOMIC LINER LAYER IN AN INTERGRATED CIRCUIT INTERCONNECT
74
Patent #:
6482656
Issue Dt:
11/19/2002
Application #:
09873667
Filing Dt:
06/04/2001
Title:
METHOD OF ELECTROCHEMICAL FORMATION OF HIGH TC SUPERCONDUCTING DAMASCENE INTERCONNECT FOR INTEGRATED CIRCUIT
75
Patent #:
6528892
Issue Dt:
03/04/2003
Application #:
09874196
Filing Dt:
06/05/2001
Publication #:
US20020180061
Pub Dt:
12/05/2002
Title:
LAND GRID ARRAY STIFFENER USE WITH FLEXIBLE CHIP CARRIERS
76
Patent #:
6592939
Issue Dt:
07/15/2003
Application #:
09875596
Filing Dt:
06/06/2001
Title:
SYSTEM FOR AND METHOD OF USING DEVELOPER AS A SOLVENT TO SPREAD PHOTORESIST FASTER AND REDUCE PHOTORESIST CONSUMPTION
77
Patent #:
6724225
Issue Dt:
04/20/2004
Application #:
09876631
Filing Dt:
06/07/2001
Publication #:
US20020186050
Pub Dt:
12/12/2002
Title:
LOGIC CIRCUIT FOR TRUE AND COMPLEMENT SIGNAL GENERATOR
78
Patent #:
8009584
Issue Dt:
08/30/2011
Application #:
09877120
Filing Dt:
06/11/2001
Title:
SYSTEM AND METHOD FOR IMPLEMENTING AN IRC ACROSS MULTIPLE NETWORK DEVICES
79
Patent #:
6656313
Issue Dt:
12/02/2003
Application #:
09878474
Filing Dt:
06/11/2001
Publication #:
US20020195197
Pub Dt:
12/26/2002
Title:
STRUCTURE AND METHOD FOR IMPROVED ADHESION BETWEEN TWO POLYMER FILMS
80
Patent #:
6512684
Issue Dt:
01/28/2003
Application #:
09878525
Filing Dt:
06/11/2001
Publication #:
US20020196648
Pub Dt:
12/26/2002
Title:
CONTENT ADDRESSABLE MEMORY HAVING CASCADED SUB-ENTRY ARCHITECTURE
81
Patent #:
6492684
Issue Dt:
12/10/2002
Application #:
09878681
Filing Dt:
06/11/2001
Publication #:
US20020043686
Pub Dt:
04/18/2002
Title:
SILICON-ON-INSULATOR CHIP HAVING AN ISOLATION BARRIER FOR RELIABILITY
82
Patent #:
6686617
Issue Dt:
02/03/2004
Application #:
09878804
Filing Dt:
06/11/2001
Publication #:
US20010031535
Pub Dt:
10/18/2001
Title:
SEMICONDUCTOR CHIP HAVING BOTH COMPACT MEMORY AND HIGH PERFORMANCE LOGIC
83
Patent #:
6573539
Issue Dt:
06/03/2003
Application #:
09878930
Filing Dt:
06/12/2001
Publication #:
US20020020852
Pub Dt:
02/21/2002
Title:
HETEROJUNCTION BIPOLAR TRANSISTOR WITH SILICON-GERMANIUM BASE
84
Patent #:
6891231
Issue Dt:
05/10/2005
Application #:
09879105
Filing Dt:
06/13/2001
Publication #:
US20020190302
Pub Dt:
12/19/2002
Title:
COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) GATE STACK WITH HIGH DIELECTRIC CONSTANT GATE DIELECTRIC AND INTEGRATED DIFFUSION BARRIER
85
Patent #:
6529282
Issue Dt:
03/04/2003
Application #:
09879338
Filing Dt:
06/11/2001
Title:
METHOD OF CONTROLLING PHOTOLITHOGRAPHY PROCESSES BASED UPON SCATTEROMETRIC MEASUREMENTS OF PHOTORESIST THICKNESS, AND SYSTEM FOR ACCOMPLISHING SAME
86
Patent #:
6759282
Issue Dt:
07/06/2004
Application #:
09879530
Filing Dt:
06/12/2001
Publication #:
US20020185684
Pub Dt:
12/12/2002
Title:
METHOD AND STRUCTURE FOR BURIED CIRCUITS AND DEVICES
87
Patent #:
6635542
Issue Dt:
10/21/2003
Application #:
09879579
Filing Dt:
06/12/2001
Publication #:
US20020187612
Pub Dt:
12/12/2002
Title:
COMPACT BODY FOR SILICON-ON-INSULATOR TRANSISTORS REQUIRING NO ADDITIONAL LAYOUT AREA
88
Patent #:
6876557
Issue Dt:
04/05/2005
Application #:
09879653
Filing Dt:
06/12/2001
Publication #:
US20020188797
Pub Dt:
12/12/2002
Title:
UNIFIED SRAM CACHE SYSTEM FOR AN EMBEDDED DRAM SYSTEM HAVING A MICRO-CELL ARCHITECTURE
89
Patent #:
6717212
Issue Dt:
04/06/2004
Application #:
09879724
Filing Dt:
06/12/2001
Publication #:
US20020185685
Pub Dt:
12/12/2002
Title:
LEAKY, THERMALLY CONDUCTIVE INSULATOR MATERIAL (LTCIM) IN SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE
90
Patent #:
6534865
Issue Dt:
03/18/2003
Application #:
09880219
Filing Dt:
06/12/2001
Title:
METHOD OF ENHANCED FILL OF VIAS AND TRENCHES
91
Patent #:
6597463
Issue Dt:
07/22/2003
Application #:
09880591
Filing Dt:
06/13/2001
Title:
SYSTEM TO DETERMINE SUITABILITY OF SION ARC SURFACE FOR DUV RESIST PATTERNING
92
Patent #:
6538932
Issue Dt:
03/25/2003
Application #:
09880598
Filing Dt:
06/13/2001
Publication #:
US20020191448
Pub Dt:
12/19/2002
Title:
TIMING CIRCUIT AND METHOD FOR A COMPILABLE DRAM
93
Patent #:
6630362
Issue Dt:
10/07/2003
Application #:
09880990
Filing Dt:
06/13/2001
Title:
METHOD AND APPARATUS FOR PERFORMING TRENCH DEPTH ANALYSIS
94
Patent #:
6592747
Issue Dt:
07/15/2003
Application #:
09881817
Filing Dt:
06/18/2001
Publication #:
US20030000850
Pub Dt:
01/02/2003
Title:
METHOD OF CONTROLLING ADDITIVES IN COPPER PLATING BATHS
95
Patent #:
6492258
Issue Dt:
12/10/2002
Application #:
09881831
Filing Dt:
06/14/2001
Title:
METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25MM AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY
96
Patent #:
6440807
Issue Dt:
08/27/2002
Application #:
09882095
Filing Dt:
06/15/2001
Title:
SURFACE ENGINEERING TO PREVENT EPI GROWTH ON GATE POLY DURING SELECTIVE EPI PROCESSING
97
Patent #:
6511873
Issue Dt:
01/28/2003
Application #:
09882749
Filing Dt:
06/15/2001
Publication #:
US20020192881
Pub Dt:
12/19/2002
Title:
HIGH-DIELECTRIC CONSTANT INSULATORS FOR FEOL CAPACITORS
98
Patent #:
6662430
Issue Dt:
12/16/2003
Application #:
09883433
Filing Dt:
06/18/2001
Publication #:
US20010030628
Pub Dt:
10/18/2001
Title:
METHOD FOR FORMING AN ANTENNA AND A RADIO FREQUENCY TRANSPONDER
99
Patent #:
6555461
Issue Dt:
04/29/2003
Application #:
09884059
Filing Dt:
06/20/2001
Title:
METHOD OF FORMING LOW RESISTANCE BARRIER ON LOW K INTERCONNECT
100
Patent #:
6537833
Issue Dt:
03/25/2003
Application #:
09885411
Filing Dt:
06/19/2001
Title:
METHOD AND APPARATUS FOR CHARACTERIZING AN INTERCONNECT STRUCTURE PROFILE USING SCATTEROMETRY MEASUREMENTS
Assignor
1
GLOBALFOUNDRIES INC.
Exec Dt:
11/27/2018
Assignee
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
1100 NORTH MARKET STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
CT CORPORATION
4400 EASTON COMMONS WAY
SUITE 125
COLUMBUS, OH 43219

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