|
|
Patent #:
|
|
Issue Dt:
|
10/13/2015
|
Application #:
|
13693865
|
Filing Dt:
|
12/04/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
METHODS AND APPARATUSES FOR REFRESHING MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2016
|
Application #:
|
13693899
|
Filing Dt:
|
12/04/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
METHODS AND APPARATUSES FOR MEMORY TESTING WITH DATA COMPRESSION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13705744
|
Filing Dt:
|
12/05/2012
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
METHOD OF MAKING A MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL STAGGERED LOCAL BIT LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2016
|
Application #:
|
13706851
|
Filing Dt:
|
12/06/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
SETTING A DEFAULT READ SIGNAL BASED ON ERROR CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13707067
|
Filing Dt:
|
12/06/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13708526
|
Filing Dt:
|
12/07/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
VERTICAL SOLID-STATE TRANSDUCERS AND HIGH VOLTAGE SOLID-STATE TRANSDUCERS HAVING BURIED CONTACTS AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13708583
|
Filing Dt:
|
12/07/2012
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
Title:
|
EXPLICIT SKEW INTERFACE FOR REDUCING CROSSTALK AND SIMULTANEOUS SWITCHING NOISE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
13708789
|
Filing Dt:
|
12/07/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
Methods of Forming Vertically-Stacked Structures, and Methods of Forming Vertically-Stacked Memory Cells
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13709792
|
Filing Dt:
|
12/10/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
APPARATUSES AND METHODS FOR UNIT IDENTIFICATION IN A MASTER/SLAVE MEMORY STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13710067
|
Filing Dt:
|
12/10/2012
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
Error-Correcting Code and Process for Fast Read-Error Correction
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
13710559
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
ALIGNMENT OF INSTRUCTIONS AND REPLIES ACROSS MULTIPLE DEVICES IN A CASCADED SYSTEM, USING BUFFERS OF PROGRAMMABLE DEPTHS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2014
|
Application #:
|
13710729
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
METHODS OF FORMING PATTERNS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/2015
|
Application #:
|
13710785
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
Electronic Devices, Memory Devices and Memory Arrays
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13711432
|
Filing Dt:
|
12/11/2012
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
METHODS AND SYSTEMS FOR REMOVING MATERIALS FROM MICROFEATURE WORKPIECES WITH ORGANIC AND/OR NON-AQUEOUS ELECTROLYTIC MEDIA
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2015
|
Application #:
|
13712635
|
Filing Dt:
|
12/12/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
METHOD OF FORMING A PLANAR SURFACE FOR A SEMICONDUCTOR DEVICE STRUCTURE, AND RELATED METHODS OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2015
|
Application #:
|
13712699
|
Filing Dt:
|
12/12/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
METHODS OF SELECTIVELY REMOVING A SUBSTRATE MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2015
|
Application #:
|
13712806
|
Filing Dt:
|
12/12/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
Substrate Mask Patterns, Methods Of Forming A Structure On A Substrate, Methods Of Forming A Square Lattice Pattern From An Oblique Lattice Pattern, And Methods Of Forming A Pattern On A Substrate
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13712820
|
Filing Dt:
|
12/12/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
Methods of Forming A Pattern On A Substrate
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13712830
|
Filing Dt:
|
12/12/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
Methods of Forming A Pattern On A Substrate
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
13712880
|
Filing Dt:
|
12/12/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
ERROR CORRECTING CODES FOR INCREASED STORAGE CAPACITY IN MULTILEVEL MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2014
|
Application #:
|
13713210
|
Filing Dt:
|
12/13/2012
|
Publication #:
|
|
Pub Dt:
|
07/25/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICE STRUCTURES AND ELECTRONIC DEVICES INCLUDING HYBRID CONDUCTIVE VIAS, AND METHODS OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2020
|
Application #:
|
13716287
|
Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
THREE DIMENSIONAL MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13716702
|
Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
Title:
|
PROCESS FOR IMPROVING CRITICAL DIMENSION UNIFORMITY OF INTEGRATED CIRCUIT ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13717465
|
Filing Dt:
|
12/17/2012
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
A MEMORY CELL COMPRISING A FLOATING BODY, A CHANNEL REGION, AND A DIODE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13718801
|
Filing Dt:
|
12/18/2012
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
Title:
|
ENABLE/DISABLE OF MEMORY CHUNKS DURING MEMORY ACCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13720045
|
Filing Dt:
|
12/19/2012
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
Title:
|
FLASH MEMORY HAVING MULTI-LEVEL ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
13721808
|
Filing Dt:
|
12/20/2012
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
Title:
|
METHODS FOR SEGMENTED PROGRAMMING AND MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13722909
|
Filing Dt:
|
12/20/2012
|
Publication #:
|
|
Pub Dt:
|
06/26/2014
| | | | |
Title:
|
Methods Of Forming A Mask And Methods Of Correcting Intra-Field Variation Across A Mask Design Used In Photolithographic Processing
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13723564
|
Filing Dt:
|
12/21/2012
|
Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICE COMPRISING TRANSISTOR STRUCTURES AND METHODS FOR FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13723573
|
Filing Dt:
|
12/21/2012
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
METAL PLATING USING SEED FILM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2016
|
Application #:
|
13723781
|
Filing Dt:
|
12/21/2012
|
Publication #:
|
|
Pub Dt:
|
06/26/2014
| | | | |
Title:
|
MEMORY DEVICES AND THEIR OPERATION HAVING TRIM REGISTERS ASSOCIATED WITH ACCESS OPERATION COMMANDS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13723838
|
Filing Dt:
|
12/21/2012
|
Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
Title:
|
METHOD FOR FORMING NANOFIN TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
13725384
|
Filing Dt:
|
12/21/2012
|
Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
Title:
|
SELF-ALIGNED SEMICONDUCTOR TRENCH STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
|
Application #:
|
13725695
|
Filing Dt:
|
12/21/2012
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
Title:
|
METHOD TO ALIGN MASK PATTERNS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2015
|
Application #:
|
13725915
|
Filing Dt:
|
12/21/2012
|
Publication #:
|
|
Pub Dt:
|
05/02/2013
| | | | |
Title:
|
SIMPLIFIED PITCH DOUBLING PROCESS FLOW
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13726891
|
Filing Dt:
|
12/26/2012
|
Title:
|
SEMICONDUCTOR SUBSTRATE FOR PHOTONIC AND ELECTRONIC STRUCTURES AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13727121
|
Filing Dt:
|
12/26/2012
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
Title:
|
SILVER SELENIDE SPUTTERED FILMS AND METHOD AND APPARATUS FOR CONTROLLING DEFECT FORMATION IN SILVER SELENIDE SPUTTERED FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13728161
|
Filing Dt:
|
12/27/2012
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
Title:
|
PERIPHERAL INTERFACE ALERT MESSAGE FOR DOWNSTREAM DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13728456
|
Filing Dt:
|
12/27/2012
|
Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
Title:
|
METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING FACE-TO-FACE SEMICONDUCTOR DICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
13731658
|
Filing Dt:
|
12/31/2012
|
Publication #:
|
|
Pub Dt:
|
05/09/2013
| | | | |
Title:
|
SELF-TIMED ERROR CORRECTING CODE EVALUATION SYSTEM AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
13732557
|
Filing Dt:
|
01/02/2013
|
Publication #:
|
|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
APPARATUS PROVIDING SIMPLIFIED ALIGNMENT OF OPTICAL FIBER IN PHOTONIC INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2015
|
Application #:
|
13733508
|
Filing Dt:
|
01/03/2013
|
Publication #:
|
|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
METHODS OF EXPOSING CONDUCTIVE VIAS OF SEMICONDUCTOR DEVICES AND ASSOCIATED STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/2015
|
Application #:
|
13733676
|
Filing Dt:
|
01/03/2013
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
VERTICAL 4-WAY SHARED PIXEL IN A SINGLE COLUMN WITH INTERNAL RESET AND NO ROW SELECT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13734476
|
Filing Dt:
|
01/04/2013
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
Title:
|
CONTACT FOR MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2013
|
Application #:
|
13734745
|
Filing Dt:
|
01/04/2013
|
Publication #:
|
|
Pub Dt:
|
07/04/2013
| | | | |
Title:
|
DELAY LINES, METHODS FOR DELAYING A SIGNAL, AND DELAY LOCK LOOPS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13735553
|
Filing Dt:
|
01/07/2013
|
Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
SYSTEM AND METHOD FOR CONTROLLING USER ACCESS TO AN ELECTRONIC DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2014
|
Application #:
|
13735789
|
Filing Dt:
|
01/07/2013
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
Title:
|
SYSTEM AND METHOD FOR DATA READ OF A SYNCHRONOUS SERIAL INTERFACE NAND
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2018
|
Application #:
|
13735791
|
Filing Dt:
|
01/07/2013
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
Title:
|
SENSING PHASE-CHANGE MEMORY/TEST CELLS FOR DETERMINING WHETHER A CELL RESISTANCE HAS CHANGED DUE TO THERMAL EXPOSURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
13735908
|
Filing Dt:
|
01/07/2013
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/2013
|
Application #:
|
13736179
|
Filing Dt:
|
01/08/2013
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
Title:
|
REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13736857
|
Filing Dt:
|
01/08/2013
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
SYSTEM AND METHOD FOR AN ACCURACY-ENHANCED DLL DURING A MEASURE INITIALIZATION MODE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13738147
|
Filing Dt:
|
01/10/2013
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
TRANSISTORS AND SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
13738201
|
Filing Dt:
|
01/10/2013
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13738260
|
Filing Dt:
|
01/10/2013
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
VERTICAL TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13738457
|
Filing Dt:
|
01/10/2013
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13739331
|
Filing Dt:
|
01/11/2013
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH MOLDED CASING AND PACKAGE INTERCONNECT EXTENDING THERETHROUGH, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2015
|
Application #:
|
13739387
|
Filing Dt:
|
01/11/2013
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
Title:
|
METHOD, SYSTEM AND DEVICE FOR PHASE CHANGE MEMORY WITH SHUNT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2016
|
Application #:
|
13739453
|
Filing Dt:
|
01/11/2013
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
Title:
|
HOST CONTROLLED ENABLEMENT OF AUTOMATIC BACKGROUND OPERATIONS IN A MEMORY DEVICE
|
|
|
Patent #:
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Issue Dt:
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01/27/2015
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Application #:
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13739679
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Filing Dt:
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01/11/2013
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Publication #:
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Pub Dt:
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07/17/2014
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Title:
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MEMORIES AND METHODS OF FORMING THIN-FILM TRANSISTORS USING HYDROGEN PLASMA DOPING
|
|
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Patent #:
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Issue Dt:
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10/14/2014
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Application #:
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13740632
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Filing Dt:
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01/14/2013
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Publication #:
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Pub Dt:
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05/23/2013
| | | | |
Title:
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MASKS FOR MICROLITHOGRAPHY AND METHODS OF MAKING AND USING SUCH MASKS
|
|
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Patent #:
|
|
Issue Dt:
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04/29/2014
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Application #:
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13741148
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Filing Dt:
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01/14/2013
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Publication #:
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Pub Dt:
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05/23/2013
| | | | |
Title:
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ERROR SCANNING IN FLASH MEMORY
|
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Patent #:
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NONE
|
Issue Dt:
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Application #:
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13741672
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Filing Dt:
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01/15/2013
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Publication #:
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Pub Dt:
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07/17/2014
| | | | |
Title:
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METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES INCLUDING AN INSULATIVE MATERIAL ON A SEMICONDUCTIVE MATERIAL, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES AND SEMICONDUCTOR DEVICES
|
|
|
Patent #:
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|
Issue Dt:
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03/24/2015
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Application #:
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13741789
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Filing Dt:
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01/15/2013
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Publication #:
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Pub Dt:
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08/01/2013
| | | | |
Title:
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PACKAGED MICRODEVICES AND METHODS FOR MANUFACTURING PACKAGED MICRODEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
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Application #:
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13741964
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Filing Dt:
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01/15/2013
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Publication #:
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Pub Dt:
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06/06/2013
| | | | |
Title:
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PARALLEL ENCRYPTION/DECRYPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
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Application #:
|
13744177
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Filing Dt:
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01/17/2013
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Publication #:
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Pub Dt:
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07/17/2014
| | | | |
Title:
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APPARATUSES AND METHODS FOR CONTROLLING A CLOCK SIGNAL PROVIDED TO A CLOCK TREE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
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Application #:
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13744236
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Filing Dt:
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01/17/2013
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Publication #:
|
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Pub Dt:
|
05/23/2013
| | | | |
Title:
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MIXED-MODE SIGNALING
|
|
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Patent #:
|
|
Issue Dt:
|
06/03/2014
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Application #:
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13745441
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Filing Dt:
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01/18/2013
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Publication #:
|
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Pub Dt:
|
06/13/2013
| | | | |
Title:
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CROSS-HAIR CELL WORDLINE FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
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Application #:
|
13745452
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Filing Dt:
|
01/18/2013
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Publication #:
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|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
MULTI-LEVEL CHARGE STORAGE TRANSISTORS AND ASSOCIATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
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Application #:
|
13746070
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Filing Dt:
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01/21/2013
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Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
Nanotube Separation Methods
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13746114
|
Filing Dt:
|
01/21/2013
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Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
ACCESS LINE DEPENDENT BIASING SCHEMES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2015
|
Application #:
|
13746141
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Filing Dt:
|
01/21/2013
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Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
Title:
|
SYSTEMS AND METHODS FOR ACCESSING MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2016
|
Application #:
|
13746181
|
Filing Dt:
|
01/21/2013
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Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
Title:
|
DETERMINING SOFT DATA FOR FRACTIONAL DIGIT MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13746189
|
Filing Dt:
|
01/21/2013
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
DATA AND ERROR CORRECTION CODE MIXING DEVICE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13746195
|
Filing Dt:
|
01/21/2013
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
Title:
|
DETERMINING SOFT DATA USING A CLASSIFICATION CODE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13746402
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Filing Dt:
|
01/22/2013
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
SPIN TORQUE TRANSFER MEMORY CELL STRUCTURES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13746504
|
Filing Dt:
|
01/22/2013
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
MEMORY SYSTEM AND METHOD USING PARTIAL ECC TO ACHIEVE LOW POWER REFRESH AND FAST ACCESS TO DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2015
|
Application #:
|
13746543
|
Filing Dt:
|
01/22/2013
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
Title:
|
METHODS OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
|
Application #:
|
13746578
|
Filing Dt:
|
01/22/2013
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
MEMORY ARRAYS WHERE A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT ONE END OF A SUBSTANTIALLY VERTICAL PORTION IS GREATER THAN A DISTANCE BETWEEN ADJACENT MEMORY CELLS AT AN OPPOSING END OF THE SUBSTANTIALLY VERTICAL PORTION AND FORMATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13746689
|
Filing Dt:
|
01/22/2013
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
METHODS, DEVICES, AND SYSTEMS FOR ADJUSTING SENSING VOLTAGES IN DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2015
|
Application #:
|
13746768
|
Filing Dt:
|
01/22/2013
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2017
|
Application #:
|
13747116
|
Filing Dt:
|
01/22/2013
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
PRE-ENCAPSULATED LEAD FRAMES FOR MICROELECTRONIC DEVICE PACKAGES, AND ASSOCIATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
13747182
|
Filing Dt:
|
01/22/2013
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
Title:
|
SOLID-STATE TRANSDUCER DEVICES WITH OPTICALLY-TRANSMISSIVE CARRIER SUBSTRATES AND RELATED SYSTEMS, METHODS, AND DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13747917
|
Filing Dt:
|
01/23/2013
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
PROTECTION OF SECURITY PARAMETERS IN STORAGE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13748199
|
Filing Dt:
|
01/23/2013
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
MANAGING MEMORY DATA RECOVERY UPON POWER LOSS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13748256
|
Filing Dt:
|
01/23/2013
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
Title:
|
IDENTIFYING STACKED DICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13748747
|
Filing Dt:
|
01/24/2013
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
Title:
|
3D MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2014
|
Application #:
|
13749046
|
Filing Dt:
|
01/24/2013
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
MEMORY SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
|
Application #:
|
13749521
|
Filing Dt:
|
01/24/2013
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
SEMICONDUCTOR ASSEMBLIES, STACKED SEMICONDUCTOR DEVICES, AND METHODS OF MANUFACTURING SEMICONDUCTOR ASSEMBLIES AND STACKED SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2014
|
Application #:
|
13749850
|
Filing Dt:
|
01/25/2013
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13750560
|
Filing Dt:
|
01/25/2013
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
CONTROL OF PAGE ACCESS IN MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13750963
|
Filing Dt:
|
01/25/2013
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
PHOTOMASK CONSTRUCTIONS HAVING LINERS OF SPECIFIED COMPOSITIONS ALONG SIDEWALLS OF MULTI-LAYERED STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13751502
|
Filing Dt:
|
01/28/2013
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
MEMORY PREFETCH SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13751537
|
Filing Dt:
|
01/28/2013
|
Publication #:
|
|
Pub Dt:
|
06/27/2013
| | | | |
Title:
|
TRANSISTORS HAVING ARGON GATE IMPLANTS AND METHODS OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13751550
|
Filing Dt:
|
01/28/2013
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
APPARATUS, METHODS, AND SYSTEM OF NAND DEFECT MANAGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2015
|
Application #:
|
13751647
|
Filing Dt:
|
01/28/2013
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
Title:
|
MEMORY DEVICE INITIATE AND TERMINATE BOOT COMMANDS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2015
|
Application #:
|
13751671
|
Filing Dt:
|
01/28/2013
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
METHODS AND SYSTEMS FOR RELEASABLY ATTACHING SUPPORT MEMBERS TO MICROFEATURE WORKPIECES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13751781
|
Filing Dt:
|
01/28/2013
|
Publication #:
|
|
Pub Dt:
|
08/15/2013
| | | | |
Title:
|
METHOD FOR PROVIDING ELECTRICAL CONNECTIONS TO SPACED CONDUCTIVE LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
13751902
|
Filing Dt:
|
01/28/2013
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
|
CROSS-POINT DIODE ARRAYS AND METHODS OF MANUFACTURING CROSS-POINT DIODE ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13753135
|
Filing Dt:
|
01/29/2013
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
Capacitor Forming Methods
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13754525
|
Filing Dt:
|
01/30/2013
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
Title:
|
DEVICES AND SYSTEM PROVIDING REDUCED QUANTITY OF INTERCONNECTIONS
|
|