|
|
Patent #:
|
|
Issue Dt:
|
07/09/2019
|
Application #:
|
14989097
|
Filing Dt:
|
01/06/2016
|
Publication #:
|
|
Pub Dt:
|
07/14/2016
| | | | |
Title:
|
SOURCE MATERIAL FOR ELECTRONIC DEVICE APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2018
|
Application #:
|
14989264
|
Filing Dt:
|
01/06/2016
|
Publication #:
|
|
Pub Dt:
|
07/06/2017
| | | | |
Title:
|
ERROR CODE CALCULATION ON SENSING CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2017
|
Application #:
|
14989556
|
Filing Dt:
|
01/06/2016
|
Publication #:
|
|
Pub Dt:
|
04/28/2016
| | | | |
Title:
|
MAGNETIC TUNNEL JUNCTIONS AND METHODS OF FORMING MAGNETIC TUNNEL JUNCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2016
|
Application #:
|
14989625
|
Filing Dt:
|
01/06/2016
|
Publication #:
|
|
Pub Dt:
|
04/28/2016
| | | | |
Title:
|
SWITCHING COMPONENTS AND MEMORY UNITS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2017
|
Application #:
|
14989678
|
Filing Dt:
|
01/06/2016
|
Publication #:
|
|
Pub Dt:
|
04/28/2016
| | | | |
Title:
|
APPARATUSES, CIRCUITS, AND METHODS FOR BIASING SIGNAL LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2016
|
Application #:
|
14990214
|
Filing Dt:
|
01/07/2016
|
Publication #:
|
|
Pub Dt:
|
04/28/2016
| | | | |
Title:
|
ZrAlON FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2018
|
Application #:
|
14991007
|
Filing Dt:
|
01/08/2016
|
Title:
|
METHODS FOR PATTERN MATCHING USING MULTIPLE CELL PAIRS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
14991792
|
Filing Dt:
|
01/08/2016
|
Publication #:
|
|
Pub Dt:
|
05/12/2016
| | | | |
Title:
|
Transistors, Memory Cells and Semiconductor Constructions
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2017
|
Application #:
|
14992280
|
Filing Dt:
|
01/11/2016
|
Publication #:
|
|
Pub Dt:
|
05/05/2016
| | | | |
Title:
|
Integrated Circuitry
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2018
|
Application #:
|
14992612
|
Filing Dt:
|
01/11/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2019
|
Application #:
|
14992616
|
Filing Dt:
|
01/11/2016
|
Publication #:
|
|
Pub Dt:
|
05/05/2016
| | | | |
Title:
|
METHODS AND SYSTEMS FOR HANDLING DATA RECEIVED BY A STATE MACHINE ENGINE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2019
|
Application #:
|
14992657
|
Filing Dt:
|
01/11/2016
|
Publication #:
|
|
Pub Dt:
|
07/13/2017
| | | | |
Title:
|
ESTIMATION OF ERROR CORRECTING PERFORMANCE OF LOW-DENSITY PARITY-CHECK (LDPC) CODES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2017
|
Application #:
|
14992787
|
Filing Dt:
|
01/11/2016
|
Publication #:
|
|
Pub Dt:
|
07/07/2016
| | | | |
Title:
|
LIGHT EMITTING DIODES WITH ENHANCED THERMAL SINKING AND ASSOCIATED METHODS OF OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2016
|
Application #:
|
14992966
|
Filing Dt:
|
01/11/2016
|
Publication #:
|
|
Pub Dt:
|
05/05/2016
| | | | |
Title:
|
METHODS OF FORMING TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2020
|
Application #:
|
14992979
|
Filing Dt:
|
01/11/2016
|
Publication #:
|
|
Pub Dt:
|
07/13/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE PARTITIONS OF A NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2018
|
Application #:
|
14993256
|
Filing Dt:
|
01/12/2016
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
AMBIENT INFRARED DETECTION IN SOLID STATE SENSORS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2018
|
Application #:
|
14993306
|
Filing Dt:
|
01/12/2016
|
Publication #:
|
|
Pub Dt:
|
05/05/2016
| | | | |
Title:
|
Memory Arrays And Methods Of Forming An Array Of Memory Cell
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2017
|
Application #:
|
14995302
|
Filing Dt:
|
01/14/2016
|
Publication #:
|
|
Pub Dt:
|
05/12/2016
| | | | |
Title:
|
OPERATING MEMORY DEVICES TO APPLY A PROGRAMMING POTENTIAL TO A MEMORY CELL IN A STRING COUPLED TO A SOURCE AND DATA LINE CONCURRENTLY WITH BIASING THE DATA LINE TO A GREATER POTENTIAL THAN THE SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2018
|
Application #:
|
14995709
|
Filing Dt:
|
01/14/2016
|
Publication #:
|
|
Pub Dt:
|
07/20/2017
| | | | |
Title:
|
INTEGRATED CIRCUITRY AND 3D MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2018
|
Application #:
|
14995925
|
Filing Dt:
|
01/14/2016
|
Publication #:
|
|
Pub Dt:
|
07/20/2017
| | | | |
Title:
|
SEMICONDUCTOR DEVICES WITH DUPLICATED DIE BOND PADS AND ASSOCIATED DEVICE PACKAGES AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2016
|
Application #:
|
14996316
|
Filing Dt:
|
01/15/2016
|
Publication #:
|
|
Pub Dt:
|
05/12/2016
| | | | |
Title:
|
SYSTEMS, DEVICES, MEMORY CONTROLLERS, AND METHODS FOR CONTROLLING MEMORY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14997108
|
Filing Dt:
|
01/15/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
NANOSTRUCTURES HAVING LOW DEFECT DENSITY AND METHODS OF FORMING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2019
|
Application #:
|
14997164
|
Filing Dt:
|
01/15/2016
|
Publication #:
|
|
Pub Dt:
|
07/20/2017
| | | | |
Title:
|
NON-VOLATILE MEMORY INCLUDING SELECTIVE ERROR CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2017
|
Application #:
|
14997278
|
Filing Dt:
|
01/15/2016
|
Publication #:
|
|
Pub Dt:
|
05/12/2016
| | | | |
Title:
|
RANDOM TELEGRAPH SIGNAL NOISE REDUCTION SCHEME FOR SEMICONDUCTOR MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2017
|
Application #:
|
15000620
|
Filing Dt:
|
01/19/2016
|
Publication #:
|
|
Pub Dt:
|
11/10/2016
| | | | |
Title:
|
Magnetic Tunnel Junctions
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2018
|
Application #:
|
15000812
|
Filing Dt:
|
01/19/2016
|
Publication #:
|
|
Pub Dt:
|
07/20/2017
| | | | |
Title:
|
NON-VOLATILE MEMORY MODULE ARCHITECTURE TO SUPPORT MEMORY ERROR CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2018
|
Application #:
|
15000935
|
Filing Dt:
|
01/19/2016
|
Publication #:
|
|
Pub Dt:
|
06/23/2016
| | | | |
Title:
|
SELF-ALIGNED INTERCONNECTION FOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2017
|
Application #:
|
15001070
|
Filing Dt:
|
01/19/2016
|
Publication #:
|
|
Pub Dt:
|
08/25/2016
| | | | |
Title:
|
SEMICONDUCTOR DIES WITH RECESSES, ASSOCIATED LEADFRAMES, AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2017
|
Application #:
|
15003246
|
Filing Dt:
|
01/21/2016
|
Publication #:
|
|
Pub Dt:
|
05/19/2016
| | | | |
Title:
|
VERTICAL SEMICONDUCTOR PILLAR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2017
|
Application #:
|
15003498
|
Filing Dt:
|
01/21/2016
|
Publication #:
|
|
Pub Dt:
|
07/27/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR ACCESSING MEMORY CELLS IN SEMICONDUCTOR MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2017
|
Application #:
|
15003606
|
Filing Dt:
|
01/21/2016
|
Publication #:
|
|
Pub Dt:
|
05/19/2016
| | | | |
Title:
|
METHODS OF FORMING MEMORY DEVICE CONSTRUCTIONS, METHODS OF FORMING MEMORY CELLS, AND METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2017
|
Application #:
|
15003679
|
Filing Dt:
|
01/21/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
Transistors and Methods of Forming Transistors
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2018
|
Application #:
|
15003715
|
Filing Dt:
|
01/21/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
MEMORY ARRAYS AND METHODS OF FORMING MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2017
|
Application #:
|
15004150
|
Filing Dt:
|
01/22/2016
|
Publication #:
|
|
Pub Dt:
|
05/19/2016
| | | | |
Title:
|
METHODS AND DEVICES FOR STORING USER DATA ALONG WITH ADDRESSES CORRESPONDING TO PHYSICAL PAGES STORING VALID DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2017
|
Application #:
|
15004282
|
Filing Dt:
|
01/22/2016
|
Publication #:
|
|
Pub Dt:
|
07/27/2017
| | | | |
Title:
|
APPARATUSES, MULTI-CHIP MODULES AND CAPACITIVE CHIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2016
|
Application #:
|
15004744
|
Filing Dt:
|
01/22/2016
|
Publication #:
|
|
Pub Dt:
|
05/19/2016
| | | | |
Title:
|
Field Effect Transistor Constructions And Memory Arrays
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2019
|
Application #:
|
15004777
|
Filing Dt:
|
01/22/2016
|
Publication #:
|
|
Pub Dt:
|
07/27/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR ENCODING AND DECODING OF SIGNAL LINES FOR MULTI-LEVEL COMMUNICATION ARCHITECTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2017
|
Application #:
|
15004781
|
Filing Dt:
|
01/22/2016
|
Publication #:
|
|
Pub Dt:
|
05/19/2016
| | | | |
Title:
|
REFERENCE VOLTAGE GENERATORS AND SENSING CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2017
|
Application #:
|
15005250
|
Filing Dt:
|
01/25/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
Ferroelectric Field Effect Transistors, Pluralities Of Ferroelectric Field Effect Transistors Arrayed In Row Lines And Column Lines, And Methods Of Forming A Plurality Of Ferroelectric Field Effect Transistors
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2018
|
Application #:
|
15005360
|
Filing Dt:
|
01/25/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
An Array Of Conductive Lines Individually Extending Transversally Across And Elevationally Over A Mid-Portion Of Individual Active Area Regions
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2016
|
Application #:
|
15006236
|
Filing Dt:
|
01/26/2016
|
Publication #:
|
|
Pub Dt:
|
05/19/2016
| | | | |
Title:
|
MAPPING BETWEEN PROGRAM STATES AND DATA PATTERNS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2017
|
Application #:
|
15006646
|
Filing Dt:
|
01/26/2016
|
Publication #:
|
|
Pub Dt:
|
07/27/2017
| | | | |
Title:
|
APPARATUS AND METHOD FOR STANDBY CURRENT CONTROL OF SIGNAL PATH
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2019
|
Application #:
|
15007615
|
Filing Dt:
|
01/27/2016
|
Publication #:
|
|
Pub Dt:
|
05/19/2016
| | | | |
Title:
|
STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH IMPROVED THERMAL PERFORMANCE AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2019
|
Application #:
|
15011115
|
Filing Dt:
|
01/29/2016
|
Publication #:
|
|
Pub Dt:
|
05/26/2016
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A REDUCED FOOTPRINT OF WIRES CONNECTING A DLL CIRCUIT WITH AN INPUT/OUTPUT BUFFER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2017
|
Application #:
|
15011816
|
Filing Dt:
|
02/01/2016
|
Publication #:
|
|
Pub Dt:
|
05/26/2016
| | | | |
Title:
|
THREE DIMENSIONAL MEMORY ARRAY ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2019
|
Application #:
|
15011819
|
Filing Dt:
|
02/01/2016
|
Publication #:
|
|
Pub Dt:
|
05/26/2016
| | | | |
Title:
|
METHODS AND APPARATUSES WITH VERTICAL STRINGS OF MEMORY CELLS AND SUPPORT CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2017
|
Application #:
|
15012478
|
Filing Dt:
|
02/01/2016
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
METHODS FOR OPERATING A MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2018
|
Application #:
|
15012519
|
Filing Dt:
|
02/01/2016
|
Publication #:
|
|
Pub Dt:
|
05/26/2016
| | | | |
Title:
|
APPARATUSES AND METHODS TO CHANGE INFORMATION VALUES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2017
|
Application #:
|
15012566
|
Filing Dt:
|
02/01/2016
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
Title:
|
CELL-BASED REFERENCE VOLTAGE GENERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2017
|
Application #:
|
15013269
|
Filing Dt:
|
02/02/2016
|
Publication #:
|
|
Pub Dt:
|
08/04/2016
| | | | |
Title:
|
LOOP STRUCTURE FOR OPERATIONS IN MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2018
|
Application #:
|
15013298
|
Filing Dt:
|
02/02/2016
|
Publication #:
|
|
Pub Dt:
|
05/26/2016
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES INCLUDING DIELECTRIC MATERIALS HAVING DIFFERING REMOVAL RATES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2017
|
Application #:
|
15013796
|
Filing Dt:
|
02/02/2016
|
Publication #:
|
|
Pub Dt:
|
06/09/2016
| | | | |
Title:
|
Semiconductor Device
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2018
|
Application #:
|
15015424
|
Filing Dt:
|
02/04/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
MEMORY DEVICES AND THEIR OPERATION HAVING TRIM REGISTERS ASSOCIATED WITH ACCESS OPERATION COMMANDS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2019
|
Application #:
|
15019175
|
Filing Dt:
|
02/09/2016
|
Publication #:
|
|
Pub Dt:
|
08/10/2017
| | | | |
Title:
|
MEMORY DEVICES WITH A TRANSISTOR THAT SELECTIVELY CONNECTS A DATA LINE TO ANOTHER DATA LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2017
|
Application #:
|
15019397
|
Filing Dt:
|
02/09/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
PROGRAM OPERATIONS WITH EMBEDDED LEAK CHECKS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2017
|
Application #:
|
15019687
|
Filing Dt:
|
02/09/2016
|
Publication #:
|
|
Pub Dt:
|
06/02/2016
| | | | |
Title:
|
METHODS AND APPARATUSES FOR COMPENSATING FOR SOURCE VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2017
|
Application #:
|
15019748
|
Filing Dt:
|
02/09/2016
|
Publication #:
|
|
Pub Dt:
|
08/04/2016
| | | | |
Title:
|
VERTICAL SOLID-STATE TRANSDUCERS AND HIGH VOLTAGE SOLID-STATE TRANSDUCERS HAVING BURIED CONTACTS AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2018
|
Application #:
|
15040084
|
Filing Dt:
|
02/10/2016
|
Publication #:
|
|
Pub Dt:
|
08/10/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR PARTITIONED PARALLEL DATA MOVEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2018
|
Application #:
|
15041207
|
Filing Dt:
|
02/11/2016
|
Publication #:
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Pub Dt:
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08/17/2017
| | | | |
Title:
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DISTRIBUTED INPUT/OUTPUT VIRTUALIZATION
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|
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Patent #:
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Issue Dt:
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08/14/2018
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Application #:
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15041277
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Filing Dt:
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02/11/2016
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Publication #:
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Pub Dt:
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06/09/2016
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Title:
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APPARATUSES INCLUDING MEMORY ARRAYS WITH SOURCE CONTACTS ADJACENT EDGES OF SOURCES
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|
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Patent #:
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Issue Dt:
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02/21/2017
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Application #:
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15042197
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Filing Dt:
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02/12/2016
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Publication #:
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Pub Dt:
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06/09/2016
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Title:
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IMPROVED DEFLATE COMPRESSION ALGORITHM
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Patent #:
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Issue Dt:
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05/16/2017
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Application #:
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15043086
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Filing Dt:
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02/12/2016
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Title:
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APPARATUSES AND METHODS FOR VOLTAGE LEVEL CONTROL
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Patent #:
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Issue Dt:
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02/13/2018
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Application #:
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15043236
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Filing Dt:
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02/12/2016
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Publication #:
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Pub Dt:
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08/17/2017
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Title:
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DATA GATHERING IN MEMORY
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Patent #:
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Issue Dt:
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07/18/2017
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Application #:
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15043921
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Filing Dt:
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02/15/2016
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Publication #:
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Pub Dt:
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06/09/2016
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Title:
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METHODS AND APPARATUSES INCLUDING A SELECT TRANSISTOR HAVING A BODY REGION INCLUDING MONOCRYSTALLINE SEMICONDUCTOR MATERIAL AND/OR AT LEAST A PORTION OF ITS GATE LOCATED IN A SUBSTRATE
|
|
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Patent #:
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Issue Dt:
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03/06/2018
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Application #:
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15044185
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Filing Dt:
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02/16/2016
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Publication #:
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Pub Dt:
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08/17/2017
| | | | |
Title:
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READ THRESHOLD VOLTAGE SELECTION
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Patent #:
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Issue Dt:
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09/19/2017
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Application #:
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15044713
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Filing Dt:
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02/16/2016
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Publication #:
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Pub Dt:
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06/09/2016
| | | | |
Title:
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METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES INCLUDING METAL OXIDE STRUCTURES
|
|
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Patent #:
|
|
Issue Dt:
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01/30/2018
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Application #:
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15045061
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Filing Dt:
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02/16/2016
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Publication #:
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Pub Dt:
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08/17/2017
| | | | |
Title:
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SELECTORS ON INTERFACE DIE FOR MEMORY DEVICE
|
|
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Patent #:
|
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Issue Dt:
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04/04/2017
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Application #:
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15045124
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Filing Dt:
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02/16/2016
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Publication #:
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Pub Dt:
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06/09/2016
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD FOR ADJUSTING IMPEDANCE OF OUTPUT CIRCUIT
|
|
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Patent #:
|
|
Issue Dt:
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12/25/2018
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Application #:
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15045490
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Filing Dt:
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02/17/2016
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Publication #:
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Pub Dt:
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06/09/2016
| | | | |
Title:
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SEMICONDUCTOR DEVICE HAVING A SECOND CONDUCTIVE LAYER PARTIALLY EMBEDDED IN A STACKED INSULATING STRUCTURE AND HAVING A FIRST CONDUCTIVE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
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01/03/2017
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Application #:
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15045550
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Filing Dt:
|
02/17/2016
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Publication #:
|
|
Pub Dt:
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08/18/2016
| | | | |
Title:
|
METHODS AND SYSTEMS FOR ROUTING IN A STATE MACHINE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2018
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Application #:
|
15045750
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Filing Dt:
|
02/17/2016
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Publication #:
|
|
Pub Dt:
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08/17/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR DATA MOVEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2017
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Application #:
|
15045865
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Filing Dt:
|
02/17/2016
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Publication #:
|
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Pub Dt:
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06/09/2016
| | | | |
Title:
|
MAGNETIC MEMORY CELLS AND METHODS OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2022
|
Application #:
|
15046078
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Filing Dt:
|
02/17/2016
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Publication #:
|
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Pub Dt:
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08/17/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR INTERNAL HEAT SPREADING FOR PACKAGED SEMICONDUCTOR DIE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2017
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Application #:
|
15046330
|
Filing Dt:
|
02/17/2016
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Title:
|
MEMORY CELL ARCHITECTURE FOR MULTILEVEL CELL PROGRAMMING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2019
|
Application #:
|
15046666
|
Filing Dt:
|
02/18/2016
|
Publication #:
|
|
Pub Dt:
|
08/24/2017
| | | | |
Title:
|
ERROR RATE REDUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2017
|
Application #:
|
15046949
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Filing Dt:
|
02/18/2016
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Publication #:
|
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Pub Dt:
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08/24/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR PHOTONIC COMMUNICATION AND PHOTONIC ADDRESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2018
|
Application #:
|
15047000
|
Filing Dt:
|
02/18/2016
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Publication #:
|
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Pub Dt:
|
08/24/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR MULTIPLE ADDRESS REGISTERS FOR A SOLID STATE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2018
|
Application #:
|
15048133
|
Filing Dt:
|
02/19/2016
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Publication #:
|
|
Pub Dt:
|
08/24/2017
| | | | |
Title:
|
MODIFIED DECODE FOR CORNER TURN
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2021
|
Application #:
|
15048179
|
Filing Dt:
|
02/19/2016
|
Publication #:
|
|
Pub Dt:
|
08/24/2017
| | | | |
Title:
|
DATA TRANSFER WITH A BIT VECTOR OPERATION DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2017
|
Application #:
|
15048746
|
Filing Dt:
|
02/19/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
METHOD, SYSTEM, AND DEVICE FOR HEATING A PHASE CHANGE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2018
|
Application #:
|
15049097
|
Filing Dt:
|
02/21/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
Methods of Fabricating Integrated Structures
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2017
|
Application #:
|
15049100
|
Filing Dt:
|
02/21/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
Memory Cells, Integrated Devices, and Methods of Forming Memory Cells
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15049754
|
Filing Dt:
|
02/22/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
INDEPENDENT CONTROL OF STACKED ELECTRONIC MODULES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2017
|
Application #:
|
15050231
|
Filing Dt:
|
02/22/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2019
|
Application #:
|
15050238
|
Filing Dt:
|
02/22/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
APPARATUSES AND METHOD FOR OVER-VOLTAGE EVENT PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2018
|
Application #:
|
15050248
|
Filing Dt:
|
02/22/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
Memory Systems and Memory Programming Methods
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2019
|
Application #:
|
15050328
|
Filing Dt:
|
02/22/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
Method of Forming Contacts for a Memory Device
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2017
|
Application #:
|
15050858
|
Filing Dt:
|
02/23/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
SEMICONDUCTOR DEVICES AND METHODS FOR BACKSIDE PHOTO ALIGNMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
15051112
|
Filing Dt:
|
02/23/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
APPARATUSES AND METHODS FOR PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2017
|
Application #:
|
15052161
|
Filing Dt:
|
02/24/2016
|
Publication #:
|
|
Pub Dt:
|
06/16/2016
| | | | |
Title:
|
OPTICAL INTERCONNECT IN HIGH-SPEED MEMORY SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
15053291
|
Filing Dt:
|
02/25/2016
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Title:
|
MEMORY DEVICES WITH STAIRS IN A STAIRCASE COUPLED TO TIERS OF MEMORY CELLS AND TO PASS TRANSISTORS DIRECTLY UNDER THE STAIRCASE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2017
|
Application #:
|
15053562
|
Filing Dt:
|
02/25/2016
|
Publication #:
|
|
Pub Dt:
|
06/23/2016
| | | | |
Title:
|
SYSTEMS, AND DEVICES, AND METHODS FOR PROGRAMMING A RESISTIVE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2019
|
Application #:
|
15053719
|
Filing Dt:
|
02/25/2016
|
Publication #:
|
|
Pub Dt:
|
08/31/2017
| | | | |
Title:
|
REDUNDANT ARRAY OF INDEPENDENT NAND FOR A THREE-DIMENSIONAL MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2017
|
Application #:
|
15054409
|
Filing Dt:
|
02/26/2016
|
Publication #:
|
|
Pub Dt:
|
06/23/2016
| | | | |
Title:
|
POWER MANAGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2017
|
Application #:
|
15054984
|
Filing Dt:
|
02/26/2016
|
Publication #:
|
|
Pub Dt:
|
06/23/2016
| | | | |
Title:
|
METHODS AND APPARATUSES HAVING A VOLTAGE GENERATOR WITH AN ADJUSTABLE VOLTAGE DROP FOR REPRESENTING A VOLTAGE DROP OF A MEMORY CELL AND/OR A CURRENT MIRROR CIRCUIT AND REPLICA CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2018
|
Application #:
|
15055230
|
Filing Dt:
|
02/26/2016
|
Publication #:
|
|
Pub Dt:
|
08/31/2017
| | | | |
Title:
|
APPARATUSES AND METHODS FOR LEVEL SHIFTING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2017
|
Application #:
|
15056548
|
Filing Dt:
|
02/29/2016
|
Publication #:
|
|
Pub Dt:
|
06/23/2016
| | | | |
Title:
|
CELL PILLAR STRUCTURES AND INTEGRATED FLOWS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2018
|
Application #:
|
15056845
|
Filing Dt:
|
02/29/2016
|
Publication #:
|
|
Pub Dt:
|
06/23/2016
| | | | |
Title:
|
METHODS AND APPARATUS PROVIDING THERMAL ISOLATION OF PHOTONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2017
|
Application #:
|
15057736
|
Filing Dt:
|
03/01/2016
|
Title:
|
VERTICAL BIT VECTOR SHIFT IN MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2018
|
Application #:
|
15057909
|
Filing Dt:
|
03/01/2016
|
Publication #:
|
|
Pub Dt:
|
06/23/2016
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES AND DEVICES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES AND MAGNETIC MEMORY CELLS
|
|