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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10290365
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Filing Dt:
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11/07/2002
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Publication #:
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Pub Dt:
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05/22/2003
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Title:
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MEMORY DEVICE AND METHOD OF ACCESSING A MEMORY DEVICE
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Patent #:
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06/22/2004
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10290907
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Filing Dt:
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11/08/2002
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Publication #:
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Pub Dt:
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05/13/2004
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Title:
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Patent #:
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Issue Dt:
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09/26/2006
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10291069
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Filing Dt:
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11/08/2002
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Publication #:
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Pub Dt:
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05/08/2003
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Title:
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CIRCUIT FOR SETTING A SIGNAL PROPAGATION TIME FOR A SIGNAL ON A SIGNAL LINE AND METHOD FOR ASCERTAINING TIMING PARAMETERS
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Patent #:
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12/28/2004
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10291070
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Filing Dt:
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11/08/2002
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Publication #:
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Pub Dt:
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05/08/2003
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Title:
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METHOD FOR FABRICATING A MASK FOR SEMICONDUCTOR STRUCTURES
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Patent #:
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05/24/2005
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10291610
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Filing Dt:
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11/12/2002
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Publication #:
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Pub Dt:
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05/13/2004
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Title:
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Patent #:
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11/28/2006
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Application #:
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10292169
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Filing Dt:
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11/12/2002
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Publication #:
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Pub Dt:
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05/13/2004
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Title:
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SUB-RESOLUTION SIZED ASSIST FEATURES
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Patent #:
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Issue Dt:
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06/28/2005
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10292621
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Filing Dt:
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11/13/2002
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Pub Dt:
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05/15/2003
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Title:
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12/16/2008
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10292844
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11/12/2002
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Pub Dt:
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04/17/2003
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Title:
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CONFIGURATION FOR THE TRANSMISSION OF SIGNALS BETWEEN A DATA PROCESSING DEVICE AND A FUNCTIONAL UNIT
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03/15/2005
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10292847
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Filing Dt:
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11/12/2002
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Pub Dt:
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05/15/2003
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Title:
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METHOD AND APPARATUS FOR FINDING A FAULT IN A SIGNAL PATH ON A PRINTED CIRCUIT BOARD
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Patent #:
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02/01/2005
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10292866
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Filing Dt:
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11/12/2002
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Pub Dt:
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05/15/2003
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Title:
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REFLECTION MASK FOR EUV-LITHOGRAPHY AND METHOD FOR FABRICATING THE REFLECTION MASK
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06/29/2004
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10293923
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11/13/2002
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06/26/2003
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Title:
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CIRCUIT DEVICE HAVING A FUSE
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08/03/2004
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10294100
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11/14/2002
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Pub Dt:
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05/20/2004
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Title:
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SILICON NITRIDE ISLAND FORMATION FOR INCREASED CAPACITANCE
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06/21/2005
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10294329
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11/14/2002
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Publication #:
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Pub Dt:
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05/20/2004
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Title:
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HIGH DENSITY DRAM WITH REDUCED PERIPHERAL DEVICE AREA AND METHOD OF MANUFACTURE
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06/26/2007
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10295710
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11/15/2002
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Pub Dt:
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05/29/2003
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Title:
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SIGNAL DISTRIBUTION TO A PLURALITY OF CIRCUIT UNITS
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Patent #:
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Issue Dt:
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03/14/2006
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10295735
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11/15/2002
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Pub Dt:
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05/15/2003
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Title:
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PHOTOLITHOGRAPHY MASK AND METHOD OF FABRICATING A PHOTOLITHOGRAPHY MASK
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Patent #:
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Issue Dt:
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08/15/2006
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10298429
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11/18/2002
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Pub Dt:
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07/03/2003
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Title:
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REFLECTION MASK AND METHOD FOR FABRICATING THE REFLECTION MASK
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Patent #:
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Issue Dt:
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05/25/2004
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10298717
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Filing Dt:
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11/18/2002
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Pub Dt:
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05/20/2004
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Title:
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SIGE VERTICAL GATE CONTACT FOR GATE CONDUCTOR POST ETCH TREATMENT
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Patent #:
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Issue Dt:
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05/01/2007
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10298772
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11/18/2002
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06/12/2003
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Title:
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PROCESS FOR PRODUCING A COMPONENT MODULE
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Patent #:
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04/19/2005
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10298831
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11/18/2002
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Pub Dt:
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04/24/2003
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Title:
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APPARATUS AND METHOD FOR HANDLING, STORING AND RELOADING CARRIERS FOR DISK-SHAPED ITEMS, SUCH AS SEMICONDUCTOR WAFERS OR CDS
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Issue Dt:
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07/13/2004
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10298834
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Filing Dt:
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11/18/2002
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Publication #:
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Pub Dt:
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05/01/2003
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Title:
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VERTICAL TRANSISTOR AND TRANSISTOR FABRICATION METHOD
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Patent #:
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Issue Dt:
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01/25/2005
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10298837
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Filing Dt:
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11/18/2002
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06/19/2003
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Title:
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METHOD FOR CONNECTION OF CIRCUIT UNITS
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Issue Dt:
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03/28/2006
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10298970
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Filing Dt:
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11/18/2002
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Pub Dt:
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06/26/2003
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Title:
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DEVICE AND METHOD FOR ASSOCIATING INFORMATION CONCERNING MEMORY CELLS OF A MEMORY WITH AN EXTERNAL MEMORY
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Patent #:
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Issue Dt:
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03/23/2004
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10299026
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Filing Dt:
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11/18/2002
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Title:
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METHOD AND IMPLEMENTATION OF AN ON-CHIP SELF REFRESH FEATURE
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04/20/2004
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10299037
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11/18/2002
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Title:
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SOFT ERROR IMPROVEMENT FOR LATCHES
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05/11/2004
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10299269
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11/19/2002
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Pub Dt:
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05/20/2004
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Title:
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SEMICONDUCTOR DEVICE WITH DEEP TRENCH ISOLATION AND METHOD OF MANUFACTURING SAME
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Issue Dt:
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07/26/2005
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10299750
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11/19/2002
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Pub Dt:
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07/03/2003
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Title:
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MEMORY, PROCESSOR SYSTEM AND METHOD FOR PERFORMING WRITE OPERATIONS ON A MEMORY REGION
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Patent #:
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09/07/2004
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10301090
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11/20/2002
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Pub Dt:
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05/22/2003
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Title:
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INTEGRATED CIRCUIT HAVING A PROGRAMMABLE ELEMENT AND METHOD OF OPERATING THE CIRCUIT
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04/27/2004
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10301368
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11/21/2002
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05/22/2003
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Title:
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SEMICONDUCTOR COMPONENT
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Issue Dt:
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09/07/2004
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10301393
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11/21/2002
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Pub Dt:
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05/22/2003
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Title:
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METHOD AND SEMICONDUCTOR WAFER CONFIGURATION FOR PRODUCING AN ALIGNMENT MARK FOR SEMICONDUCTOR WAFERS
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06/01/2004
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10301398
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11/21/2002
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05/22/2003
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Title:
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SEMICONDUCTOR MEMORY MODULE WITH LOW CURRENT CONSUMPTION
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11/30/2004
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10301529
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11/20/2002
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Pub Dt:
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05/20/2004
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Title:
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2T2C SIGNAL MARGIN TEST MODE USING A DEFINED CHARGE AND DISCHARGE OF BL AND /BL
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05/04/2004
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10301546
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11/20/2002
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05/20/2004
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Title:
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2T2C SIGNAL MARGIN TEST MODE USING RESISTIVE ELEMENT
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04/05/2005
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10301548
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11/20/2002
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Pub Dt:
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05/20/2004
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Title:
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2T2C SIGNAL MARGIN TEST MODE USING A DEFINED CHARGE EXCHANGE BETWEEN BL AND/BL
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05/16/2006
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10302214
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11/22/2002
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05/29/2003
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07/05/2005
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10302615
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11/21/2002
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07/03/2003
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FLOATING GATE FIELD-EFFECT TRANSISTOR
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09/13/2005
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10302725
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11/22/2002
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Pub Dt:
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07/10/2003
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MANUFACTURING OF A CORROSION PROTECTED INTERCONNECT ON A SUBSTRATE
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04/04/2006
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10302805
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11/22/2002
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07/03/2003
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ARRAY OF SYNCHRONIZED MEMORY MODULES
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03/02/2004
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10302864
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11/25/2002
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07/10/2003
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Title:
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PROGRAMMABLE VOLTAGE PUMP HAVING A GROUND OPTION
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12/04/2007
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10303179
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11/25/2002
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05/27/2004
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INTEGRATED CIRCUIT IN A MAXIMUM INPUT/OUTPUT CONFIGURATION
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02/07/2006
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10304131
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11/25/2002
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05/29/2003
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PROCESS FOR CHEMICALLY MECHANICALLY POLISHING WAFERS
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07/20/2004
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10304134
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11/25/2002
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05/29/2003
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FIELD EFFECT TRANSISTOR AND FABRICATION METHOD
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06/06/2006
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10304135
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11/25/2002
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05/29/2003
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INTEGRATED MEMORY AND METHOD OF REPAIRING AN INTEGRATED MEMORY
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04/08/2008
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10304506
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11/26/2002
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05/27/2004
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MODULAR TEST CONTROLLER WITH BISTCIRCUIT FOR TESTING EMBEDDED DRAM CIRCUITS
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09/21/2004
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10305063
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11/27/2002
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05/27/2004
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THREE LAYER ALUMINUM DEPOSITION PROCESS FOR HIGH ASPECT RATIO CL CONTACTS
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09/20/2005
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10306184
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11/27/2002
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05/29/2003
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LEADFRAME OF A CONDUCTIVE MATERIAL AND COMPONENT WITH A LEADFRAME OF A CONDUCTIVE MATERIAL
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03/22/2005
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10306438
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11/27/2002
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07/03/2003
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SEMICONDUCTOR CHIP, FABRICATION METHOD, AND DEVICE FOR FABRICATING A SEMICONDUCTOR CHIP
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09/20/2005
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10307257
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11/29/2002
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06/03/2004
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SIDE-WALL BARRIER STRUCTURE AND METHOD OF FABRICATION
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05/16/2006
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10307800
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12/02/2002
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Pub Dt:
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07/17/2003
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MASK WITH PROGRAMMED DEFECTS AND METHOD FOR THE FABRICATION THEREOF
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08/31/2004
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10309291
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12/03/2002
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06/03/2004
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INTRA-CELL MASK ALIGNMENT FOR IMPROVED OVERLAY
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03/15/2005
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10310397
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12/05/2002
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06/05/2003
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METHOD FOR FABRICATING AN INTEGRATED SEMICONDUCTOR CIRCUIT
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06/15/2004
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10310930
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12/05/2002
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06/05/2003
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METHOD FOR DRIVING MEMORY CELLS OF A DYNAMIC SEMICONDUCTOR MEMORY AND CIRCUIT CONFIGURATION
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05/31/2005
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10314049
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12/04/2002
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Pub Dt:
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06/26/2003
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LAYER ARRANGEMENT, MEMORY CELL, MEMORY CELL ARRANGEMENT AND METHOD FOR PRODUCING A LAYER ARRANGEMENT
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Issue Dt:
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03/23/2004
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10314548
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12/06/2002
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Title:
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METHOD OF AREA ENHANCEMENT IN CAPACITOR PLATES
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Issue Dt:
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09/20/2005
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10314797
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12/09/2002
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Pub Dt:
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10/02/2003
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Title:
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MEMORY CHIP, MEMORY COMPONENT AND CORRESPONDING MEMORY MODULE AND METHOD
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Issue Dt:
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09/23/2003
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Application #:
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10315342
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Filing Dt:
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12/10/2002
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Publication #:
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Pub Dt:
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05/01/2003
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Title:
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CIRCUIT CONFIGURATION FIR EVALUATING THE INFORMATION CONTENT OF A MEMORY CELL
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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10317933
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Filing Dt:
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12/12/2002
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Publication #:
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Pub Dt:
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06/12/2003
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Title:
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INTEGRATED TEST CIRCUIT
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Patent #:
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Issue Dt:
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04/19/2005
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Application #:
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10317972
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Filing Dt:
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12/12/2002
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Publication #:
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Pub Dt:
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06/12/2003
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Title:
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METHOD FOR OPERATING A SEMICONDUCTOR MEMORY, AND SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10318709
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Filing Dt:
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12/13/2002
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Publication #:
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Pub Dt:
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06/17/2004
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Title:
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ARCHITECTURE FOR HIGH-SPEED MAGNETIC MEMORIES
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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10318795
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Filing Dt:
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12/13/2002
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Title:
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WORDLINE ON AND OFF VOLTAGE COMPENSATION CIRCUIT BASED ON THE ARRAY DEVICE THRESHOLD VOLTAGE
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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10320127
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Filing Dt:
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12/16/2002
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Publication #:
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Pub Dt:
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06/19/2003
| | | | |
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Title:
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CONTACT PIN FOR TESTING MICROELECTRONIC COMPONENTS HAVING SUBSTANTIALLY SPHERICAL CONTACTS
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Patent #:
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Issue Dt:
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04/20/2004
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10320867
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Filing Dt:
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12/17/2002
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Title:
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SELF-ALIGNED CONTACT FORMATION USING DOUBLE SIN SPACERS
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10321185
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Filing Dt:
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12/17/2002
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Publication #:
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Pub Dt:
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06/26/2003
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Title:
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METHOD FOR TRENCH ETCHING
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Patent #:
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Issue Dt:
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10/24/2006
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Application #:
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10322587
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Filing Dt:
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12/19/2002
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Publication #:
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Pub Dt:
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06/24/2004
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Title:
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SEMICONDUCTOR DEVICE COMPRISING TRANSITION DETECTING CIRCUIT AND METHOD OF ACTIVATING THE SAME
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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10324432
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Filing Dt:
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12/20/2002
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Publication #:
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Pub Dt:
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06/26/2003
| | | | |
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Title:
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INTEGRATED CIRCUIT HAVING A CONNECTION PAD FOR STIPULATING ONE OF A PLURALITY OF ORGANIZATION FORMS, AND METHOD FOR OPERATING THE CIRCUIT
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Patent #:
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Issue Dt:
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06/07/2005
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Application #:
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10324874
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Filing Dt:
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12/20/2002
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Publication #:
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Pub Dt:
|
06/26/2003
| | | | |
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Title:
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CONTACT SPRING CONFIGURATION FOR CONTACTING A SEMICONDUCTOR WAFER AND METHOD FOR PRODUCING A CONTACT SPRING CONFIGURATION
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Patent #:
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Issue Dt:
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11/01/2005
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Application #:
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10325100
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Filing Dt:
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12/20/2002
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Publication #:
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Pub Dt:
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07/31/2003
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Title:
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METHOD FOR ACTIVATING FUSE UNITS IN ELECTRONIC CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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03/06/2007
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Application #:
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10325250
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Filing Dt:
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12/19/2002
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Publication #:
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Pub Dt:
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07/10/2003
| | | | |
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Title:
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MEMORY UNIT AND BRANCHED COMMAND/ADDRESS BUS ARCHITECTURE BETWEEN A MEMORY REGISTER AND A PLURALITY OF MEMORY UNITS
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Patent #:
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Issue Dt:
|
08/23/2005
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Application #:
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10325251
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Filing Dt:
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12/19/2002
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Publication #:
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Pub Dt:
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06/19/2003
| | | | |
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Title:
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ELECTRONIC DEVICE AND LEADFRAME AND METHODS FOR PRODUCING THE ELECTRONIC DEVICE AND THE LEADFRAME
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10325349
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Filing Dt:
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12/18/2002
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Publication #:
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Pub Dt:
|
06/19/2003
| | | | |
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Title:
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INTEGRATED MEMORY HAVING A PRECHARGE CIRCUIT FOR PRECHARGING A BIT LINE
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Patent #:
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Issue Dt:
|
11/29/2005
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Application #:
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10330440
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Filing Dt:
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12/27/2002
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Publication #:
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Pub Dt:
|
06/05/2003
| | | | |
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Title:
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LEADFRAME FOR SEMICONDUCTOR CHIPS AND ELECTRONIC DEVICES AND PRODUCTION METHODS FOR A LEADFRAME AND FOR ELECTRONIC DEVICES
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10330444
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Filing Dt:
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12/27/2002
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Publication #:
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Pub Dt:
|
07/03/2003
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Title:
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PROCESS FACILITY HAVING AT LEAST TWO PHYSICAL UNITS EACH HAVING A REDUCED DENSITY OF CONTAMINATING PARTICLES WITH RESPECT TO THE SURROUNDINGS
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Patent #:
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Issue Dt:
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03/14/2006
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Application #:
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10331641
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Filing Dt:
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12/30/2002
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Pub Dt:
|
07/31/2003
| | | | |
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Title:
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PHOTOMASK AND METHOD OF STRUCTURING A PHOTORESIST BY DOUBLE EXPOSURE WITH IMAGING AUXILIARY STRUCTURES AND DIFFERENT EXPOSURE TOOLS
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Patent #:
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Issue Dt:
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08/10/2004
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Application #:
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10337606
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Filing Dt:
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01/07/2003
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Publication #:
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Pub Dt:
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07/08/2004
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Title:
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HIGH RESOLUTION INTERLEAVED DELAY CHAIN
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Patent #:
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Issue Dt:
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09/25/2007
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Application #:
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10338254
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Filing Dt:
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01/07/2003
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Publication #:
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Pub Dt:
|
07/08/2004
| | | | |
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Title:
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HIGH DENSITY PLASMA OXIDATION
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Patent #:
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Issue Dt:
|
03/15/2005
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Application #:
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10338517
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Filing Dt:
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01/08/2003
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Publication #:
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Pub Dt:
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07/22/2004
| | | | |
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Title:
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REDUCED HOT CARRIER INDUCED PARASITIC SIDEWALL DEVICE ACTIVATION IN ISOLATED BURIED CHANNEL DEVICES BY CONDUCTIVE BURIED CHANNEL DEPTH OPTIMIZATION
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Patent #:
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Issue Dt:
|
06/08/2004
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Application #:
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10338798
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Filing Dt:
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01/07/2003
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Title:
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ENCAPSULATION OF FERROELECTRIC CAPACITORS
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Patent #:
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Issue Dt:
|
11/16/2004
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Application #:
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10339031
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Filing Dt:
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01/09/2003
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Publication #:
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Pub Dt:
|
08/28/2003
| | | | |
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Title:
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METHOD FOR STORING DATA IN A MEMORY DEVICE WITH THE POSSIBILITY OF ACCESS TO REDUNDANT MEMORY CELLS
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Patent #:
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Issue Dt:
|
10/19/2004
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Application #:
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10340046
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Filing Dt:
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01/10/2003
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Publication #:
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Pub Dt:
|
07/10/2003
| | | | |
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Title:
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METHOD AND LOGIC/MEMORY MODULE FOR CORRECTING THE DUTY CYCLE OF AT LEAST ONE CONTROL/REFERENCE SIGNAL
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10340047
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Filing Dt:
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01/10/2003
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Publication #:
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Pub Dt:
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07/10/2003
| | | | |
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Title:
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METHOD FOR PROCESSING A SUBSTRATE TO FORM A STRUCTURE
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Patent #:
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Issue Dt:
|
01/11/2005
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Application #:
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10340464
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Filing Dt:
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01/10/2003
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Publication #:
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Pub Dt:
|
07/10/2003
| | | | |
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Title:
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CONTACT BASE WITH DETACHABLE CONTACTS FOR MAKING ELECTRICAL CONTACT WITH AN ELECTRONIC COMPONENT, IN PARTICULAR A MULTIPIN ELECTRONIC COMPONENT, AND MODULE CARRIER
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Patent #:
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Issue Dt:
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01/09/2007
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10340987
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01/13/2003
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Pub Dt:
|
07/17/2003
| | | | |
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Title:
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RESIST FOR FORMING A STRUCTURE FOR ALIGNING AN ELECTRON OR ION BEAM AND TECHNIQUE FOR FORMING THE STRUCTURE
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Patent #:
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Issue Dt:
|
01/25/2005
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Application #:
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10340989
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Filing Dt:
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01/13/2003
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Publication #:
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Pub Dt:
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07/17/2003
| | | | |
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Title:
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INTEGRATED CIRCUIT AND METHOD FOR OPERATING THE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10341503
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Filing Dt:
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01/13/2003
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Publication #:
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Pub Dt:
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07/31/2003
| | | | |
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Title:
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DLL-(DELAY-LOCKED-LOOP) CIRCUIT
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10342901
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Filing Dt:
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01/15/2003
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Publication #:
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Pub Dt:
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05/06/2004
| | | | |
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Title:
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DIGITAL MEMORY CIRCUIT HAVING A PLURALITY OF MEMORY BANKS
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10343844
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Filing Dt:
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07/31/2003
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Publication #:
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Pub Dt:
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01/08/2004
| | | | |
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Title:
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Memory cell arrangement and method of fabricating it
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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10345057
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Filing Dt:
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01/15/2003
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Publication #:
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Pub Dt:
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08/21/2003
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Title:
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APPARATUS FOR CONNECTING SEMICONDUCTOR MODULES
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10348150
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Filing Dt:
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01/21/2003
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Publication #:
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Pub Dt:
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07/24/2003
| | | | |
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Title:
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METHOD FOR PRODUCING A CAVITY IN A MONOCRYSTALLINE SILICON SUBSTRATE AND A SEMICONDUCTOR COMPONENT HAVING A CAVITY IN A MONOCRYSTALLINE SILICON SUBSTRATE WITH AN EPITAXIAL COVERING LAYER
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10348235
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Filing Dt:
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01/21/2003
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Publication #:
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Pub Dt:
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05/06/2004
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Title:
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TWO-STEP MAGNETIC TUNNEL JUNCTION STACK DEPOSITION
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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10348847
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Filing Dt:
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01/21/2003
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Publication #:
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Pub Dt:
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07/22/2004
| | | | |
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Title:
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METHOD OF RESOLVING MISMATCHED GRAPHICAL SYMBOLS IN COMPUTER-AIDED INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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10348928
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Filing Dt:
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01/21/2003
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Publication #:
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Pub Dt:
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07/22/2004
| | | | |
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Title:
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METHOD OF RESOLVING MISSING GRAPHICAL SYMBOLS IN COMPUTER-AIDED INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
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01/03/2006
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Application #:
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10349342
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Filing Dt:
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01/21/2003
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Publication #:
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Pub Dt:
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07/22/2004
| | | | |
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Title:
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METHOD OF RESOLVING MISMATCHED PARAMETERS IN COMPUTER-AIDED INTEGRATED CIRCUIT DESIGN
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Patent #:
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Issue Dt:
|
05/04/2004
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Application #:
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10350482
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Filing Dt:
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01/24/2003
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Pub Dt:
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08/14/2003
| | | | |
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Title:
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DDR MEMORY AND STORAGE METHOD
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10352730
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Filing Dt:
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01/27/2003
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Publication #:
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Pub Dt:
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07/31/2003
| | | | |
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Title:
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MAGNETORESISTIVE MEMORY CELL WITH POLARITY-DEPENDENT RESISTANCE
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Patent #:
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Issue Dt:
|
10/18/2005
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Application #:
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10352735
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Filing Dt:
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01/27/2003
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Publication #:
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Pub Dt:
|
07/24/2003
| | | | |
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Title:
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METHOD FOR DETERMINING THE ABILITY TO PROJECT IMAGES OF INTEGRATED SEMICONDUCTOR CIRCUITS ONTO ALTERNATING PHASE MASKS
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10352824
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Filing Dt:
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01/28/2003
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Publication #:
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Pub Dt:
|
07/31/2003
| | | | |
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Title:
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INTEGRATED CIRCUIT WITH TEMPERATURE SENSOR AND METHOD FOR HEATING THE CIRCUIT
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Patent #:
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Issue Dt:
|
01/06/2004
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Application #:
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10352826
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Filing Dt:
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01/28/2003
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Publication #:
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Pub Dt:
|
07/17/2003
| | | | |
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Title:
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METHOD FOR MANUFACTURING A MULTI-BIT MEMORY CELL
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Patent #:
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Issue Dt:
|
05/25/2004
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Application #:
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10352830
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Filing Dt:
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01/28/2003
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Publication #:
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Pub Dt:
|
07/17/2003
| | | | |
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Title:
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FIELD-EFFECT TRANSISTOR, CIRCUIT CONFIGURATION AND METHOD OF FABRICATING A FIELD-EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10353463
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Filing Dt:
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01/29/2003
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Publication #:
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Pub Dt:
|
08/14/2003
| | | | |
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Title:
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PHOTOLITHOGRAPHIC MASK
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Patent #:
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Issue Dt:
|
05/31/2005
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Application #:
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10353733
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Filing Dt:
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01/29/2003
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Publication #:
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Pub Dt:
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01/20/2005
| | | | |
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Title:
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CHEMICAL MECHANICAL POLISHING (CMP) PROCESS USING FIXED ABRASIVE PADS
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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10356106
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Filing Dt:
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01/31/2003
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Publication #:
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Pub Dt:
|
07/31/2003
| | | | |
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Title:
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PROCESS FOR THE PLASMA ETCHING OF MATERIALS NOT CONTAINING SILICON
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