skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:040632/0001   Pages: 34
Recorded: 11/08/2016
Attorney Dkt #:NAME CHANGE-NXP USA, INC.
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 1087
Page 2 of 11
Pages: 1 2 3 4 5 6 7 8 9 10 11
1
Patent #:
Issue Dt:
04/14/2009
Application #:
11672279
Filing Dt:
02/07/2007
Publication #:
Pub Dt:
08/07/2008
Title:
CIRCUIT FOR USE IN A MULTIPLE BLOCK MEMORY
2
Patent #:
Issue Dt:
07/29/2008
Application #:
11674888
Filing Dt:
02/14/2007
Publication #:
Pub Dt:
08/14/2008
Title:
DOTTED CHANNEL MOSFET AND METHOD
3
Patent #:
Issue Dt:
12/08/2009
Application #:
11676341
Filing Dt:
02/19/2007
Publication #:
Pub Dt:
08/21/2008
Title:
MULTIPLE PORT MEMORY WITH PRIORITIZED WORD LINE DRIVER AND METHOD THEREOF
4
Patent #:
Issue Dt:
04/27/2010
Application #:
11678258
Filing Dt:
02/23/2007
Publication #:
Pub Dt:
08/28/2008
Title:
SHARED LATCH FOR MEMORY TEST/REPAIR AND FUNCTIONAL OPERATIONS
5
Patent #:
Issue Dt:
12/14/2010
Application #:
11678322
Filing Dt:
02/23/2007
Publication #:
Pub Dt:
08/28/2008
Title:
SEMICONDUCTOR FIN INTEGRATION USING A SACRIFICIAL FIN
6
Patent #:
Issue Dt:
08/10/2010
Application #:
11678327
Filing Dt:
02/23/2007
Publication #:
Pub Dt:
08/28/2008
Title:
FORMING SEMICONDUCTOR FINS USING A SACRIFICIAL FIN
7
Patent #:
Issue Dt:
04/28/2009
Application #:
11678330
Filing Dt:
02/23/2007
Publication #:
Pub Dt:
09/06/2007
Title:
RF POWER TRANSISTOR DEVICE WITH METAL ELECTROMIGRATION DESIGN AND METHOD THEREOF
8
Patent #:
Issue Dt:
04/20/2010
Application #:
11678962
Filing Dt:
02/26/2007
Publication #:
Pub Dt:
08/28/2008
Title:
COMPLEMENTARY ZENER TRIGGERED BIPOLAR ESD PROTECTION
9
Patent #:
Issue Dt:
06/22/2010
Application #:
11679512
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
CONDUCTIVE VIA FORMATION UTILIZING ELECTROPLATING
10
Patent #:
Issue Dt:
09/28/2010
Application #:
11679590
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
MULTIPLE ADDRESS AND ARITHMETIC BIT-MODE DATA PROCESSING DEVICE AND METHODS THEREOF
11
Patent #:
Issue Dt:
08/11/2009
Application #:
11680012
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
08/28/2008
Title:
YIELD ANALYSIS AND IMPROVEMENT USING ELECTRICAL SENSITIVITY EXTRACTION
12
Patent #:
Issue Dt:
07/06/2010
Application #:
11680177
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
08/28/2008
Title:
PACKAGED INTEGRATED CIRCUIT
13
Patent #:
Issue Dt:
09/14/2010
Application #:
11680219
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
08/28/2008
Title:
FORMING A SEMICONDUCTOR DEVICE HAVING EPITAXIALLY GROWN SOURCE AND DRAIN REGIONS
14
Patent #:
Issue Dt:
11/16/2010
Application #:
11680430
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
08/28/2008
Title:
APPARATUS AND METHOD FOR REDUCING NOISE IN MIXED-SIGNAL CIRCUITS AND DIGITAL CIRCUITS
15
Patent #:
Issue Dt:
09/01/2009
Application #:
11681421
Filing Dt:
03/02/2007
Publication #:
Pub Dt:
09/04/2008
Title:
INTEGRATED CIRCUIT FUSE ARRAY
16
Patent #:
Issue Dt:
08/31/2010
Application #:
11683236
Filing Dt:
03/07/2007
Publication #:
Pub Dt:
09/11/2008
Title:
SEMICONDUCTOR DEVICE HAVING TILES FOR DUAL-TRENCH INTEGRATION AND METHOD THEREFOR
17
Patent #:
Issue Dt:
02/23/2010
Application #:
11683607
Filing Dt:
03/08/2007
Publication #:
Pub Dt:
09/11/2008
Title:
SYSTEM AND METHOD FOR TESTING AND PROVIDING AN INTEGRATED CIRCUIT HAVING MULTIPLE MODULES OR SUBMODULES
18
Patent #:
Issue Dt:
02/01/2011
Application #:
11683846
Filing Dt:
03/08/2007
Publication #:
Pub Dt:
09/11/2008
Title:
TRENCH FORMATION IN A SEMICONDUCTOR MATERIAL
19
Patent #:
Issue Dt:
07/19/2011
Application #:
11684529
Filing Dt:
03/09/2007
Publication #:
Pub Dt:
09/11/2008
Title:
PIPELINED TAG AND INFORMATION ARRAY ACCESS WITH SPECULATIVE RETRIEVAL OF TAG THAT CORRESPONDS TO INFORMATION ACCESS
20
Patent #:
Issue Dt:
03/23/2010
Application #:
11685027
Filing Dt:
03/12/2007
Publication #:
Pub Dt:
09/18/2008
Title:
SEMICONDUCTOR DEVICE HAVING A METAL CARBIDE GATE WITH AN ELECTROPOSITIVE ELEMENT AND A METHOD OF MAKING THE SAME
21
Patent #:
Issue Dt:
08/12/2014
Application #:
11685297
Filing Dt:
03/13/2007
Publication #:
Pub Dt:
09/18/2008
Title:
PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A CONTROL GATE ELECTRODE, A SEMICONDUCTOR LAYER, AND A SELECT GATE ELECTRODE
22
Patent #:
Issue Dt:
04/20/2010
Application #:
11686439
Filing Dt:
03/15/2007
Publication #:
Pub Dt:
09/18/2008
Title:
METHODS FOR FORMING CASCODE CURRENT MIRRORS
23
Patent #:
Issue Dt:
10/26/2010
Application #:
11689657
Filing Dt:
03/22/2007
Publication #:
Pub Dt:
09/25/2008
Title:
SEMICONDUCTOR DEVICE WITH CAPACITOR AND/OR INDUCTOR AND METHOD OF MAKING
24
Patent #:
Issue Dt:
09/22/2009
Application #:
11692722
Filing Dt:
03/28/2007
Publication #:
Pub Dt:
10/04/2007
Title:
ESD PROTECTION CIRCUIT WITH ISOLATED DIODE ELEMENT AND METHOD THEREOF
25
Patent #:
Issue Dt:
01/05/2010
Application #:
11693829
Filing Dt:
03/30/2007
Publication #:
Pub Dt:
10/02/2008
Title:
PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DISCONTINUOUS STORAGE ELEMENTS WITHIN A DIELECTRIC LAYER
26
Patent #:
Issue Dt:
05/11/2010
Application #:
11694264
Filing Dt:
03/30/2007
Publication #:
Pub Dt:
10/02/2008
Title:
METHOD OF MAKING A SEMICONDUCTOR STRUCTURE UTILIZING SPACER REMOVAL AND SEMICONDUCTOR STRUCTURE
27
Patent #:
Issue Dt:
08/24/2010
Application #:
11694273
Filing Dt:
03/30/2007
Publication #:
Pub Dt:
10/02/2008
Title:
STRUCTURE AND METHOD FOR STRAINED TRANSISTOR DIRECTLY ON INSULATOR
28
Patent #:
Issue Dt:
02/23/2010
Application #:
11695722
Filing Dt:
04/03/2007
Publication #:
Pub Dt:
10/09/2008
Title:
ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY ARRAY AND METHODS OF USING THE SAME
29
Patent #:
Issue Dt:
05/07/2013
Application #:
11697106
Filing Dt:
04/05/2007
Publication #:
Pub Dt:
10/09/2008
Title:
FIRST INTER-LAYER DIELECTRIC STACK FOR NON-VOLATILE MEMORY
30
Patent #:
Issue Dt:
08/10/2010
Application #:
11701651
Filing Dt:
02/02/2007
Publication #:
Pub Dt:
08/07/2008
Title:
DYNAMIC PAD SIZE TO REDUCE SOLDER FATIGUE
31
Patent #:
Issue Dt:
03/20/2012
Application #:
11711327
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
ESTIMATING DELAY OF AN ECHO PATH IN A COMMUNICATION SYSTEM
32
Patent #:
Issue Dt:
04/13/2010
Application #:
11731028
Filing Dt:
03/31/2007
Publication #:
Pub Dt:
10/02/2008
Title:
ON-CHIP DECOUPLING CAPACITANCE AND POWER/GROUND NETWORK WIRE CO-OPTIMIZATION TO REDUCE DYNAMIC NOISE
33
Patent #:
Issue Dt:
11/09/2010
Application #:
11732594
Filing Dt:
04/04/2007
Publication #:
Pub Dt:
10/09/2008
Title:
NOVEL INTERCONNECT FOR CHIP LEVEL POWER DISTRIBUTION
34
Patent #:
Issue Dt:
05/03/2011
Application #:
11733063
Filing Dt:
04/09/2007
Publication #:
Pub Dt:
10/09/2008
Title:
INTEGRATED PASSIVE DEVICE WITH A HIGH RESISTIVITY SUBSTRATE AND METHOD FOR FORMING THE SAME
35
Patent #:
Issue Dt:
11/24/2015
Application #:
11733978
Filing Dt:
04/11/2007
Publication #:
Pub Dt:
10/16/2008
Title:
Techniques for Tracing Processes in a Multi-Threaded Processor
36
Patent #:
Issue Dt:
04/19/2011
Application #:
11734328
Filing Dt:
04/12/2007
Publication #:
Pub Dt:
10/16/2008
Title:
SOI SEMICONDUCTOR DEVICE WITH BODY CONTACT AND METHOD THEREOF
37
Patent #:
Issue Dt:
12/08/2009
Application #:
11736272
Filing Dt:
04/17/2007
Publication #:
Pub Dt:
10/23/2008
Title:
SPACE AND PROCESS EFFICIENT MRAM AND METHOD
38
Patent #:
Issue Dt:
05/19/2009
Application #:
11737492
Filing Dt:
04/19/2007
Publication #:
Pub Dt:
10/23/2008
Title:
METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH A STRESSOR
39
Patent #:
Issue Dt:
09/22/2009
Application #:
11737499
Filing Dt:
04/19/2007
Publication #:
Pub Dt:
10/23/2008
Title:
SEMICONDUCTOR DEVICE WITH HYDROGEN BARRIER AND METHOD THEREFOR
40
Patent #:
Issue Dt:
07/28/2009
Application #:
11738514
Filing Dt:
04/22/2007
Publication #:
Pub Dt:
10/23/2008
Title:
METHOD OF MAKING SOLDER PAD
41
Patent #:
Issue Dt:
10/18/2011
Application #:
11738683
Filing Dt:
04/23/2007
Publication #:
Pub Dt:
10/23/2008
Title:
SEPARATE LAYER FORMATION IN A SEMICONDUCTOR DEVICE
42
Patent #:
Issue Dt:
04/06/2010
Application #:
11740331
Filing Dt:
04/26/2007
Publication #:
Pub Dt:
10/30/2008
Title:
NON-VOLATILE MEMORY HAVING A STATIC VERIFY-READ OUTPUT DATA PATH
43
Patent #:
Issue Dt:
08/31/2010
Application #:
11741192
Filing Dt:
04/27/2007
Publication #:
Pub Dt:
10/30/2008
Title:
LEVEL DETECT CIRCUIT
44
Patent #:
Issue Dt:
10/12/2010
Application #:
11741251
Filing Dt:
04/27/2007
Publication #:
Pub Dt:
10/30/2008
Title:
CLOCK CONTROL MODULE SIMULATOR AND METHOD THEREOF
45
Patent #:
Issue Dt:
01/11/2011
Application #:
11741870
Filing Dt:
04/30/2007
Publication #:
Pub Dt:
10/30/2008
Title:
SHIELDING STRUCTURES FOR SIGNAL PATHS IN ELECTRONIC DEVICES
46
Patent #:
Issue Dt:
08/18/2009
Application #:
11742081
Filing Dt:
04/30/2007
Publication #:
Pub Dt:
10/30/2008
Title:
INVERSE SLOPE ISOLATION AND DUAL SURFACE ORIENTATION INTEGRATION
47
Patent #:
Issue Dt:
12/14/2010
Application #:
11742363
Filing Dt:
04/30/2007
Publication #:
Pub Dt:
10/30/2008
Title:
MOSFET DEVICE INCLUDING A SOURCE WITH ALTERNATING P-TYPE AND N-TYPE REGIONS
48
Patent #:
Issue Dt:
09/07/2010
Application #:
11742778
Filing Dt:
05/01/2007
Publication #:
Pub Dt:
11/06/2008
Title:
DUAL SUBSTRATE ORIENTATION OR BULK ON SOI INTEGRATIONS USING OXIDATION FOR SILICON EPITAXY SPACER FORMATION
49
Patent #:
Issue Dt:
03/16/2010
Application #:
11744581
Filing Dt:
05/04/2007
Publication #:
Pub Dt:
11/06/2008
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH MULTIPLE TENSILE STRESSOR LAYERS
50
Patent #:
Issue Dt:
12/28/2010
Application #:
11744638
Filing Dt:
05/04/2007
Publication #:
Pub Dt:
11/06/2008
Title:
METHOD OF FORMING A TRANSISTOR HAVING MULTIPLE TYPES OF SCHOTTKY JUNCTIONS
51
Patent #:
Issue Dt:
11/11/2008
Application #:
11746126
Filing Dt:
05/09/2007
Publication #:
Pub Dt:
11/13/2008
Title:
LOW VOLTAGE DATA PATH IN MEMORY ARRAY
52
Patent #:
Issue Dt:
09/09/2014
Application #:
11746998
Filing Dt:
05/10/2007
Publication #:
Pub Dt:
11/13/2008
Title:
THREAD DE-EMPHASIS INSTRUCTION FOR MULTITHREADED PROCESSOR
53
Patent #:
Issue Dt:
03/03/2015
Application #:
11748350
Filing Dt:
05/14/2007
Publication #:
Pub Dt:
11/20/2008
Title:
METHOD AND APPARATUS FOR CACHE TRANSACTIONS IN A DATA PROCESSING SYSTEM
54
Patent #:
Issue Dt:
02/10/2009
Application #:
11752051
Filing Dt:
05/22/2007
Publication #:
Pub Dt:
11/27/2008
Title:
BITCELL WITH VARIABLE-CONDUCTANCE TRANSFER GATE AND METHOD THEREOF
55
Patent #:
Issue Dt:
08/30/2011
Application #:
11753003
Filing Dt:
05/24/2007
Title:
TESTER AND A METHOD FOR TESTING AN INTEGRATED CIRCUIT
56
Patent #:
Issue Dt:
08/25/2009
Application #:
11753749
Filing Dt:
05/25/2007
Publication #:
Pub Dt:
11/27/2008
Title:
ANTENNA STRUCTURE FOR INTEGRATED CIRCUIT DIE USING BOND WIRE
57
Patent #:
Issue Dt:
08/25/2009
Application #:
11756187
Filing Dt:
05/31/2007
Publication #:
Pub Dt:
12/04/2008
Title:
METHOD FOR GENERATION, PLACEMENT, AND ROUTING OF TEST STRUCTURES IN TEST CHIPS
58
Patent #:
Issue Dt:
06/02/2009
Application #:
11756192
Filing Dt:
05/31/2007
Publication #:
Pub Dt:
12/04/2008
Title:
INTEGRATED CIRCUIT FEATURING A NON-VOLATILE MEMORY WITH CHARGE/DISCHARGE RAMP RATE CONTROL AND METHOD THEREFOR
59
Patent #:
Issue Dt:
06/14/2011
Application #:
11756231
Filing Dt:
05/31/2007
Publication #:
Pub Dt:
12/04/2008
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE FEATURING A GATE STRESSOR AND SEMICONDUCTOR DEVICE
60
Patent #:
Issue Dt:
08/11/2009
Application #:
11759028
Filing Dt:
06/06/2007
Publication #:
Pub Dt:
12/11/2008
Title:
ONE TIME PROGRAMMABLE ELEMENT SYSTEM IN AN INTEGRATED CIRCUIT
61
Patent #:
Issue Dt:
05/05/2009
Application #:
11759593
Filing Dt:
06/07/2007
Publication #:
Pub Dt:
12/11/2008
Title:
SELF-ALIGNED SPLIT GATE MEMORY CELL AND METHOD OF FORMING
62
Patent #:
Issue Dt:
02/04/2014
Application #:
11759935
Filing Dt:
06/08/2007
Publication #:
Pub Dt:
12/11/2008
Title:
HEAT SPREADER FOR CENTER GATE MOLDING
63
Patent #:
Issue Dt:
03/24/2009
Application #:
11760775
Filing Dt:
06/10/2007
Publication #:
Pub Dt:
12/27/2007
Title:
RF POWER TRANSISTOR DEVICE WITH HIGH PERFORMANCE SHUNT CAPACITOR AND METHOD THEREOF
64
Patent #:
Issue Dt:
03/29/2011
Application #:
11763107
Filing Dt:
06/14/2007
Publication #:
Pub Dt:
12/18/2008
Title:
OPTIMIZATION OF STORAGE DEVICE ACCESSES IN RAID SYSTEMS
65
Patent #:
Issue Dt:
11/09/2010
Application #:
11765891
Filing Dt:
06/20/2007
Publication #:
Pub Dt:
12/25/2008
Title:
EXCEPTION-BASED TIMER CONTROL
66
Patent #:
Issue Dt:
01/10/2012
Application #:
11770295
Filing Dt:
06/28/2007
Publication #:
Pub Dt:
01/01/2009
Title:
PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A PLURALITY OF SINGULATED DIE
67
Patent #:
Issue Dt:
02/23/2010
Application #:
11771721
Filing Dt:
06/29/2007
Publication #:
Pub Dt:
01/01/2009
Title:
METHOD FOR FORMING A DUAL METAL GATE STRUCTURE
68
Patent #:
Issue Dt:
08/18/2015
Application #:
11772655
Filing Dt:
07/02/2007
Publication #:
Pub Dt:
02/04/2010
Title:
Asymmetric Cryptographic Device With Local Private Key Generation and Method Therefor
69
Patent #:
Issue Dt:
11/10/2009
Application #:
11777635
Filing Dt:
07/13/2007
Publication #:
Pub Dt:
01/15/2009
Title:
DYNAMIC VOLTAGE ADJUSTMENT FOR MEMORY
70
Patent #:
Issue Dt:
04/26/2011
Application #:
11777650
Filing Dt:
07/13/2007
Publication #:
Pub Dt:
01/15/2009
Title:
CIRCUIT AND METHOD FOR CORRELATED INPUTS TO A POPULATION COUNT CIRCUIT
71
Patent #:
Issue Dt:
06/07/2011
Application #:
11777664
Filing Dt:
07/13/2007
Publication #:
Pub Dt:
01/15/2009
Title:
POPULATION COUNT APPROXIMATION CIRCUIT AND METHOD THEREOF
72
Patent #:
Issue Dt:
06/23/2015
Application #:
11780900
Filing Dt:
07/20/2007
Publication #:
Pub Dt:
01/22/2009
Title:
ELECTRONIC DEVICE INCLUDING A CAPACITOR AND A PROCESS OF FORMING THE SAME
73
Patent #:
Issue Dt:
06/28/2011
Application #:
11781097
Filing Dt:
07/20/2007
Publication #:
Pub Dt:
01/22/2009
Title:
SYSTEMS AND METHODS FOR EFFICIENT GENERATION OF HASH VALUES OF VARYING BIT WIDTHS
74
Patent #:
Issue Dt:
11/16/2010
Application #:
11781610
Filing Dt:
07/23/2007
Publication #:
Pub Dt:
01/29/2009
Title:
SOURCE/DRAIN STRESSORS FORMED USING IN-SITU EPITAXIAL GROWTH
75
Patent #:
Issue Dt:
03/22/2011
Application #:
11782319
Filing Dt:
07/24/2007
Publication #:
Pub Dt:
01/29/2009
Title:
PROCESS FOR MAKING A SEMICONDUCTOR DEVICE USING PARTIAL ETCHING
76
Patent #:
Issue Dt:
08/07/2012
Application #:
11788184
Filing Dt:
04/18/2007
Publication #:
Pub Dt:
10/23/2008
Title:
SHALLOW TRENCH ISOLATION FOR SOI STRUCTURES COMBINING SIDEWALL SPACER AND BOTTOM LINER
77
Patent #:
Issue Dt:
02/09/2010
Application #:
11788216
Filing Dt:
04/18/2007
Publication #:
Pub Dt:
10/23/2008
Title:
METHOD TO SELECTIVELY MODULATE GATE WORK FUNCTION THROUGH SELECTIVE GE CONDENSATION AND HIGH-K DIELECTRIC LAYER
78
Patent #:
Issue Dt:
09/04/2012
Application #:
11800204
Filing Dt:
05/04/2007
Publication #:
Pub Dt:
11/06/2008
Title:
METHOD TO IMPROVE SOURCE/DRAIN PARASITICS IN VERTICAL DEVICES
79
Patent #:
Issue Dt:
11/03/2009
Application #:
11803097
Filing Dt:
05/11/2007
Publication #:
Pub Dt:
11/13/2008
Title:
METHOD TO CONTROL UNIFORMITY/COMPOSITION OF METAL ELECTRODES, SILICIDES ON TOPOGRAPHY AND DEVICES USING THIS METHOD
80
Patent #:
Issue Dt:
04/26/2011
Application #:
11807745
Filing Dt:
05/29/2007
Publication #:
Pub Dt:
12/04/2008
Title:
METHOD TO FORM A VIA
81
Patent #:
Issue Dt:
08/23/2011
Application #:
11807777
Filing Dt:
05/29/2007
Publication #:
Pub Dt:
12/04/2008
Title:
METHOD FOR FORMING INTERCONNECTS FOR 3-D APPLICATIONS
82
Patent #:
Issue Dt:
05/18/2010
Application #:
11811407
Filing Dt:
06/11/2007
Publication #:
Pub Dt:
04/17/2008
Title:
SYSTEM AND METHOD FOR ELECTROMIGRATION TOLERANT CELL SYNTHESIS
83
Patent #:
Issue Dt:
08/25/2009
Application #:
11825953
Filing Dt:
07/10/2007
Publication #:
Pub Dt:
01/15/2009
Title:
DISPOSABLE ORGANIC SPACERS
84
Patent #:
Issue Dt:
09/21/2010
Application #:
11831394
Filing Dt:
07/31/2007
Publication #:
Pub Dt:
02/05/2009
Title:
MOSFET DEVICE FEATURING A SUPERLATTICE BARRIER LAYER AND METHOD
85
Patent #:
Issue Dt:
05/14/2013
Application #:
11831400
Filing Dt:
07/31/2007
Publication #:
Pub Dt:
02/05/2009
Title:
ISOLATION TRENCH PROCESSING FOR STRAIN CONTROL
86
Patent #:
Issue Dt:
07/10/2012
Application #:
11831651
Filing Dt:
07/31/2007
Publication #:
Pub Dt:
02/05/2009
Title:
REDISTRIBUTED CHIP PACKAGING WITH THERMAL CONTACT TO DEVICE BACKSIDE
87
Patent #:
Issue Dt:
04/17/2012
Application #:
11833360
Filing Dt:
08/03/2007
Publication #:
Pub Dt:
02/14/2008
Title:
MULTI-MODE TRANSCEIVER HAVING TUNABLE HARMONIC TERMINATION CIRCUIT AND METHOD THEREFOR
88
Patent #:
Issue Dt:
05/25/2010
Application #:
11833545
Filing Dt:
08/03/2007
Publication #:
Pub Dt:
02/05/2009
Title:
METHOD AND CIRCUIT FOR PREVENTING HIGH VOLTAGE MEMORY DISTURB
89
Patent #:
Issue Dt:
09/21/2010
Application #:
11835547
Filing Dt:
08/08/2007
Publication #:
Pub Dt:
02/12/2009
Title:
METHOD FOR MAKING A TRANSISTOR WITH A STRESSOR
90
Patent #:
Issue Dt:
10/12/2010
Application #:
11835548
Filing Dt:
08/08/2007
Publication #:
Pub Dt:
02/12/2009
Title:
FINFET MEMORY CELL HAVING A FLOATING GATE AND METHOD THEREFOR
91
Patent #:
Issue Dt:
07/14/2009
Application #:
11835552
Filing Dt:
08/08/2007
Publication #:
Pub Dt:
02/12/2009
Title:
LEVEL SHIFTER
92
Patent #:
Issue Dt:
07/14/2009
Application #:
11835643
Filing Dt:
08/08/2007
Publication #:
Pub Dt:
02/12/2009
Title:
PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A DOPED SEMICONDUCTOR LAYER
93
Patent #:
Issue Dt:
06/14/2011
Application #:
11835680
Filing Dt:
08/08/2007
Publication #:
Pub Dt:
02/12/2009
Title:
STRESS RELIEF OF A SEMICONDUCTOR DEVICE
94
Patent #:
Issue Dt:
06/22/2010
Application #:
11837587
Filing Dt:
08/13/2007
Title:
DEVICE AND METHOD FOR COMPENSATING FOR GROUND VOLTAGE ELEVATIONS
95
Patent #:
Issue Dt:
11/23/2010
Application #:
11846874
Filing Dt:
08/29/2007
Publication #:
Pub Dt:
03/05/2009
Title:
INTERCONNECT IN A MULTI-ELEMENT PACKAGE
96
Patent #:
Issue Dt:
10/13/2009
Application #:
11849155
Filing Dt:
08/31/2007
Publication #:
Pub Dt:
03/05/2009
Title:
VOLTAGE REGULATOR FOR INTEGRATED CIRCUITS
97
Patent #:
Issue Dt:
01/06/2009
Application #:
11849301
Filing Dt:
09/03/2007
Title:
METHOD OF FORMING FLIP-CHIP BUMP CARRIER TYPE PACKAGE
98
Patent #:
Issue Dt:
01/24/2012
Application #:
11849375
Filing Dt:
09/04/2007
Publication #:
Pub Dt:
03/05/2009
Title:
CACHE MEMORY AND A METHOD FOR SERVICING ACCESS REQUESTS
99
Patent #:
Issue Dt:
04/27/2010
Application #:
11851857
Filing Dt:
09/07/2007
Publication #:
Pub Dt:
03/12/2009
Title:
SUBSTRATE HAVING THROUGH-WAFER VIAS AND METHOD OF FORMING
100
Patent #:
Issue Dt:
08/17/2010
Application #:
11852396
Filing Dt:
09/10/2007
Publication #:
Pub Dt:
03/12/2009
Title:
ELECTROSTATIC DISCHARGE CIRCUIT AND METHOD THEREFOR
Assignor
1
Exec Dt:
11/07/2016
Assignee
1
6501 WILLIAM CANNON DRIVE WEST
AUSTIN, TEXAS 78735
Correspondence name and address
NXP USA, INC.
6501 WILLIAM CANNON DRIVE WEST
TX30/OE62
AUSTIN, TX 78735

Search Results as of: 09/23/2024 01:05 PM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT