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Patent #:
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04/14/2009
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Application #:
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11672279
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Filing Dt:
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02/07/2007
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Publication #:
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Pub Dt:
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08/07/2008
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Title:
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CIRCUIT FOR USE IN A MULTIPLE BLOCK MEMORY
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Patent #:
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Issue Dt:
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07/29/2008
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Application #:
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11674888
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Filing Dt:
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02/14/2007
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Publication #:
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Pub Dt:
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08/14/2008
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Title:
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DOTTED CHANNEL MOSFET AND METHOD
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Patent #:
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Issue Dt:
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12/08/2009
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Application #:
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11676341
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Filing Dt:
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02/19/2007
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Publication #:
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Pub Dt:
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08/21/2008
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Title:
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MULTIPLE PORT MEMORY WITH PRIORITIZED WORD LINE DRIVER AND METHOD THEREOF
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Patent #:
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Issue Dt:
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04/27/2010
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Application #:
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11678258
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Filing Dt:
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02/23/2007
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Publication #:
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Pub Dt:
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08/28/2008
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Title:
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SHARED LATCH FOR MEMORY TEST/REPAIR AND FUNCTIONAL OPERATIONS
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Patent #:
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Issue Dt:
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12/14/2010
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Application #:
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11678322
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Filing Dt:
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02/23/2007
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Publication #:
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Pub Dt:
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08/28/2008
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Title:
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SEMICONDUCTOR FIN INTEGRATION USING A SACRIFICIAL FIN
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Patent #:
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Issue Dt:
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08/10/2010
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Application #:
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11678327
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Filing Dt:
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02/23/2007
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Publication #:
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Pub Dt:
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08/28/2008
| | | | |
Title:
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FORMING SEMICONDUCTOR FINS USING A SACRIFICIAL FIN
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Patent #:
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Issue Dt:
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04/28/2009
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Application #:
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11678330
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Filing Dt:
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02/23/2007
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Publication #:
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Pub Dt:
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09/06/2007
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Title:
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RF POWER TRANSISTOR DEVICE WITH METAL ELECTROMIGRATION DESIGN AND METHOD THEREOF
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Patent #:
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Issue Dt:
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04/20/2010
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Application #:
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11678962
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Filing Dt:
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02/26/2007
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Publication #:
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Pub Dt:
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08/28/2008
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Title:
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COMPLEMENTARY ZENER TRIGGERED BIPOLAR ESD PROTECTION
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Patent #:
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Issue Dt:
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06/22/2010
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Application #:
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11679512
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Filing Dt:
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02/27/2007
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Publication #:
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Pub Dt:
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08/28/2008
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Title:
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CONDUCTIVE VIA FORMATION UTILIZING ELECTROPLATING
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Patent #:
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Issue Dt:
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09/28/2010
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Application #:
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11679590
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Filing Dt:
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02/27/2007
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Publication #:
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Pub Dt:
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08/28/2008
| | | | |
Title:
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MULTIPLE ADDRESS AND ARITHMETIC BIT-MODE DATA PROCESSING DEVICE AND METHODS THEREOF
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Patent #:
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Issue Dt:
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08/11/2009
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Application #:
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11680012
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Filing Dt:
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02/28/2007
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Publication #:
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Pub Dt:
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08/28/2008
| | | | |
Title:
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YIELD ANALYSIS AND IMPROVEMENT USING ELECTRICAL SENSITIVITY EXTRACTION
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Patent #:
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Issue Dt:
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07/06/2010
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Application #:
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11680177
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Filing Dt:
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02/28/2007
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Publication #:
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Pub Dt:
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08/28/2008
| | | | |
Title:
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PACKAGED INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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09/14/2010
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Application #:
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11680219
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Filing Dt:
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02/28/2007
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Publication #:
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Pub Dt:
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08/28/2008
| | | | |
Title:
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FORMING A SEMICONDUCTOR DEVICE HAVING EPITAXIALLY GROWN SOURCE AND DRAIN REGIONS
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Patent #:
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Issue Dt:
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11/16/2010
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Application #:
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11680430
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Filing Dt:
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02/28/2007
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Publication #:
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Pub Dt:
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08/28/2008
| | | | |
Title:
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APPARATUS AND METHOD FOR REDUCING NOISE IN MIXED-SIGNAL CIRCUITS AND DIGITAL CIRCUITS
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Patent #:
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Issue Dt:
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09/01/2009
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Application #:
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11681421
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Filing Dt:
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03/02/2007
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Publication #:
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Pub Dt:
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09/04/2008
| | | | |
Title:
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INTEGRATED CIRCUIT FUSE ARRAY
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Patent #:
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Issue Dt:
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08/31/2010
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Application #:
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11683236
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Filing Dt:
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03/07/2007
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Publication #:
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Pub Dt:
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09/11/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICE HAVING TILES FOR DUAL-TRENCH INTEGRATION AND METHOD THEREFOR
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Patent #:
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Issue Dt:
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02/23/2010
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Application #:
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11683607
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Filing Dt:
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03/08/2007
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Publication #:
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Pub Dt:
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09/11/2008
| | | | |
Title:
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SYSTEM AND METHOD FOR TESTING AND PROVIDING AN INTEGRATED CIRCUIT HAVING MULTIPLE MODULES OR SUBMODULES
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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11683846
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Filing Dt:
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03/08/2007
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Publication #:
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Pub Dt:
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09/11/2008
| | | | |
Title:
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TRENCH FORMATION IN A SEMICONDUCTOR MATERIAL
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Patent #:
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Issue Dt:
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07/19/2011
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Application #:
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11684529
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Filing Dt:
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03/09/2007
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Publication #:
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Pub Dt:
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09/11/2008
| | | | |
Title:
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PIPELINED TAG AND INFORMATION ARRAY ACCESS WITH SPECULATIVE RETRIEVAL OF TAG THAT CORRESPONDS TO INFORMATION ACCESS
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Patent #:
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Issue Dt:
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03/23/2010
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Application #:
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11685027
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Filing Dt:
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03/12/2007
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Publication #:
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Pub Dt:
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09/18/2008
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Title:
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SEMICONDUCTOR DEVICE HAVING A METAL CARBIDE GATE WITH AN ELECTROPOSITIVE ELEMENT AND A METHOD OF MAKING THE SAME
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Patent #:
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Issue Dt:
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08/12/2014
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Application #:
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11685297
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Filing Dt:
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03/13/2007
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Publication #:
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Pub Dt:
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09/18/2008
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Title:
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PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A CONTROL GATE ELECTRODE, A SEMICONDUCTOR LAYER, AND A SELECT GATE ELECTRODE
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Patent #:
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Issue Dt:
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04/20/2010
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Application #:
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11686439
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Filing Dt:
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03/15/2007
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Publication #:
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Pub Dt:
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09/18/2008
| | | | |
Title:
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METHODS FOR FORMING CASCODE CURRENT MIRRORS
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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11689657
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Filing Dt:
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03/22/2007
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Publication #:
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Pub Dt:
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09/25/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH CAPACITOR AND/OR INDUCTOR AND METHOD OF MAKING
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Patent #:
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Issue Dt:
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09/22/2009
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Application #:
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11692722
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Filing Dt:
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03/28/2007
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Publication #:
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Pub Dt:
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10/04/2007
| | | | |
Title:
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ESD PROTECTION CIRCUIT WITH ISOLATED DIODE ELEMENT AND METHOD THEREOF
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|
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Patent #:
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|
Issue Dt:
|
01/05/2010
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Application #:
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11693829
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Filing Dt:
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03/30/2007
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Publication #:
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Pub Dt:
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10/02/2008
| | | | |
Title:
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PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DISCONTINUOUS STORAGE ELEMENTS WITHIN A DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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05/11/2010
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Application #:
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11694264
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Filing Dt:
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03/30/2007
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Publication #:
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Pub Dt:
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10/02/2008
| | | | |
Title:
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METHOD OF MAKING A SEMICONDUCTOR STRUCTURE UTILIZING SPACER REMOVAL AND SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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08/24/2010
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Application #:
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11694273
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Filing Dt:
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03/30/2007
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Publication #:
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Pub Dt:
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10/02/2008
| | | | |
Title:
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STRUCTURE AND METHOD FOR STRAINED TRANSISTOR DIRECTLY ON INSULATOR
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Patent #:
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Issue Dt:
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02/23/2010
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Application #:
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11695722
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Filing Dt:
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04/03/2007
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Publication #:
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Pub Dt:
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10/09/2008
| | | | |
Title:
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ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY ARRAY AND METHODS OF USING THE SAME
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Patent #:
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Issue Dt:
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05/07/2013
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Application #:
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11697106
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Filing Dt:
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04/05/2007
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Publication #:
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Pub Dt:
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10/09/2008
| | | | |
Title:
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FIRST INTER-LAYER DIELECTRIC STACK FOR NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
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08/10/2010
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Application #:
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11701651
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Filing Dt:
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02/02/2007
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Publication #:
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Pub Dt:
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08/07/2008
| | | | |
Title:
|
DYNAMIC PAD SIZE TO REDUCE SOLDER FATIGUE
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Patent #:
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|
Issue Dt:
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03/20/2012
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Application #:
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11711327
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Filing Dt:
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02/27/2007
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Publication #:
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Pub Dt:
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08/28/2008
| | | | |
Title:
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ESTIMATING DELAY OF AN ECHO PATH IN A COMMUNICATION SYSTEM
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Patent #:
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|
Issue Dt:
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04/13/2010
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Application #:
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11731028
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Filing Dt:
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03/31/2007
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Publication #:
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|
Pub Dt:
|
10/02/2008
| | | | |
Title:
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ON-CHIP DECOUPLING CAPACITANCE AND POWER/GROUND NETWORK WIRE CO-OPTIMIZATION TO REDUCE DYNAMIC NOISE
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Patent #:
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|
Issue Dt:
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11/09/2010
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Application #:
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11732594
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Filing Dt:
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04/04/2007
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Publication #:
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Pub Dt:
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10/09/2008
| | | | |
Title:
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NOVEL INTERCONNECT FOR CHIP LEVEL POWER DISTRIBUTION
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|
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Patent #:
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Issue Dt:
|
05/03/2011
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Application #:
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11733063
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Filing Dt:
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04/09/2007
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Publication #:
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Pub Dt:
|
10/09/2008
| | | | |
Title:
|
INTEGRATED PASSIVE DEVICE WITH A HIGH RESISTIVITY SUBSTRATE AND METHOD FOR FORMING THE SAME
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|
|
Patent #:
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|
Issue Dt:
|
11/24/2015
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Application #:
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11733978
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Filing Dt:
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04/11/2007
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Publication #:
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Pub Dt:
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10/16/2008
| | | | |
Title:
|
Techniques for Tracing Processes in a Multi-Threaded Processor
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Patent #:
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|
Issue Dt:
|
04/19/2011
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Application #:
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11734328
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Filing Dt:
|
04/12/2007
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Publication #:
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|
Pub Dt:
|
10/16/2008
| | | | |
Title:
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SOI SEMICONDUCTOR DEVICE WITH BODY CONTACT AND METHOD THEREOF
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|
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Patent #:
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|
Issue Dt:
|
12/08/2009
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Application #:
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11736272
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Filing Dt:
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04/17/2007
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Publication #:
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Pub Dt:
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10/23/2008
| | | | |
Title:
|
SPACE AND PROCESS EFFICIENT MRAM AND METHOD
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Patent #:
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|
Issue Dt:
|
05/19/2009
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Application #:
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11737492
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Filing Dt:
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04/19/2007
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Publication #:
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Pub Dt:
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10/23/2008
| | | | |
Title:
|
METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH A STRESSOR
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Patent #:
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|
Issue Dt:
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09/22/2009
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Application #:
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11737499
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Filing Dt:
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04/19/2007
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Publication #:
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Pub Dt:
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10/23/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH HYDROGEN BARRIER AND METHOD THEREFOR
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Patent #:
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|
Issue Dt:
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07/28/2009
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Application #:
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11738514
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Filing Dt:
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04/22/2007
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Publication #:
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|
Pub Dt:
|
10/23/2008
| | | | |
Title:
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METHOD OF MAKING SOLDER PAD
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|
|
Patent #:
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|
Issue Dt:
|
10/18/2011
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Application #:
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11738683
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Filing Dt:
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04/23/2007
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Publication #:
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|
Pub Dt:
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10/23/2008
| | | | |
Title:
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SEPARATE LAYER FORMATION IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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04/06/2010
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Application #:
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11740331
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Filing Dt:
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04/26/2007
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Publication #:
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|
Pub Dt:
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10/30/2008
| | | | |
Title:
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NON-VOLATILE MEMORY HAVING A STATIC VERIFY-READ OUTPUT DATA PATH
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Patent #:
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|
Issue Dt:
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08/31/2010
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Application #:
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11741192
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Filing Dt:
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04/27/2007
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Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
Title:
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LEVEL DETECT CIRCUIT
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Patent #:
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|
Issue Dt:
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10/12/2010
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Application #:
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11741251
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Filing Dt:
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04/27/2007
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Publication #:
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Pub Dt:
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10/30/2008
| | | | |
Title:
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CLOCK CONTROL MODULE SIMULATOR AND METHOD THEREOF
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|
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Patent #:
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|
Issue Dt:
|
01/11/2011
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Application #:
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11741870
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Filing Dt:
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04/30/2007
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Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
Title:
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SHIELDING STRUCTURES FOR SIGNAL PATHS IN ELECTRONIC DEVICES
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|
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Patent #:
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|
Issue Dt:
|
08/18/2009
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Application #:
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11742081
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Filing Dt:
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04/30/2007
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Publication #:
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|
Pub Dt:
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10/30/2008
| | | | |
Title:
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INVERSE SLOPE ISOLATION AND DUAL SURFACE ORIENTATION INTEGRATION
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|
|
Patent #:
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|
Issue Dt:
|
12/14/2010
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Application #:
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11742363
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Filing Dt:
|
04/30/2007
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Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
MOSFET DEVICE INCLUDING A SOURCE WITH ALTERNATING P-TYPE AND N-TYPE REGIONS
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|
|
Patent #:
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|
Issue Dt:
|
09/07/2010
|
Application #:
|
11742778
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Filing Dt:
|
05/01/2007
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Publication #:
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|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
DUAL SUBSTRATE ORIENTATION OR BULK ON SOI INTEGRATIONS USING OXIDATION FOR SILICON EPITAXY SPACER FORMATION
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|
Patent #:
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|
Issue Dt:
|
03/16/2010
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Application #:
|
11744581
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Filing Dt:
|
05/04/2007
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Publication #:
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|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH MULTIPLE TENSILE STRESSOR LAYERS
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|
|
Patent #:
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|
Issue Dt:
|
12/28/2010
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Application #:
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11744638
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Filing Dt:
|
05/04/2007
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Publication #:
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|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
METHOD OF FORMING A TRANSISTOR HAVING MULTIPLE TYPES OF SCHOTTKY JUNCTIONS
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|
Patent #:
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|
Issue Dt:
|
11/11/2008
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Application #:
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11746126
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Filing Dt:
|
05/09/2007
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Publication #:
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|
Pub Dt:
|
11/13/2008
| | | | |
Title:
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LOW VOLTAGE DATA PATH IN MEMORY ARRAY
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|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
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Application #:
|
11746998
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Filing Dt:
|
05/10/2007
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Publication #:
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|
Pub Dt:
|
11/13/2008
| | | | |
Title:
|
THREAD DE-EMPHASIS INSTRUCTION FOR MULTITHREADED PROCESSOR
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|
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Patent #:
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Issue Dt:
|
03/03/2015
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Application #:
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11748350
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Filing Dt:
|
05/14/2007
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Publication #:
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Pub Dt:
|
11/20/2008
| | | | |
Title:
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METHOD AND APPARATUS FOR CACHE TRANSACTIONS IN A DATA PROCESSING SYSTEM
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Patent #:
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Issue Dt:
|
02/10/2009
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Application #:
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11752051
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Filing Dt:
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05/22/2007
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Publication #:
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Pub Dt:
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11/27/2008
| | | | |
Title:
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BITCELL WITH VARIABLE-CONDUCTANCE TRANSFER GATE AND METHOD THEREOF
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Patent #:
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Issue Dt:
|
08/30/2011
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Application #:
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11753003
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Filing Dt:
|
05/24/2007
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Title:
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TESTER AND A METHOD FOR TESTING AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
08/25/2009
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Application #:
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11753749
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Filing Dt:
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05/25/2007
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Publication #:
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Pub Dt:
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11/27/2008
| | | | |
Title:
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ANTENNA STRUCTURE FOR INTEGRATED CIRCUIT DIE USING BOND WIRE
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Patent #:
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Issue Dt:
|
08/25/2009
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Application #:
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11756187
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Filing Dt:
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05/31/2007
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Publication #:
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Pub Dt:
|
12/04/2008
| | | | |
Title:
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METHOD FOR GENERATION, PLACEMENT, AND ROUTING OF TEST STRUCTURES IN TEST CHIPS
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Patent #:
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Issue Dt:
|
06/02/2009
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Application #:
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11756192
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Filing Dt:
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05/31/2007
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Publication #:
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Pub Dt:
|
12/04/2008
| | | | |
Title:
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INTEGRATED CIRCUIT FEATURING A NON-VOLATILE MEMORY WITH CHARGE/DISCHARGE RAMP RATE CONTROL AND METHOD THEREFOR
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Patent #:
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06/14/2011
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11756231
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05/31/2007
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12/04/2008
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Title:
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08/11/2009
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11759028
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06/06/2007
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12/11/2008
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ONE TIME PROGRAMMABLE ELEMENT SYSTEM IN AN INTEGRATED CIRCUIT
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05/05/2009
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11759593
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06/07/2007
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12/11/2008
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02/04/2014
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11759935
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06/08/2007
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12/11/2008
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03/24/2009
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11760775
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06/10/2007
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12/27/2007
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03/29/2011
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06/14/2007
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12/18/2008
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OPTIMIZATION OF STORAGE DEVICE ACCESSES IN RAID SYSTEMS
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11/09/2010
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11765891
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06/20/2007
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12/25/2008
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01/10/2012
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06/28/2007
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01/01/2009
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PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A PLURALITY OF SINGULATED DIE
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02/23/2010
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11771721
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06/29/2007
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01/01/2009
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Title:
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METHOD FOR FORMING A DUAL METAL GATE STRUCTURE
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08/18/2015
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11772655
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07/02/2007
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02/04/2010
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Title:
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Asymmetric Cryptographic Device With Local Private Key Generation and Method Therefor
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11/10/2009
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11777635
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07/13/2007
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01/15/2009
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DYNAMIC VOLTAGE ADJUSTMENT FOR MEMORY
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04/26/2011
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07/13/2007
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01/15/2009
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CIRCUIT AND METHOD FOR CORRELATED INPUTS TO A POPULATION COUNT CIRCUIT
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06/07/2011
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07/13/2007
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01/15/2009
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06/23/2015
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07/20/2007
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01/22/2009
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ELECTRONIC DEVICE INCLUDING A CAPACITOR AND A PROCESS OF FORMING THE SAME
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06/28/2011
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11781097
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07/20/2007
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01/22/2009
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SYSTEMS AND METHODS FOR EFFICIENT GENERATION OF HASH VALUES OF VARYING BIT WIDTHS
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11/16/2010
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11781610
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07/23/2007
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01/29/2009
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03/22/2011
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11782319
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07/24/2007
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01/29/2009
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PROCESS FOR MAKING A SEMICONDUCTOR DEVICE USING PARTIAL ETCHING
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08/07/2012
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11788184
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04/18/2007
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10/23/2008
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SHALLOW TRENCH ISOLATION FOR SOI STRUCTURES COMBINING SIDEWALL SPACER AND BOTTOM LINER
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02/09/2010
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11788216
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04/18/2007
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10/23/2008
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METHOD TO SELECTIVELY MODULATE GATE WORK FUNCTION THROUGH SELECTIVE GE CONDENSATION AND HIGH-K DIELECTRIC LAYER
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09/04/2012
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11800204
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05/04/2007
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11/06/2008
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METHOD TO IMPROVE SOURCE/DRAIN PARASITICS IN VERTICAL DEVICES
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11/03/2009
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11803097
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05/11/2007
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11/13/2008
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METHOD TO CONTROL UNIFORMITY/COMPOSITION OF METAL ELECTRODES, SILICIDES ON TOPOGRAPHY AND DEVICES USING THIS METHOD
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04/26/2011
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11807745
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05/29/2007
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12/04/2008
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METHOD TO FORM A VIA
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08/23/2011
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11807777
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05/29/2007
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12/04/2008
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METHOD FOR FORMING INTERCONNECTS FOR 3-D APPLICATIONS
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05/18/2010
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11811407
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06/11/2007
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04/17/2008
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SYSTEM AND METHOD FOR ELECTROMIGRATION TOLERANT CELL SYNTHESIS
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08/25/2009
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11825953
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07/10/2007
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01/15/2009
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DISPOSABLE ORGANIC SPACERS
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09/21/2010
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11831394
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07/31/2007
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02/05/2009
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MOSFET DEVICE FEATURING A SUPERLATTICE BARRIER LAYER AND METHOD
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05/14/2013
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11831400
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07/31/2007
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02/05/2009
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ISOLATION TRENCH PROCESSING FOR STRAIN CONTROL
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07/10/2012
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11831651
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07/31/2007
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02/05/2009
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REDISTRIBUTED CHIP PACKAGING WITH THERMAL CONTACT TO DEVICE BACKSIDE
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04/17/2012
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11833360
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08/03/2007
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02/14/2008
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MULTI-MODE TRANSCEIVER HAVING TUNABLE HARMONIC TERMINATION CIRCUIT AND METHOD THEREFOR
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05/25/2010
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11833545
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08/03/2007
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02/05/2009
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METHOD AND CIRCUIT FOR PREVENTING HIGH VOLTAGE MEMORY DISTURB
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09/21/2010
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11835547
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08/08/2007
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02/12/2009
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METHOD FOR MAKING A TRANSISTOR WITH A STRESSOR
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10/12/2010
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11835548
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08/08/2007
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02/12/2009
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FINFET MEMORY CELL HAVING A FLOATING GATE AND METHOD THEREFOR
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07/14/2009
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11835552
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08/08/2007
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02/12/2009
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LEVEL SHIFTER
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07/14/2009
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11835643
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08/08/2007
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02/12/2009
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PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A DOPED SEMICONDUCTOR LAYER
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06/14/2011
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11835680
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08/08/2007
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02/12/2009
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STRESS RELIEF OF A SEMICONDUCTOR DEVICE
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06/22/2010
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11837587
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08/13/2007
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DEVICE AND METHOD FOR COMPENSATING FOR GROUND VOLTAGE ELEVATIONS
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11/23/2010
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11846874
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08/29/2007
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03/05/2009
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INTERCONNECT IN A MULTI-ELEMENT PACKAGE
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10/13/2009
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11849155
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08/31/2007
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03/05/2009
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VOLTAGE REGULATOR FOR INTEGRATED CIRCUITS
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01/06/2009
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11849301
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09/03/2007
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Title:
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METHOD OF FORMING FLIP-CHIP BUMP CARRIER TYPE PACKAGE
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01/24/2012
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11849375
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09/04/2007
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03/05/2009
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CACHE MEMORY AND A METHOD FOR SERVICING ACCESS REQUESTS
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04/27/2010
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11851857
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09/07/2007
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03/12/2009
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08/17/2010
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11852396
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09/10/2007
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03/12/2009
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Title:
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ELECTROSTATIC DISCHARGE CIRCUIT AND METHOD THEREFOR
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