|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2010
|
Application #:
|
10546938
|
Filing Dt:
|
01/25/2007
|
|
Publication #:
|
|
Pub Dt:
|
07/26/2007
| | | | |
|
Title:
|
MULTI-PROTOCOL MEMORY CARD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2009
|
Application #:
|
10566454
|
Filing Dt:
|
08/07/2006
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2007
| | | | |
|
Title:
|
METHOD FOR APPLYING REWIRING TO A PANEL WHILE COMPENSATING FOR POSITION ERRORS OF SEMICONDUCTOR CHIPS IN COMPONENT POSITIONS OF THE PANEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
10569859
|
Filing Dt:
|
12/07/2006
|
|
Publication #:
|
|
Pub Dt:
|
07/05/2007
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING A SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2008
|
Application #:
|
10574236
|
Filing Dt:
|
01/18/2007
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2007
| | | | |
|
Title:
|
CLOCK RECEIVER CIRCUIT DEVICE, IN PARTICULAR FOR SEMI-CONDUCTOR COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2011
|
Application #:
|
10577173
|
Filing Dt:
|
10/27/2009
|
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH PLASTIC PACKAGE MOLDING COMPOUND, SEMICONDUCTOR CHIP AND LEADFRAME AND METHOD FOR PRODUCING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
10585151
|
Filing Dt:
|
10/16/2007
|
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
|
Title:
|
VOLTAGE REGULATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2008
|
Application #:
|
10599428
|
Filing Dt:
|
11/06/2006
|
|
Publication #:
|
|
Pub Dt:
|
02/14/2008
| | | | |
|
Title:
|
METHOD FOR DETERMINING A RADIATION POWER AND AN EXPOSURE APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10600034
|
Filing Dt:
|
06/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
|
Title:
|
SELF-ALIGNED MASK TO REDUCE CELL LAYOUT AREA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
10600057
|
Filing Dt:
|
06/20/2003
|
|
Title:
|
SUBTRACTIVE STUD FORMATION FOR MRAM MANUFACTURING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2004
|
Application #:
|
10600408
|
Filing Dt:
|
06/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/26/2004
| | | | |
|
Title:
|
CIRCUIT CONFIGURATION FOR DRIVING A PROGRAMMABLE LINK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2004
|
Application #:
|
10600661
|
Filing Dt:
|
06/20/2003
|
|
Title:
|
MAGNETIC TUNNEL JUNCTION PATTERNING USING SIC OR SIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10600911
|
Filing Dt:
|
06/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/19/2004
| | | | |
|
Title:
|
CIRCUIT CONFIGURATION FOR DRIVING A PROGRAMMABLE LINK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10600916
|
Filing Dt:
|
06/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2004
| | | | |
|
Title:
|
CIRCUIT CONFIGURATION FOR LEVEL BOOSTING, IN PARTICULAR FOR DRIVING A PROGRAMMABLE LINK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2005
|
Application #:
|
10600920
|
Filing Dt:
|
06/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/23/2004
| | | | |
|
Title:
|
METHOD OF PATTERNING A MAGNETIC MEMORY CELL BOTTOM ELECTRODE BEFORE MAGNETIC STACK DEPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10600961
|
Filing Dt:
|
06/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
METHOD FOR INCREASING THE INPUT VOLTAGE OF AN INTEGRATED CIRCUIT WITH A TWO-STAGE CHARGE PUMP, AND INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
10601236
|
Filing Dt:
|
06/20/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/08/2004
| | | | |
|
Title:
|
CIRCUIT CONFIGURATION FOR DRIVING A PROGRAMMABLE LINK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
10601537
|
Filing Dt:
|
06/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/18/2004
| | | | |
|
Title:
|
METHOD FOR ON-DEMAND GENERATION OF INDIVIDUAL RANDOM NUMBERS OF A SEQUENCE OF RANDOM NUMBERS OF A 1/F NOISE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
10601639
|
Filing Dt:
|
06/23/2003
|
|
Title:
|
SEMICONDUCTOR PRODUCT CONTAINER AND SYSTEM FOR HANDLING A SEMICONDUCTOR PRODUCT CONTAINER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2004
|
Application #:
|
10602403
|
Filing Dt:
|
06/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
|
Title:
|
METHOD FOR STORING DATA, METHOD FOR READING DATA, APPARATUS FOR STORING DATA AND APPARATUS FOR READING DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10604323
|
Filing Dt:
|
07/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/16/2004
| | | | |
|
Title:
|
BARRIER STACK WITH IMPROVED BARRIER PROPERTIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10604533
|
Filing Dt:
|
07/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF FABRICATING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2005
|
Application #:
|
10604731
|
Filing Dt:
|
08/13/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
|
Title:
|
SELF-ALIGNED DRAIN/CHANNEL JUNCTION IN VERTICAL PASS TRANSISTOR DRAM CELL DESIGN FOR DEVICE SCALING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10605604
|
Filing Dt:
|
10/13/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
METHOD FOR IMPROVED ALIGNMENT OF MAGNETIC TUNNEL JUNCTION ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
10606069
|
Filing Dt:
|
06/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/19/2004
| | | | |
|
Title:
|
METHOD FOR FABRICATING MICROSTRUCTURES AND ARRANGEMENT OF MICROSTRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
10607518
|
Filing Dt:
|
06/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/15/2004
| | | | |
|
Title:
|
METHOD FOR CHECKING THE REFRESH FUNCTION OF AN INFORMATION MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2007
|
Application #:
|
10609453
|
Filing Dt:
|
06/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
|
Title:
|
POLY-O-HYDROXYAMIDE, POLYBENZOXAZOLE FROM THE POLY-O-HYDROXYAMIDE, ELECTRONIC COMPONENT INCLUDING A POLYBENZOXAZOLE, AND PROCESSES FOR PRODUCING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2004
|
Application #:
|
10609455
|
Filing Dt:
|
06/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2004
| | | | |
|
Title:
|
CONFIGURATION FOR TESTING SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
10609456
|
Filing Dt:
|
06/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
|
Title:
|
BIS-O-AMINOPHENOLS AND PROCESSES FOR PRODUCING BIS-O-AMINOPHENOLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2004
|
Application #:
|
10609460
|
Filing Dt:
|
06/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2004
| | | | |
|
Title:
|
POLY-O-HYDROXYAMIDE, POLYBENZOXAZOLE, AND ELECTRONIC COMPONENT INCLUDING A DIELECTRIC HAVING A BARRIER EFFECT AGAINST COPPER DIFFUSION, AND PROCESSES FOR PREPARING POLY-O-HYDROXYAMIDES, POLYBENZOXAZOLES, AND ELECTRONIC COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2005
|
Application #:
|
10609464
|
Filing Dt:
|
06/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/19/2004
| | | | |
|
Title:
|
METHOD FOR CHARACTERIZING AND SIMULATING A CHEMICAL MECHANICAL POLISHING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
10609871
|
Filing Dt:
|
06/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/08/2004
| | | | |
|
Title:
|
CONFIGURATION, PLUG-IN MOUNT AND CONTACT ELEMENT FOR FIXING AND CONTACTING SWITCHING ASSEMBLIES ON A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10609873
|
Filing Dt:
|
06/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/08/2004
| | | | |
|
Title:
|
METHOD, ADAPTER CARD AND CONFIGURATION FOR AN INSTALLATION OF MEMORY MODULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10610186
|
Filing Dt:
|
06/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2004
| | | | |
|
Title:
|
MEMORY CHIP WITH TEST LOGIC TAKING INTO CONSIDERATION THE ADDRESS OF A REDUNDANT WORD LINE AND METHOD FOR TESTING A MEMORY CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2005
|
Application #:
|
10610241
|
Filing Dt:
|
06/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
|
Title:
|
CONNECTOR FOR A PLURALITY OF SWITCHING ASSEMBLIES WITH COMPATIBLE INTERFACES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10610609
|
Filing Dt:
|
07/01/2003
|
|
Title:
|
RECESSED METAL LINES FOR PROTECTIVE ENCLOSURE IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
10611067
|
Filing Dt:
|
07/01/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/06/2005
| | | | |
|
Title:
|
METHOD OF INSPECTING A MASK OR RETICLE FOR DETECTING A DEFECT, AND MASK OR RETICLE INSPECTION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
10613367
|
Filing Dt:
|
07/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2004
| | | | |
|
Title:
|
TEST CIRCUIT AND METHOD FOR TESTING AN INTEGRATED MEMORY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2005
|
Application #:
|
10613381
|
Filing Dt:
|
07/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/22/2004
| | | | |
|
Title:
|
LEVEL SHIFTER WITHOUT DUTYCYCLE DISTORTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10614430
|
Filing Dt:
|
07/07/2003
|
|
Title:
|
METHOD FOR MAKING CONTACT WITH A DOPING REGION OF A SEMICONDUCTOR COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
10615567
|
Filing Dt:
|
07/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/08/2004
| | | | |
|
Title:
|
VERTICAL TRANSISTOR, AND A METHOD FOR PRODUCING A VERTICAL TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2005
|
Application #:
|
10615630
|
Filing Dt:
|
07/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
METHOD OF FORMING SHALLOW TRENCH ISOLATION USING DEEP TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10616396
|
Filing Dt:
|
07/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
|
Title:
|
METHOD FOR FABRICATING TRENCH CAPACITORS FOR INTEGRATED SEMICONDUCTOR MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10618056
|
Filing Dt:
|
07/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/18/2004
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR CALIBRATING SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
10618333
|
Filing Dt:
|
07/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
|
Title:
|
STRUCTURE AND METHOD OF MULTIPLEXING BITLINE SIGNALS WITHIN A MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2005
|
Application #:
|
10619014
|
Filing Dt:
|
07/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2004
| | | | |
|
Title:
|
CIRCUIT CONFIGURATION FOR CONTROLLING LOAD-DEPENDENT DRIVER STRENGTHS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
10619157
|
Filing Dt:
|
07/14/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
INTEGRATED MEMORY AND METHOD FOR TESTING THE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2004
|
Application #:
|
10619290
|
Filing Dt:
|
07/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/19/2004
| | | | |
|
Title:
|
CIRCUIT CONFIGURATION FOR THE BIT-PARALLEL OUTPUTTING OF A DATA WORD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
10619970
|
Filing Dt:
|
07/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2004
| | | | |
|
Title:
|
INTEGRATED SEMICONDUCTOR MEMORY AND FABRICATION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2005
|
Application #:
|
10620092
|
Filing Dt:
|
07/15/2003
|
|
Title:
|
CIRCUIT ELEMENT WITH TIMING CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10620570
|
Filing Dt:
|
07/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2004
| | | | |
|
Title:
|
PVD METHOD AND PVD APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2005
|
Application #:
|
10620587
|
Filing Dt:
|
07/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
|
Title:
|
CONFIGURATION AND METHOD FOR CHECKING AN ADDRESS GENERATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10620989
|
Filing Dt:
|
07/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR ACTIVE TERMINATION OF HIGH-FREQUENCY SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10621535
|
Filing Dt:
|
07/17/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
METHOD FOR CORRECTING LOCAL LOADING EFFECTS IN THE ETCHING OF PHOTOMASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
10622050
|
Filing Dt:
|
07/17/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/18/2004
| | | | |
|
Title:
|
WAFER LIFTING DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10623067
|
Filing Dt:
|
07/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/19/2004
| | | | |
|
Title:
|
METHOD OF GENERATING A TEST PATTERN FOR SIMULATING AND/OR TESTING THE LAYOUT OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10623078
|
Filing Dt:
|
07/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
|
Title:
|
SYSTEM OF MULTIPLEXED DATA LINES IN A DYNAMIC RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
10623461
|
Filing Dt:
|
07/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
|
Title:
|
MULTI-LAYER BARRIER ALLOWING RECOVERY ANNEAL FOR FERROELECTRIC CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
10623815
|
Filing Dt:
|
07/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2004
| | | | |
|
Title:
|
SEMICONDUCTOR COMPONENT WITH ESD PROTECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
10623824
|
Filing Dt:
|
07/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/22/2004
| | | | |
|
Title:
|
SELECTION DEVICE FOR A SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10623831
|
Filing Dt:
|
07/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2004
| | | | |
|
Title:
|
CIRCUIT AND METHOD FOR WRITING AND READING DATA FROM A DYNAMIC MEMORY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2005
|
Application #:
|
10624031
|
Filing Dt:
|
07/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
|
Title:
|
MEMORY DEVICE AND METHOD OF STORING FAIL ADDRESSES OF A MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10625483
|
Filing Dt:
|
07/22/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
|
Title:
|
FORMATION OF A CONTACT IN A DEVICE, AND THE DEVICE INCLUDING THE CONTACT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
10625495
|
Filing Dt:
|
07/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/08/2004
| | | | |
|
Title:
|
METHOD FOR CONNECTING AN INTEGRATED CIRCUIT TO A SUBSTRATE AND CORRESPONDING CIRCUIT ARRANGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10625962
|
Filing Dt:
|
07/24/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
|
Title:
|
ARRAY TRANSISTOR AMPLIFICATION METHOD AND APPARATUS FOR DYNAMIC RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2005
|
Application #:
|
10626955
|
Filing Dt:
|
07/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/05/2004
| | | | |
|
Title:
|
INTEGRATED SYNCHRONOUS MEMORY AND MEMORY CONFIGURATION HAVING A MEMORY MODULE WITH AT LEAST ONE SYNCHRONOUS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
10626956
|
Filing Dt:
|
07/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/05/2004
| | | | |
|
Title:
|
METHOD FOR FABRICATING A VERTICAL TRANSISTOR, AND SEMICONDUCTOR MEMORY CELL HAVING A TRENCH CAPACITOR AND AN ASSOCIATED VERTICAL SELECTION TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2005
|
Application #:
|
10626957
|
Filing Dt:
|
07/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/29/2004
| | | | |
|
Title:
|
SEMICONDUCTOR CIRCUIT STRUCTURE AND METHOD FOR FABRICATING THE SEMICONDUCTOR CIRCUIT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10627841
|
Filing Dt:
|
07/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/12/2004
| | | | |
|
Title:
|
CIRCUIT CONFIGURATION FOR READING OUT A PROGRAMMABLE LINK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2004
|
Application #:
|
10627906
|
Filing Dt:
|
07/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/29/2004
| | | | |
|
Title:
|
POLYMERIZABLE COMPOSITION, POLYMER, RESIST, AND PROCESS FOR ELECTRON BEAM LITHOGRAPHY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2005
|
Application #:
|
10628149
|
Filing Dt:
|
07/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
METHOD OF FORMING ISOLATION DUMMY FILL STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10629326
|
Filing Dt:
|
07/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
FABRICATION OF A FERAM CAPACITOR USING A NOBLE METAL HARDMASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2005
|
Application #:
|
10630373
|
Filing Dt:
|
07/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
SEMICONDUCTOR TRENCH STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10630632
|
Filing Dt:
|
07/29/2003
|
|
Title:
|
SEMICONDUCTOR CIRCUIT MODULE AND METHOD FOR FABRICATING SEMICONDUCTOR CIRCUIT MODULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10631356
|
Filing Dt:
|
07/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/05/2004
| | | | |
|
Title:
|
METHOD FOR TESTING A SEMICONDUCTOR MEMORY HAVING A PLURALITY OF MEMORY BANKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2005
|
Application #:
|
10631394
|
Filing Dt:
|
07/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
OFF CHIP DRIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2004
|
Application #:
|
10631554
|
Filing Dt:
|
07/31/2003
|
|
Title:
|
METHOD FOR FABRICATING AN ELECTRODE ARRANGEMENT FOR CHARGE STORAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10631587
|
Filing Dt:
|
07/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/01/2004
| | | | |
|
Title:
|
MICROELECTRONIC PROCESS AND STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
10632365
|
Filing Dt:
|
07/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
MAGNETICALLY LINED CONDUCTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10632752
|
Filing Dt:
|
08/01/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
|
Title:
|
REFLECTIVE MIRROR FOR LITHOGRAPHIC EXPOSURE AND PRODUCTION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
10633996
|
Filing Dt:
|
08/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/18/2004
| | | | |
|
Title:
|
INTEGRATED MEMORY AND METHOD FOR CHECKING THE FUNCTIONING OF AN INTEGRATED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2005
|
Application #:
|
10634242
|
Filing Dt:
|
08/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2004
| | | | |
|
Title:
|
METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE AND CORRESPONDING SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10635583
|
Filing Dt:
|
08/06/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2004
| | | | |
|
Title:
|
METHOD FOR EXPOSING AT LEAST ONE OR AT LEAST TWO SEMICONDUCTOR WAFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2006
|
Application #:
|
10636369
|
Filing Dt:
|
08/06/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
MEMORY CELL SIGNAL WINDOW TESTING APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10637899
|
Filing Dt:
|
08/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2004
| | | | |
|
Title:
|
INTEGRATED CIRCUIT AND METHOD FOR PRODUCING A COMPOSITE COMPRISING A TESTED INTEGRATED CIRCUIT AND AN ELECTRICAL DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2005
|
Application #:
|
10638594
|
Filing Dt:
|
08/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
09/23/2004
| | | | |
|
Title:
|
METHOD FOR PRODUCING FERROELECTRIC CAPACITORS AND INTEGRATED SEMICONDUCTOR MEMORY CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
10638673
|
Filing Dt:
|
08/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
|
Title:
|
METHOD TO ETCH POLY SI GATE STACKS WITH RAISED STI STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10639379
|
Filing Dt:
|
08/12/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/22/2004
| | | | |
|
Title:
|
RAM MEMORY CIRCUIT AND METHOD FOR MEMORY OPERATION AT A MULTIPLIED DATA RATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2007
|
Application #:
|
10640230
|
Filing Dt:
|
08/13/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/19/2004
| | | | |
|
Title:
|
PHASE DETECTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
10641812
|
Filing Dt:
|
08/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
|
Title:
|
REDUCED POWER CONSUMPTION IN INTEGRATED CIRCUITS WITH FUSE CONTROLLED REDUNDANT CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2005
|
Application #:
|
10642063
|
Filing Dt:
|
08/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/17/2004
| | | | |
|
Title:
|
METHOD OF PRODUCING A SEMICONDUCTOR COMPONENT HAVING A COMPLIANT BUFFER LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10642092
|
Filing Dt:
|
08/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
|
Title:
|
METHOD FOR FABRICATING CONNECTION REGIONS OF AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT HAVING CONNECTION REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
10642856
|
Filing Dt:
|
08/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
|
Title:
|
METHOD FOR WRITING TO MAGNETORESISTIVE MEMORY CELLS AND MAGNETORESISTIVE MEMORY WHICH CAN BE WRITTEN TO BY THE METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2005
|
Application #:
|
10643820
|
Filing Dt:
|
08/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/12/2004
| | | | |
|
Title:
|
CONFIGURATION AND A METHOD FOR REDUCING CONTAMINATION WITH PARTICLES ON A SUBSTRATE IN A PROCESS TOOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2005
|
Application #:
|
10645053
|
Filing Dt:
|
08/21/2003
|
|
Title:
|
SHIFT REGISTER CHAIN FOR TRIMMING GENERATORS FOR AN INTEGRATED SEMICONDUCTOR APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10646166
|
Filing Dt:
|
08/22/2003
|
|
Title:
|
SEMICONDUCTOR MEMORY APPARATUS WITH VARIABLE CONTACT CONNECTIONS AND A CORRESPONDING SEMICONDUCTOR APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2004
|
Application #:
|
10647614
|
Filing Dt:
|
08/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/26/2004
| | | | |
|
Title:
|
METHOD FOR ETCHING A HARD MASK LAYER AND A METAL LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10648493
|
Filing Dt:
|
08/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
SYSTEM AND METHOD OF CORRECTING MASK RULE VIOLATIONS AFTER OPTICAL PROXIMITY CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2006
|
Application #:
|
10649408
|
Filing Dt:
|
08/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
|
Title:
|
INTEGRATED MEMORY AND METHOD FOR SETTING THE LATENCY IN THE INTEGRATED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
10649411
|
Filing Dt:
|
08/27/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2004
| | | | |
|
Title:
|
PROCESS FOR PRODUCING AND REMOVING A MASK LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2004
|
Application #:
|
10650818
|
Filing Dt:
|
08/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/22/2004
| | | | |
|
Title:
|
INTEGRATED DRAM MEMORY COMPONENT
|
|
