|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10892420
|
Filing Dt:
|
07/15/2004
|
Publication #:
|
|
Pub Dt:
|
01/19/2006
| | | | |
Title:
|
POWER ON RESET CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10892693
|
Filing Dt:
|
07/16/2004
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
Title:
|
DEVICE INCLUDING AN AMORPHOUS CARBON LAYER FOR IMPROVED ADHESION OF ORGANIC LAYERS AND METHOD OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10893034
|
Filing Dt:
|
07/16/2004
|
Publication #:
|
|
Pub Dt:
|
01/19/2006
| | | | |
Title:
|
AUTOMATIC GAIN CONTROL FOR AN ADAPTIVE FINITE IMPULSE RESPONSE AND METHOD THEREFORE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
10895552
|
Filing Dt:
|
07/21/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
HIGH K DIELECTRIC FILM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
10895553
|
Filing Dt:
|
07/21/2004
|
Publication #:
|
|
Pub Dt:
|
01/26/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH LOW RESISTANCE CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
10900719
|
Filing Dt:
|
07/27/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
LAMINATE TAPE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
10901589
|
Filing Dt:
|
07/29/2004
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
Title:
|
METHOD FOR PREPARING A SEMICONDUCTOR SUBSTRATE SURFACE FOR SEMICONDUCTOR DEVICE FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
10901844
|
Filing Dt:
|
07/29/2004
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
Title:
|
SOLDERABLE METAL FINISH FOR INTEGRATED CIRCUIT PACKAGE LEADS AND METHOD FOR FORMING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
10902021
|
Filing Dt:
|
07/30/2004
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR THE MITIGATION OF SPECTRAL LINES IN AN ULTRAWIDE BANDWIDTH TRANSCEIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2007
|
Application #:
|
10902204
|
Filing Dt:
|
07/29/2004
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
Title:
|
DYNAMIC LATCH HAVING INTEGRAL LOGIC FUNCTION AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
10902218
|
Filing Dt:
|
07/29/2004
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10903784
|
Filing Dt:
|
07/30/2004
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
Title:
|
COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR STRUCTURE HAVING ION IMPLANT IN ONLY ONE OF THE COMPLEMENTARY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2008
|
Application #:
|
10903841
|
Filing Dt:
|
07/30/2004
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
Title:
|
INTERFACIAL LAYER FOR USE WITH HIGH K DIELECTRIC MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10909124
|
Filing Dt:
|
07/30/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH STRAIN RELIEVING BUMP DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10910036
|
Filing Dt:
|
08/03/2004
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
Title:
|
METHOD FOR FORMING A BOND PAD INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
10911624
|
Filing Dt:
|
08/05/2004
|
Publication #:
|
|
Pub Dt:
|
03/17/2005
| | | | |
Title:
|
HETEROJUNCTION TUNNELING DIODES AND PROCESS FOR FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10912824
|
Filing Dt:
|
08/06/2004
|
Publication #:
|
|
Pub Dt:
|
02/09/2006
| | | | |
Title:
|
MEMORY BIT LINE SEGMENT ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10912825
|
Filing Dt:
|
08/06/2004
|
Publication #:
|
|
Pub Dt:
|
02/09/2006
| | | | |
Title:
|
METHOD OF DISCHARGING A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
10914006
|
Filing Dt:
|
08/06/2004
|
Publication #:
|
|
Pub Dt:
|
02/09/2006
| | | | |
Title:
|
TUNGSTEN COATED SILICON FINGERS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
10915439
|
Filing Dt:
|
08/11/2004
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
10916298
|
Filing Dt:
|
08/11/2004
|
Publication #:
|
|
Pub Dt:
|
02/16/2006
| | | | |
Title:
|
PREFETCHING IN A DATA PROCESSING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
10918457
|
Filing Dt:
|
08/16/2004
|
Publication #:
|
|
Pub Dt:
|
02/16/2006
| | | | |
Title:
|
METHOD FOR PROVIDING RAPID DELAYED FRAME ACKNOWLEDGEMENT IN A WIRELESS TRANSCEIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10919784
|
Filing Dt:
|
08/17/2004
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
Title:
|
SEMICONDUCTOR LAYER FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10919922
|
Filing Dt:
|
08/17/2004
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
Title:
|
TEMPLATE LAYER FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
10919952
|
Filing Dt:
|
08/17/2004
|
Publication #:
|
|
Pub Dt:
|
02/23/2006
| | | | |
Title:
|
GRADED SEMICONDUCTOR LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2005
|
Application #:
|
10924632
|
Filing Dt:
|
08/24/2004
|
Title:
|
SEMICONDUCTOR TRANSISTOR HAVING STRUCTURAL ELEMENTS OF DIFFERING MATERIALS AND METHOD OF FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2007
|
Application #:
|
10924650
|
Filing Dt:
|
08/24/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR PERFORMANCE ENHANCEMENT IN AN ASYMMETRICAL SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10925084
|
Filing Dt:
|
08/24/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
TRANSISTOR STRUCTURE WITH STRESS MODIFICATION AND CAPACITIVE REDUCTION FEATURE IN A WIDTH DIRECTION AND METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
10925108
|
Filing Dt:
|
08/24/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR MOBILITY ENHANCEMENT IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
10925855
|
Filing Dt:
|
08/25/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
RECESSED SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10926121
|
Filing Dt:
|
08/25/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
VARIABLE IMPEDANCE OUTPUT BUFFER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2006
|
Application #:
|
10927921
|
Filing Dt:
|
08/27/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
APPLICATIONS OF A HIGH IMPEDANCE SURFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2006
|
Application #:
|
10927944
|
Filing Dt:
|
08/27/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
FREQUENCY SELECTIVE HIGH IMPEDANCE SURFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10928399
|
Filing Dt:
|
08/27/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
DATA PROCESSING SYSTEM HAVING TRANSLATION LOOKASIDE BUFFER VALID BITS WITH LOCK AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10930660
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
MULTILAYER CAVITY SLOT ANTENNA
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
10930891
|
Filing Dt:
|
08/31/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
PROGRAMMING AND ERASING STRUCTURE FOR AN NVM CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
10933191
|
Filing Dt:
|
09/02/2004
|
Publication #:
|
|
Pub Dt:
|
03/02/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR MODIFYING AN INFORMATION UNIT USING AN ATOMIC OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
10939148
|
Filing Dt:
|
09/10/2004
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING CONDUCTIVE SPACERS IN SIDEWALL REGIONS AND METHOD FOR FORMING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
10940058
|
Filing Dt:
|
09/14/2004
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
Title:
|
OPEN LOOP MOTOR PARKING METHOD AND SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
10940121
|
Filing Dt:
|
09/14/2004
|
Publication #:
|
|
Pub Dt:
|
03/16/2006
| | | | |
Title:
|
System and method for fetching information in response to hazard indication information
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
10940252
|
Filing Dt:
|
09/14/2004
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR NON-INTRUSIVE TRACING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10943383
|
Filing Dt:
|
09/17/2004
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A METAL LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10943579
|
Filing Dt:
|
09/17/2004
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
MRAM SENSE AMPLIFIER HAVING A PRECHARGE CIRCUIT AND METHOD FOR SENSING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10944239
|
Filing Dt:
|
09/17/2004
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
PROGRAMMING AND ERASING STRUCTURE FOR A FLOATING GATE MEMORY CELL AND METHOD OF MAKING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10944244
|
Filing Dt:
|
09/17/2004
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
PROGRAMMING AND ERASING STRUCTURE FOR A FLOATING GATE MEMORY CELL AND METHOD OF MAKING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2007
|
Application #:
|
10944306
|
Filing Dt:
|
09/17/2004
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A GATE WITH A THIN CONDUCTIVE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
10945319
|
Filing Dt:
|
09/20/2004
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
DEPOSITION AND PATTERNING OF BORON NITRIDE NANOTUBE ILD
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10946675
|
Filing Dt:
|
09/22/2004
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING A MULTIPLE THICKNESS INTERCONNECT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2005
|
Application #:
|
10946758
|
Filing Dt:
|
09/22/2004
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING ELECTRICAL CONTACT FROM OPPOSITE SIDES INCLUDING A VIA WITH AN END FORMED AT A BOTTOM SURFACE OF THE DIFFUSION REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10946938
|
Filing Dt:
|
09/22/2004
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A DIELECTRIC LAYER WITH HIGH DIELECTRIC CONSTANT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
10946951
|
Filing Dt:
|
09/22/2004
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR PROTECTING AN INTEGRATED CIRCUIT FROM ERRONEOUS OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
10949057
|
Filing Dt:
|
09/23/2004
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
SEMICONDUCTOR PROCESS WITH FIRST TRANSISTOR TYPES ORIENTED IN A FIRST PLANE AND SECOND TRANSISTOR TYPES ORIENTED IN A SECOND PLANE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2005
|
Application #:
|
10950855
|
Filing Dt:
|
09/27/2004
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
Title:
|
NON-VOLATILE MEMORY HAVING A REFERENCE TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10952676
|
Filing Dt:
|
09/29/2004
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
Title:
|
DOUBLE GATE DEVICE HAVING A HETEROJUNCTION SOURCE/DRAIN AND STRAINED CHANNEL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
10952813
|
Filing Dt:
|
09/30/2004
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR ULTRA WIDEBAND COMMUNICATIONS USING MULTIPLE CODE WORDS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10954121
|
Filing Dt:
|
09/29/2004
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
Title:
|
METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A STRAINED CHANNEL AND A HETEROJUNCTION SOURCE/DRAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10954400
|
Filing Dt:
|
09/30/2004
|
Publication #:
|
|
Pub Dt:
|
04/06/2006
| | | | |
Title:
|
PLASMA ENHANCED NITRIDE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
10954793
|
Filing Dt:
|
09/30/2004
|
Publication #:
|
|
Pub Dt:
|
04/06/2006
| | | | |
Title:
|
APPARATUS AND METHOD FOR HIGH SPEED VOLTAGE REGULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
10954809
|
Filing Dt:
|
09/30/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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DATA PROCESSING SYSTEM WITH BUS ACCESS RETRACTION
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|
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Patent #:
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Issue Dt:
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06/05/2007
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Application #:
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10955219
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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DEVICE AND A METHOD FOR BIASING A TRANSISTOR THAT IS CONNECTED TO A POWER CONVERTER
|
|
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Patent #:
|
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Issue Dt:
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10/07/2008
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Application #:
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10955220
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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03/30/2006
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Title:
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APPARATUS AND METHOD FOR PROVIDING INFORMATION TO A CACHE MODULE USING FETCH BURSTS
|
|
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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10955356
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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04/20/2006
| | | | |
Title:
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INTEGRATED CIRCUIT FUSES HAVING CORRESPONDING STORAGE CIRCUITRY
|
|
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Patent #:
|
|
Issue Dt:
|
03/04/2008
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Application #:
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10955558
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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DATA PROCESSING SYSTEM WITH BUS ACCESS RETRACTION
|
|
|
Patent #:
|
|
Issue Dt:
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11/14/2006
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Application #:
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10955658
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Filing Dt:
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09/30/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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ISOLATION TRENCH PERIMETER IMPLANT FOR THRESHOLD VOLTAGE CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
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Application #:
|
10957254
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Filing Dt:
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10/01/2004
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Title:
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SENSOR AND METHOD OF SENSING HAVING AN ENERGY SOURCE AND DETECTOR ON THE SAME SIDE OF A SENSOR SUBSTANCE
|
|
|
Patent #:
|
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Issue Dt:
|
11/09/2010
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Application #:
|
10958039
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Filing Dt:
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10/04/2004
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Publication #:
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Pub Dt:
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03/17/2005
| | | | |
Title:
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METHOD AND APPARATUS FOR DATA ALLOCATION IN AN OVERLAP-ENABLED COMMUNICATION SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
10958831
|
Filing Dt:
|
10/05/2004
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Publication #:
|
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Pub Dt:
|
04/06/2006
| | | | |
Title:
|
WELL BIAS VOLTAGE GENERATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2006
|
Application #:
|
10961014
|
Filing Dt:
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10/08/2004
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Publication #:
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Pub Dt:
|
04/13/2006
| | | | |
Title:
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METHOD FOR FORMING A MULTI-BIT NON-VOLATILE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
10961295
|
Filing Dt:
|
10/08/2004
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Publication #:
|
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Pub Dt:
|
04/13/2006
| | | | |
Title:
|
VIRTUAL GROUND MEMORY ARRAY AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
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Application #:
|
10962944
|
Filing Dt:
|
10/12/2004
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Publication #:
|
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Pub Dt:
|
04/13/2006
| | | | |
Title:
|
INTEGRATION OF MULTIPLE GATE DIELECTRICS BY SURFACE PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
10964793
|
Filing Dt:
|
10/14/2004
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
BAND-GAP REFERENCE CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10965596
|
Filing Dt:
|
10/14/2004
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
Title:
|
SYSTEM AND METHOD FOR CACHE EXTERNAL WRITING AND WRITE SHADOWING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10965964
|
Filing Dt:
|
10/15/2004
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
LOW RC PRODUCT TRANSISTORS IN SOI SEMICONDUCTOR PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2008
|
Application #:
|
10966086
|
Filing Dt:
|
10/15/2004
|
Publication #:
|
|
Pub Dt:
|
09/08/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR DETERMINING FREQUENCY OF EXECUTION FOR COMPILED METHODS WITHIN A VIRTUAL MACHINE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
10967563
|
Filing Dt:
|
10/18/2004
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
LOGIC CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10967898
|
Filing Dt:
|
10/18/2004
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
CIRCUIT AND METHOD FOR INTERPOLATIVE DELAY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10969108
|
Filing Dt:
|
10/20/2004
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
CHANNEL ORIENTATION TO ENHANCE TRANSISTOR PERFORMANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
10969426
|
Filing Dt:
|
10/20/2004
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
TEST SYSTEM FOR DEVICE CHARACTERIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10969634
|
Filing Dt:
|
10/20/2004
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Title:
|
METHOD FOR FORMING A LAYER USING A PURGING GAS IN A SEMICONDUCTOR PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
10970098
|
Filing Dt:
|
10/20/2004
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
RADIO FREQUENCY POWER AMPLIFIER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
10971657
|
Filing Dt:
|
10/22/2004
|
Publication #:
|
|
Pub Dt:
|
04/27/2006
| | | | |
Title:
|
MANUFACTURING METHOD TO CONSTRUCT SEMICONDUCTOR-ON-INSULATOR WITH CONDUCTOR LAYER SANDWICHED BETWEEN BURIED DIELECTRIC LAYER AND SEMICONDUCTOR LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
10973728
|
Filing Dt:
|
10/26/2004
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
Title:
|
TRANSCONDUCTANCE AMPLIFIER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
10974658
|
Filing Dt:
|
10/27/2004
|
Publication #:
|
|
Pub Dt:
|
04/27/2006
| | | | |
Title:
|
THERMALLY ENHANCED MOLDED PACKAGE FOR SEMICONDUCTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
10975375
|
Filing Dt:
|
10/29/2004
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR PROVIDING A SINGLE-ENDED RECEIVE PORTION AND A DIFFERENTIAL TRANSMIT PORTION IN A WIRELESS TRANSCEIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
10977010
|
Filing Dt:
|
10/29/2004
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
Title:
|
GAIN CONTROL IN A SIGNAL PATH WITH SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
10977226
|
Filing Dt:
|
01/18/2005
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING TRENCH ISOLATION FOR DIFFERENTIAL STRESS AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
10977266
|
Filing Dt:
|
10/29/2004
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
Title:
|
TRANSISTOR STRUCTURE WITH DUAL TRENCH FOR OPTIMIZED STRESS EFFECT AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
10977423
|
Filing Dt:
|
10/29/2004
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
10977727
|
Filing Dt:
|
10/29/2004
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE HAVING A METALLIC BUFFER LAYER AND METHOD FOR FORMING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10977832
|
Filing Dt:
|
10/29/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
POWER AMPLIFIER SATURATION DETECTION AND OPERATION AT MAXIMUM POWER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
10978596
|
Filing Dt:
|
11/01/2004
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
Title:
|
BALUNS FOR MULTIPLE BAND OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
10980707
|
Filing Dt:
|
11/03/2004
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
Title:
|
PHASE MODULATING AND COMBINING CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10984438
|
Filing Dt:
|
11/09/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
ON-CHIP TEMPERATURE COMPENSATION CIRCUIT FOR AN ELECTRONIC DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
10985530
|
Filing Dt:
|
11/09/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
MICROELECTROMECHANICAL (MEM) DEVICE INCLUDING A SPRING RELEASE BRIDGE AND METHOD OF MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
10987047
|
Filing Dt:
|
11/12/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
METHOD OF FORMING A NANOCLUSTER CHARGE STORAGE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10987790
|
Filing Dt:
|
11/12/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
PLASMA TREATMENT FOR SURFACE OF SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10988963
|
Filing Dt:
|
11/15/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
METHOD OF INTEGRATING OPTICAL DEVICES AND ELECTRONIC DEVICES ON AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2007
|
Application #:
|
10989937
|
Filing Dt:
|
11/15/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
10989940
|
Filing Dt:
|
11/15/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
METHOD OF INTEGRATING OPTICAL DEVICES AND ELECTRONIC DEVICES ON AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10989947
|
Filing Dt:
|
11/15/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR DEVICE
|
|