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03/15/2005
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10720144
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11/25/2003
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07/22/2004
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03/20/2007
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10721036
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11/21/2003
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10/28/2008
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10721445
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11/24/2003
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05/26/2005
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02/27/2007
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10723574
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11/26/2003
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02/03/2005
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11/28/2006
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10724036
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12/01/2003
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06/17/2004
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05/20/2008
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10725008
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12/02/2003
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09/02/2004
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Title:
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METHOD OF AND SYSTEM FOR PERFORMING DIFFERENTIAL LOSSLESS COMPRESSION
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NONE
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10725771
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12/02/2003
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05/05/2005
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Reduction of memory requirements by overlaying buffers
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12/13/2011
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10725974
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12/02/2003
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05/05/2005
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VIDEO DISPLAY AND DECODE UTILIZING OFF-CHIP PROCESSOR AND DRAM
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11/07/2006
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10726180
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12/02/2003
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05/05/2005
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NONE
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10726342
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12/03/2003
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09/23/2004
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Title:
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Free pointer pool implementation
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12/14/2010
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10726814
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12/03/2003
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06/17/2004
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PROCESSING HIGH DEFINITION VIDEO DATA
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02/06/2007
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10727378
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12/04/2003
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06/17/2004
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Title:
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NONE
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10727379
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12/04/2003
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06/17/2004
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Title:
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Method of manufacture an on-chip inductor having a square geometry and high Q factor
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08/15/2006
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10727380
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12/04/2003
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06/09/2005
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Title:
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LOW LOSS DIVERSITY ANTENNA T/R SWITCH
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08/08/2006
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10727422
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12/04/2003
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06/10/2004
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ON-CHIP MULTIPLE TAP TRANSFORMER AND INDUCTOR
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09/08/2009
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10727430
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12/04/2003
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07/22/2004
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DATA PATH SECURITY PROCESSING
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08/15/2006
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10727431
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12/04/2003
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06/10/2004
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ON-CHIP DIFFERENTIAL MULTI-LAYER INDUCTOR
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04/21/2015
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10728192
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12/04/2003
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07/15/2004
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TAGGING MECHANISM FOR DATA PATH SECURITY PROCESSING
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11/16/2004
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10728201
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12/04/2003
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04/29/2004
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APPLICATIONS OF A DIFFERENTIAL LATCH
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10/02/2007
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10729275
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12/05/2003
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06/17/2004
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MANAGING MULTI-COMPONENT DATA
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02/13/2007
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10729405
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12/05/2003
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06/24/2004
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BLOCK REDUNDANCY IMPLEMENTATION IN HEIRARCHICAL RAM'S
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09/01/2009
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10729443
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12/05/2003
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06/17/2004
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MANAGING BURSTS OF DATA
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05/03/2005
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10730093
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12/09/2003
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06/17/2004
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Title:
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METHOD FOR MAKING AN ENHANCED DIE-UP BALL GRID ARRAY PACKAGE WITH TWO SUBSTRATES
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06/15/2010
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10730405
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12/08/2003
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06/17/2004
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PROCESSING DATA STREAMS
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08/09/2005
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10731078
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12/09/2003
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06/24/2004
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DYNAMIC REGISTER WITH LOW CLOCK RATE TESTING CAPABILITY
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07/12/2005
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10731667
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12/09/2003
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06/24/2004
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ANALOG TO DIGITAL CONVERTER THAT SERVICES VOICE COMMUNICATIONS
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01/16/2007
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10731803
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12/09/2003
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06/24/2004
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09/18/2007
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10731804
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12/09/2003
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06/24/2004
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EDGE INCREMENTAL REDUNDANCY MEMORY STRUCTURE AND MEMORY MANAGEMENT
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04/11/2006
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10731858
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12/09/2003
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06/24/2004
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PIPELINE ARCHITECTURE FOR MULTI-SLOT WIRELESS LINK PROCESSING
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07/18/2006
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10733823
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12/11/2003
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06/24/2004
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FORWARD ERROR CORRECTOR
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08/23/2011
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10733856
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12/11/2003
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09/23/2004
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SYNCHRONIZATION OF MULTIPLE PROCESSORS IN A MULTI-MODE WIRELESS COMMUNICATION DEVICE
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04/16/2013
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10733861
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12/11/2003
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09/09/2004
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Multi-processor platform for wireless communication terminal having partitioned protocol stack
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09/13/2005
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10734464
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12/12/2003
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CONTENT ADDRESSABLE MEMORY WITH MODE-SELECTABLE MATCH DETECT TIMING
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07/05/2005
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10734666
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12/12/2003
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CONTENT ADDRESSABLE MEMORY WITH SELECTIVE ERROR LOGGING
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06/19/2007
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10735107
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12/12/2003
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METHOD AND APPARATUS FOR IMPLEMENTING A SEARCH ENGINE USING AN SRAM
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10/16/2007
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10735980
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12/15/2003
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02/17/2005
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DMA ENGINE FOR FETCHING WORDS IN REVERSE ORDER
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10/21/2008
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10736068
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12/15/2003
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07/01/2004
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HIERARCHICAL COMMUNICATION SYSTEM PROVIDING INTELLIGENT DATA, PROGRAM AND PROCESSING MIGRATION
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NONE
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10736125
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12/15/2003
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02/17/2005
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DMA engine for fetching words in reverse bit order
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01/13/2009
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10736349
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12/15/2003
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07/15/2004
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ECHO CANCELLATION FOR A PACKET VOICE SYSTEM
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07/06/2010
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10736434
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12/15/2003
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08/19/2004
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COMMUNICATIONS SIGNAL TRANSCODER
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09/26/2006
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10736681
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12/17/2003
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06/23/2005
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SYSTEM FOR ESD PROTECTION WITH EXTRA HEADROOM IN RELATIVELY LOW SUPPLY VOLTAGE INTEGRATED CIRCUITS
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09/26/2006
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10736819
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12/15/2003
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06/16/2005
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ROADWAY TRAVEL DATA EXCHANGE NETWORK
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03/13/2007
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10737358
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12/16/2003
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01/13/2005
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Title:
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SCHMOO RUNTIME REDUCTION AND DYNAMIC CALIBRATION BASED ON A DLL LOCK VALUE
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Patent #:
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NONE
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10737492
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12/16/2003
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06/16/2005
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Title:
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Dual context audio parser
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01/17/2006
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10738264
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12/17/2003
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Title:
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CONTENT ADDRESSABLE MEMORY (CAM) DEVICES HAVING MULTI-BLOCK ERROR DETECTION LOGIC AND ENTRY SELECTIVE ERROR CORRECTION LOGIC THEREIN
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06/07/2005
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10739246
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12/17/2003
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Pub Dt:
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06/03/2004
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Title:
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CONTENT ADDRESSABLE MEMORY WITH CASCADED ARRAY
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08/21/2007
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10739874
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12/17/2003
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Title:
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TECHNIQUE FOR DEALLOCATION OF MEMORY IN A MULTICASTING ENVIRONMENT
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06/12/2007
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10740085
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12/17/2003
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Pub Dt:
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06/23/2005
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Title:
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PRIORITIZATION OF REAL TIME / NON-REAL TIME MEMORY REQUESTS FROM BUS COMPLIANT DEVICES
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03/21/2006
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10740641
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12/22/2003
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08/26/2004
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APPARATUS AND METHOD FOR OPTIMIZING ACCESS TO MEMORY
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09/06/2005
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10740814
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12/22/2003
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07/08/2004
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METHODS AND SYSTEMS FOR GENERATING INTERIM VOLTAGE SUPPLIES
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06/30/2009
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10741665
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12/19/2003
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Pub Dt:
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06/23/2005
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RF TRANSMITTER HAVING MULTIPLE CONSTANT TRANSMIT POWER LEVELS
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08/29/2006
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10741852
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12/19/2003
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Pub Dt:
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06/23/2005
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RADIO FREQUENCY INTEGRATED CIRCUIT LAYOUT WITH NOISE IMMUNITY BORDER
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02/10/2009
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10742060
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12/20/2003
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07/08/2004
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HYPERTRANSPORT/SPI-4 INTERFACE SUPPORTING CONFIGURABLE DESKEWING
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12/04/2007
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10742374
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12/19/2003
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06/23/2005
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RADIO FREQUENCY INTEGRATED CIRCUIT HAVING REDUCED RECEIVER NOISE LEVELS
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08/22/2006
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10742489
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12/19/2003
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06/23/2005
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Title:
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PHASE LOCKED LOOP CALIBRATION
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Patent #:
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06/24/2008
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10742496
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12/19/2003
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Pub Dt:
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06/23/2005
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Title:
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HIGH FREQUENCY INTEGRATED CIRCUIT PAD CONFIGURATION INCLUDING ESD PROTECTION CIRCUITRY
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Issue Dt:
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10/04/2005
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Application #:
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10742942
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Filing Dt:
|
12/23/2003
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Publication #:
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Pub Dt:
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07/15/2004
| | | | |
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Title:
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PROTECTION CIRCUIT FOR EXTENDING HEADROOM WITH OFF-CHIP INDUCTORS
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Patent #:
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Issue Dt:
|
02/27/2007
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Application #:
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10743597
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Filing Dt:
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12/22/2003
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Title:
|
CAM-BASED SEARCH ENGINE DEVICES HAVING INDEX TRANSLATION CAPABILITY
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Patent #:
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Issue Dt:
|
11/01/2005
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Application #:
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10743962
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Filing Dt:
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12/22/2003
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Publication #:
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Pub Dt:
|
07/15/2004
| | | | |
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Title:
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SYNCHRONOUS CONTENT ADDRESSABLE MEMORY
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10744488
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Filing Dt:
|
12/23/2003
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|
Publication #:
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Pub Dt:
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06/23/2005
| | | | |
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Title:
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Method and system for a communication device having a single button photo send
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10744517
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Filing Dt:
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12/23/2003
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Publication #:
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Pub Dt:
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01/20/2005
| | | | |
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Title:
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Two-bit branch prediction scheme using reduced memory size
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Patent #:
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Issue Dt:
|
03/02/2010
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Application #:
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10744527
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Filing Dt:
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12/23/2003
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Publication #:
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Pub Dt:
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02/24/2005
| | | | |
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Title:
|
PHY CONTROL MODULE FOR A MULTI-PAIR GIGABIT TRANSCEIVER
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Patent #:
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Issue Dt:
|
05/20/2008
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Application #:
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10744531
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Filing Dt:
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12/22/2003
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Publication #:
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Pub Dt:
|
07/15/2004
| | | | |
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Title:
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VIDEO ENCODING AND VIDEO/AUDIO/DATA MULTIPLEXING DEVICE
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Patent #:
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Issue Dt:
|
08/29/2006
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Application #:
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10744785
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Filing Dt:
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12/24/2003
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Publication #:
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Pub Dt:
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06/30/2005
| | | | |
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Title:
|
FINE STEP AND LARGE GAIN RANGE PROGRAMMABLE GAIN AMPLIFIER
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|
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|
Patent #:
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|
Issue Dt:
|
09/19/2006
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Application #:
|
10744892
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Filing Dt:
|
12/23/2003
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Publication #:
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Pub Dt:
|
01/20/2005
| | | | |
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Title:
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SYSTEM FOR SUPPORTING UNLIMITED CONSECUTIVE DATA STORES INTO A CACHE MEMORY
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|
Patent #:
|
NONE
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Issue Dt:
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Application #:
|
10745155
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Filing Dt:
|
12/23/2003
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|
Publication #:
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Pub Dt:
|
07/22/2004
| | | | |
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Title:
|
Mechanism to maintain data coherency for a read-ahead cache
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|
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Patent #:
|
|
Issue Dt:
|
12/07/2004
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Application #:
|
10745688
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Filing Dt:
|
12/29/2003
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|
Publication #:
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Pub Dt:
|
07/15/2004
| | | | |
|
Title:
|
METHOD AND CIRCUIT FOR A DUAL SUPPLY AMPLIFIER
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/25/2005
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Application #:
|
10746899
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Filing Dt:
|
12/24/2003
|
|
Title:
|
STAGGERED COMPARE ARCHITECTURE FOR CONTENT ADDRESSABLE MEMORY (CAM) DEVICE
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|
|
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Patent #:
|
|
Issue Dt:
|
07/11/2006
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Application #:
|
10747124
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Filing Dt:
|
12/30/2003
|
|
Publication #:
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Pub Dt:
|
11/04/2004
| | | | |
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Title:
|
VARIABLE GAIN AMPLIFIER FOR LOW VOLTAGE APPLICATIONS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
04/15/2008
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Application #:
|
10747276
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Filing Dt:
|
12/30/2003
|
|
Publication #:
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|
Pub Dt:
|
06/30/2005
| | | | |
|
Title:
|
SIMULTANEOUS SWITCH TEST MODE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/15/2005
|
Application #:
|
10747310
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Filing Dt:
|
12/30/2003
|
|
Publication #:
|
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Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
VOLTAGE MODE DIFFERENTIAL DRIVER AND METHOD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
10747931
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Filing Dt:
|
12/30/2003
|
|
Publication #:
|
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Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
MULTI-MODE VARIABLE RATE DIGITAL SATELLITE RECEIVER
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|
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
10748223
|
Filing Dt:
|
12/31/2003
|
|
Publication #:
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Pub Dt:
|
06/30/2005
| | | | |
|
Title:
|
System and method for controlling packet transmission using a plurality of buckets
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2004
|
Application #:
|
10748250
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Filing Dt:
|
12/31/2003
|
|
Publication #:
|
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Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
ANALOG TO DIGITAL CONVERTER WITH INTERPOLATION OF REFERENCE LADDER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2009
|
Application #:
|
10748290
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Filing Dt:
|
12/31/2003
|
|
Publication #:
|
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Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR COMMUNICATING ARBITRARILY ENCODED DATA OVER A 1-GIGABIT ETHERNET
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
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Application #:
|
10748551
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Filing Dt:
|
12/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
DIRECT ACCESS MODE FOR A CACHE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2005
|
Application #:
|
10748564
|
Filing Dt:
|
12/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
INTERNAL EVICT WITH EXTERNAL REQUEST
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10748639
|
Filing Dt:
|
12/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/12/2004
| | | | |
|
Title:
|
DYNAMIC TO STATIC CONVERTER WITH NOISE SUPPRESSION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
10749492
|
Filing Dt:
|
12/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/16/2004
| | | | |
|
Title:
|
SYSTEM AND METHOD TO EXTRACT UPLINK STATUS FLAG BITS IN A CELLULAR WIRELESS NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
10749661
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Filing Dt:
|
12/31/2003
|
|
Publication #:
|
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Pub Dt:
|
12/16/2004
| | | | |
|
Title:
|
SYSTEM AND METHOD TO CONDUCT IDLE MODE PAGING CHANNEL MONITORING WITHIN A CELLULAR WIRELESS NETWORK
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
10749799
|
Filing Dt:
|
12/30/2003
|
|
Title:
|
DIGITAL UNDERSAMPLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10749965
|
Filing Dt:
|
12/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/12/2004
| | | | |
|
Title:
|
METHODS AND CIRCUITRY FOR IMPLEMENTING FIRST-IN FIRST-OUT STRUCTURE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2005
|
Application #:
|
10750098
|
Filing Dt:
|
12/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/12/2004
| | | | |
|
Title:
|
METHODS AND CIRCUITRY FOR IMPLEMENTING FIRST-IN FIRST-OUT STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
10750523
|
Filing Dt:
|
12/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
01/20/2005
| | | | |
|
Title:
|
MINI-TRANSLATION LOOKASIDE BUFFER FOR USE IN MEMORY TRANSLATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
10750834
|
Filing Dt:
|
01/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/09/2004
| | | | |
|
Title:
|
HIGH DENSITY METAL CAPACITOR USING VIA ETCH STOPPING LAYER AS FIELD DIELECTRIC IN DUAL-DAMASCENCE INTERCONNECT PROCESS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2005
|
Application #:
|
10750835
|
Filing Dt:
|
01/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/18/2004
| | | | |
|
Title:
|
HACKER-PROOF ONE TIME PROGRAMMABLE MEMORY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
10750960
|
Filing Dt:
|
01/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/15/2004
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR HIGH SPEED TABLE SEARCH
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10750961
|
Filing Dt:
|
01/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
System and method for self-adaptive redundancy choice logic
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|
|
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|
Patent #:
|
|
Issue Dt:
|
01/03/2006
|
Application #:
|
10751148
|
Filing Dt:
|
01/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/22/2004
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR ITERATIVE DECODING
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|
|
|
|
Patent #:
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|
Issue Dt:
|
06/19/2007
|
Application #:
|
10751508
|
Filing Dt:
|
01/06/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/07/2005
| | | | |
|
Title:
|
CIRCUIT OUTPUT STAGE PROTECTION SYSTEM
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/14/2012
|
Application #:
|
10751732
|
Filing Dt:
|
01/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR HANDLING TRANSPORT PROTOCOL SEGMENTS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2010
|
Application #:
|
10752191
|
Filing Dt:
|
01/06/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
|
Title:
|
ADAPTIVE RADIO TRANSCEIVER WITH A POWER AMPLIFIER
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|
|
|
|
Patent #:
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|
Issue Dt:
|
01/04/2011
|
Application #:
|
10752336
|
Filing Dt:
|
01/06/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/07/2005
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR TRANSMISSION CONTROL PACKET (TCP) SEGMENTATION OFFLOAD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
10752456
|
Filing Dt:
|
01/06/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
|
Title:
|
ADAPTIVE RADIO TRANSCEIVER WITH A POWER AMPLIFIER
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/05/2005
|
Application #:
|
10752581
|
Filing Dt:
|
01/08/2004
|
|
Publication #:
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|
Pub Dt:
|
07/22/2004
| | | | |
|
Title:
|
HIGH LINEARITY LARGE BANDWIDTH, SWITCH INSENSITIVE, PROGRAMMABLE GAIN ATTENUATOR
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
10752633
|
Filing Dt:
|
01/07/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/22/2004
| | | | |
|
Title:
|
DETERMINATION OF TRANSMITTER DISTORTION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10752889
|
Filing Dt:
|
01/07/2004
|
|
Title:
|
CONTENT ADDRESSABLE MEMORY WITH SIMULTANEOUS WRITE AND COMPARE FUNCTION
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|
|
|
|
Patent #:
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|
Issue Dt:
|
10/18/2005
|
Application #:
|
10753194
|
Filing Dt:
|
01/08/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/06/2005
| | | | |
|
Title:
|
MOSFET WELL BIASING SCHEME THAT MITIGATES BODY EFFECT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
10753560
|
Filing Dt:
|
01/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/14/2005
| | | | |
|
Title:
|
SATURATED DATAGRAM AGING MECHANISM
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10753964
|
Filing Dt:
|
01/08/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/23/2004
| | | | |
|
Title:
|
Transporting home networking frame-based communication signals over coaxial cables
|
|
