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05/29/2007
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11100617
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04/07/2005
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Publication #:
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Pub Dt:
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10/13/2005
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Title:
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05/08/2007
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11101972
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04/08/2005
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08/10/2006
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Title:
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01/23/2007
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11101974
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04/08/2005
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10/12/2006
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PHASE CHANGE MEMORY CELL DEFINED BY A PATTERN SHRINK MATERIAL PROCESS
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02/27/2007
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11102071
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04/08/2005
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11/03/2005
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Title:
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03/25/2008
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11102350
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04/08/2005
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Pub Dt:
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08/10/2006
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Title:
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PHASE CHANGE MEMORY CELL WITH HIGH READ MARGIN AT LOW POWER OPERATION
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08/14/2007
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11103244
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04/11/2005
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10/12/2006
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Title:
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METHOD OF MANUFACTURING A MEMORY DEVICE
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03/13/2007
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11105580
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04/14/2005
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10/19/2006
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Title:
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02/17/2009
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11106719
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04/15/2005
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10/27/2005
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Title:
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12/11/2007
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11107182
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04/15/2005
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11/03/2005
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03/17/2009
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11107750
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04/18/2005
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10/19/2006
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SEMICONDUCTOR DEVICE AND MASK PATTERN
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08/12/2008
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11108154
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04/15/2005
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11/10/2005
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Title:
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TRENCH AND A TRENCH CAPACITOR AND METHOD FOR FORMING THE SAME
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05/29/2007
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11108179
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04/18/2005
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10/19/2006
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REDUNDANCY CIRCUITS FOR SEMICONDUCTOR MEMORY
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09/12/2006
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11109583
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04/19/2005
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11/03/2005
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MEMORY CIRCUIT AND METHOD FOR PROVIDING AN ITEM OF INFORMATION FOR A PRESCRIBED PERIOD OF TIME
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12/23/2008
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11111140
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04/21/2005
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10/26/2006
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01/08/2008
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11112743
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04/22/2005
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11/10/2005
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12/11/2007
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11112748
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04/22/2005
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10/27/2005
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METHOD FOR THE FORMATION OF A STRUCTURE SIZE MEASURED VALUE
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11/25/2008
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11112940
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04/22/2005
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11/03/2005
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STACKED CAPACITOR ARRAY AND FABRICATION METHOD FOR A STACKED CAPACITOR ARRAY
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10/23/2007
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11114566
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04/25/2005
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10/26/2006
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CLOSING DISK FOR IMMERSION HEAD
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12/25/2007
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11115391
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04/27/2005
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11/02/2006
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MANUFACTURING METHOD FOR A TRENCH CAPACITOR HAVING AN ISOLATION COLLAR ELECTRICALLY CONNECTED WITH A SUBSTRATE ON A SINGLE SIDE VIA A BURIED CONTACT FOR USE IN A SEMICONDUCTOR MEMORY CELL
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09/18/2007
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11116197
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04/28/2005
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11/10/2005
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METHOD FOR TESTING A MEMORY CHIP AND TEST ARRANGEMENT
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10/23/2007
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11116439
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04/28/2005
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11/02/2006
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EXPOSING A SEMICONDUCTOR WAFER USING TWO DIFFERENT SPECTRAL WAVELENGTHS AND ADJUSTING FOR CHROMATIC ABERRATION
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04/17/2007
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11116456
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04/28/2005
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11/02/2006
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METHODS AND APPARATUS FOR IMPLEMENTING STANDBY MODE IN A RANDOM ACCESS MEMORY
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12/11/2007
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11116875
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04/28/2005
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11/02/2006
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VOLTAGE MONITORING TEST MODE AND TEST ADAPTER
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05/29/2007
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11117698
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04/29/2005
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11/17/2005
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METHOD AND CIRCUIT ARRANGEMENT FOR CONTROLLING WRITE ACCESS TO A SEMICONDUCTOR MEMORY
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11/06/2007
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11117712
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04/29/2005
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11/03/2005
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METHOD FOR PRODUCTION OF TRENCH DRAM CELLS AND A TRENCH DRAM CELL ARRAY WITH FIN FIELD-EFFECT TRANSISTORS WITH A CURVED CHANNEL (CFET - CURVED FETS)
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04/22/2008
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11117736
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04/29/2005
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11/17/2005
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METHOD AND CIRCUIT ARRANGEMENT FOR RESETTING AN INTEGRATED CIRCUIT
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01/22/2008
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11117853
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04/29/2005
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11/17/2005
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DRAM MEMORY CELL ARRANGEMENT
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10/13/2009
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11117854
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04/29/2005
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11/02/2006
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MEMORY HAVING CAP STRUCTURE FOR MAGNETORESISTIVE JUNCTION AND METHOD FOR STRUCTURING THE SAME
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01/02/2007
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11117855
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04/29/2005
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11/02/2006
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06/05/2007
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11118036
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04/29/2005
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11/02/2006
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SENSE AMPLIFIER FOR ELIMINATING LEAKAGE CURRENT DUE TO BIT LINE SHORTS
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03/06/2007
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11118037
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04/29/2005
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11/02/2006
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MEMORY HAVING POWER-UP CIRCUIT
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11/06/2007
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11118374
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05/02/2005
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11/02/2006
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DISTRIBUTION OF SIGNALS THROUGHOUT A SPINE OF AN INTEGRATED CIRCUIT
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01/06/2009
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11118768
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05/02/2005
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11/02/2006
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MEMORY CELL ARRAY AND METHOD OF MANUFACTURING THE SAME
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09/23/2008
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11119029
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04/29/2005
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TARGETS FOR MEASUREMENTS IN SEMICONDUCTOR DEVICES
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12/30/2008
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11119320
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04/29/2005
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METHOD FOR REDUCING LITHOGRAPHY PATTERN DEFECTS
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09/18/2007
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11119376
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04/29/2005
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11/02/2006
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MULTI-BIT VIRTUAL-GROUND NAND MEMORY DEVICE
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08/05/2008
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11120007
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05/02/2005
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11/02/2006
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MEMORY DEVICE
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01/30/2007
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11121171
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05/04/2005
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11/09/2006
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INTEGRATED SEMICONDUCTOR MEMORY DEVICE FOR SYNCHRONIZING A SIGNAL WITH A CLOCK SIGNAL
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01/02/2007
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11121175
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05/04/2005
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11/10/2005
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METHOD FOR TESTING AN INTEGRATED SEMICONDUCTOR MEMORY
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10/09/2007
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11122016
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05/05/2005
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11/09/2006
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04/17/2007
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11123221
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05/06/2005
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11/10/2005
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INTEGRATED SEMICONDUCTOR MEMORY
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03/27/2007
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11123226
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05/06/2005
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11/10/2005
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INTEGRATED CIRCUIT FOR STABILIZING A VOLTAGE
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10/26/2010
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11124515
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05/06/2005
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09/22/2005
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METHOD OF PRODUCING AN ELECTRONIC COMPONENT WITH FLEXIBLE BONDING PADS
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12/04/2007
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11125654
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05/10/2005
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11/24/2005
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METHOD FOR FABRICATING DIELECTRIC MIXED LAYERS AND CAPACITIVE ELEMENT AND USE THEREOF
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04/24/2007
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11126392
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05/11/2005
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11/16/2006
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METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING STACKED CHIPS AND A CORRESPONDING SEMICONDUCTOR DEVICE
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10/27/2009
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05/11/2005
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11/16/2006
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TECHNIQUE TO READ SPECIAL MODE REGISTER
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03/06/2007
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11127022
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05/11/2005
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11/16/2006
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12/04/2007
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11127304
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05/12/2005
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12/08/2005
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12/25/2007
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11127505
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05/12/2005
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01/05/2006
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FABRICATION METHOD FOR A SEMICONDUCTOR STRUCTURE HAVING INTEGRATED CAPACITORS
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05/22/2007
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11127536
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05/12/2005
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12/08/2005
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BACKWARDS-COMPATIBLE MEMORY MODULE
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07/01/2008
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11127782
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05/12/2005
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12/01/2005
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SEMICONDUCTOR CHIP WITH METALLIZATION LEVELS, AND A METHOD FOR FORMATION OF INTERCONNECT STRUCTURES
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10/28/2008
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11128431
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05/13/2005
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11/16/2006
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METHOD FOR EXPOSING A SEMICONDUCTOR WAFER BY APPLYING PERIODIC MOVEMENT TO A COMPONENT
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01/29/2008
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11128625
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05/13/2005
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12/08/2005
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12/22/2009
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11128782
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05/13/2005
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Pub Dt:
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12/29/2005
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Title:
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TRANSISTOR, MEMORY CELL ARRAY AND METHOD OF MANUFACTURING A TRANSISTOR
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Patent #:
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Issue Dt:
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06/03/2008
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Application #:
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11130412
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Filing Dt:
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05/17/2005
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Publication #:
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Pub Dt:
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11/23/2006
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Title:
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METHOD FOR SETTING A SECOND RANK ADDRESS FROM A FIRST RANK ADDRESS IN A MEMORY MODULE
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Patent #:
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Issue Dt:
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02/27/2007
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Application #:
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11131356
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Filing Dt:
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05/18/2005
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Publication #:
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Pub Dt:
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11/23/2006
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Title:
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LITHOGRAPHY METHOD AND SYSTEM WITH CORRECTION OF OVERLAY OFFSET ERRORS CAUSED BY WAFER PROCESSING
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Patent #:
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Issue Dt:
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06/10/2008
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Application #:
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11131938
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Filing Dt:
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05/17/2005
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Publication #:
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Pub Dt:
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12/29/2005
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Title:
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TRANSISTOR ARRANGEMENT IN MONOCRYSTALLINE SUBSTRATE HAVING STRESS EXERTING INSULATORS
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Patent #:
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Issue Dt:
|
10/24/2006
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Application #:
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11131957
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Filing Dt:
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05/18/2005
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Title:
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SYSTEM AND METHOD TO PREDICT THE STATE OF A PROCESS CONTROLLER IN A SEMICONDUCTOR MANUFACTURING FACILITY
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Patent #:
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Issue Dt:
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12/04/2007
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Application #:
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11132419
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Filing Dt:
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05/19/2005
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Publication #:
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Pub Dt:
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11/10/2005
| | | | |
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Title:
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MEMORY SYSTEM FOR NETWORK BROADCASTING APPLICATIONS AND METHOD FOR OPERATING THE SAME
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Patent #:
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Issue Dt:
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05/13/2008
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Application #:
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11132562
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Filing Dt:
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05/19/2005
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Publication #:
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Pub Dt:
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12/14/2006
| | | | |
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Title:
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ECC FLAG FOR TESTING ON-CHIP ERROR CORRECTION CIRCUIT
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Patent #:
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Issue Dt:
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09/04/2007
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Application #:
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11133038
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Filing Dt:
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05/19/2005
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Publication #:
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Pub Dt:
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08/03/2006
| | | | |
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Title:
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METHOD FOR ACTIVATING AND DEACTIVATING ELECTRONIC CIRCUIT UNITS AND CIRCUIT ARRANGEMENT FOR CARRYING OUT THE METHOD
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Patent #:
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Issue Dt:
|
07/05/2011
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Application #:
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11133491
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Filing Dt:
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05/20/2005
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Publication #:
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Pub Dt:
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11/23/2006
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Title:
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LOW POWER PHASE CHANGE MEMORY CELL WITH LARGE READ SIGNAL
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Patent #:
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Issue Dt:
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02/05/2008
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Application #:
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11134512
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Filing Dt:
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05/23/2005
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Publication #:
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Pub Dt:
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11/24/2005
| | | | |
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Title:
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THIN FILM FIELD EFFECT TRANSISTOR WITH GATE DIELECTRIC MADE OF ORGANIC MATERIAL AND METHOD FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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02/26/2008
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Application #:
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11135002
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Filing Dt:
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05/23/2005
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
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Title:
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SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PRODUCTION
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Patent #:
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Issue Dt:
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05/15/2007
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Application #:
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11135212
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Filing Dt:
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05/23/2005
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Publication #:
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Pub Dt:
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12/08/2005
| | | | |
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Title:
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MEMORY CIRCUIT, AND METHOD FOR READING OUT DATA CONTAINED IN THE MEMORY CIRCUIT USING SHARED COMMAND SIGNALS
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Patent #:
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Issue Dt:
|
06/16/2009
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Application #:
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11135611
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Filing Dt:
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05/23/2005
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
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Title:
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METHOD AND APPARATUS FOR ADAPTING CIRCUIT COMPONENTS OF A MEMORY MODULE TO CHANGING OPERATING CONDITIONS
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Patent #:
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Issue Dt:
|
09/25/2007
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Application #:
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11135642
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Filing Dt:
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05/24/2005
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Publication #:
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Pub Dt:
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12/22/2005
| | | | |
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Title:
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INTEGRATED CIRCUIT
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Patent #:
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|
Issue Dt:
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07/22/2008
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Application #:
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11136712
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Filing Dt:
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05/25/2005
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Publication #:
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Pub Dt:
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12/08/2005
| | | | |
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Title:
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READ LATENCY CONTROL CIRCUIT
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Patent #:
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Issue Dt:
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07/25/2006
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Application #:
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11137061
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Filing Dt:
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05/25/2005
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Publication #:
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Pub Dt:
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12/22/2005
| | | | |
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Title:
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FLEXIBLE CONTACT-CONNECTION DEVICE
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Patent #:
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Issue Dt:
|
01/22/2008
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Application #:
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11137062
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Filing Dt:
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05/25/2005
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Publication #:
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Pub Dt:
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12/22/2005
| | | | |
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Title:
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ELECTRONIC CIRCUIT APPARATUS AND METHOD FOR STACKING ELECTRONIC CIRCUIT UNITS
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Patent #:
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Issue Dt:
|
03/06/2007
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Application #:
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11137736
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Filing Dt:
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05/25/2005
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Publication #:
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Pub Dt:
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11/30/2006
| | | | |
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Title:
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INTEGRATED CIRCUIT CHIP HAVING A FIRST DELAY CIRCUIT TRIMMED VIA A SECOND DELAY CIRCUIT
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Patent #:
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Issue Dt:
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09/25/2007
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Application #:
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11137783
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Filing Dt:
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05/25/2005
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Publication #:
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Pub Dt:
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11/30/2006
| | | | |
|
Title:
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REDISTRIBUTION LAYER WITH MICROSTRIPS
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Patent #:
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Issue Dt:
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05/26/2009
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Application #:
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11138462
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Filing Dt:
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05/27/2005
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Publication #:
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Pub Dt:
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12/14/2006
| | | | |
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Title:
|
TEST MODE FOR PROGRAMMING RATE AND PRECHARGE TIME FOR DRAM ACTIVATE-PRECHARGE CYCLE
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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11138643
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Filing Dt:
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05/27/2005
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Publication #:
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Pub Dt:
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11/30/2006
| | | | |
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Title:
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MRAM CELL WITH SPLIT CONDUCTIVE LINES
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Patent #:
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Issue Dt:
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05/29/2007
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Application #:
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11138671
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Filing Dt:
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05/27/2005
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Publication #:
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Pub Dt:
|
11/30/2006
| | | | |
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Title:
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INTEGRATED CIRCUIT
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/23/2008
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Application #:
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11139975
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Filing Dt:
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05/31/2005
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Publication #:
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Pub Dt:
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11/30/2006
| | | | |
|
Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
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|
|
|
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Patent #:
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|
Issue Dt:
|
01/17/2012
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Application #:
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11139976
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Filing Dt:
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05/31/2005
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Publication #:
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Pub Dt:
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11/30/2006
| | | | |
|
Title:
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SEMICONDUCTOR MEMORY DEVICE
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/24/2007
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Application #:
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11140143
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Filing Dt:
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05/27/2005
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Publication #:
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Pub Dt:
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11/30/2006
| | | | |
|
Title:
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METHOD OF FORMING A MEMORY CELL ARRAY AND A MEMORY CELL ARRAY
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|
|
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Patent #:
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|
Issue Dt:
|
02/20/2007
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Application #:
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11140554
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Filing Dt:
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05/27/2005
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Publication #:
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Pub Dt:
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12/22/2005
| | | | |
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Title:
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INTEGRATED SEMICONDUCTOR MEMORY COMPRISING AT LEAST ONE WORD LINE AND COMPRISING A MULTIPLICITY OF MEMORY CELLS
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|
|
|
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Patent #:
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|
Issue Dt:
|
09/25/2007
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Application #:
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11141255
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Filing Dt:
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05/31/2005
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Publication #:
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Pub Dt:
|
11/30/2006
| | | | |
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Title:
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METHOD OF PROGRAMMING OF A NON-VOLATILE MEMORY CELL COMPRISING STEPS OF APPLYING CONSTANT VOLTAGE AND THEN CONSTANT CURRENT
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|
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Patent #:
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|
Issue Dt:
|
10/02/2007
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Application #:
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11142023
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Filing Dt:
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06/01/2005
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Publication #:
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Pub Dt:
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12/07/2006
| | | | |
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Title:
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IMPLEMENTATION OF A FUSING SCHEME TO ALLOW INTERNAL VOLTAGE TRIMMING
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Patent #:
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Issue Dt:
|
03/27/2007
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Application #:
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11144791
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Filing Dt:
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06/06/2005
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Publication #:
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Pub Dt:
|
12/07/2006
| | | | |
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Title:
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SENSING CURRENT RECYCLING METHOD DURING SELF-REFRESH
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Patent #:
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Issue Dt:
|
02/26/2008
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Application #:
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11145183
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Filing Dt:
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06/06/2005
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Publication #:
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Pub Dt:
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01/04/2007
| | | | |
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Title:
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METHOD OF FORMING MAGNETORESISTIVE JUNCTIONS IN MANUFACTURING MRAM CELLS
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Patent #:
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Issue Dt:
|
12/25/2007
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Application #:
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11145192
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Filing Dt:
|
06/06/2005
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Publication #:
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Pub Dt:
|
12/29/2005
| | | | |
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Title:
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INTEGRATED SEMICONDUCTOR MEMORY
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/13/2008
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Application #:
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11145256
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Filing Dt:
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06/03/2005
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Publication #:
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Pub Dt:
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12/22/2005
| | | | |
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Title:
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MEMORY CIRCUIT COMPRISING REDUNDANT MEMORY AREAS
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|
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Patent #:
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Issue Dt:
|
08/21/2007
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Application #:
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11145520
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Filing Dt:
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06/03/2005
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Publication #:
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Pub Dt:
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12/07/2006
| | | | |
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Title:
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REFERENCE SCHEME FOR A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
|
02/27/2007
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Application #:
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11145541
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Filing Dt:
|
06/03/2005
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Publication #:
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Pub Dt:
|
12/29/2005
| | | | |
|
Title:
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SEMICONDUCTOR MEMORY HAVING CHARGE TRAPPING MEMORY CELLS AND FABRICATION METHOD
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/13/2007
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Application #:
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11145551
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Filing Dt:
|
06/03/2005
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|
Publication #:
|
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Pub Dt:
|
12/07/2006
| | | | |
|
Title:
|
SENSING SCHEME FOR A NON-VOLATILE SEMICONDUCTOR MEMORY CELL
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/02/2007
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Application #:
|
11145610
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Filing Dt:
|
06/06/2005
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|
Publication #:
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Pub Dt:
|
12/22/2005
| | | | |
|
Title:
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TEST APPARATUS AND METHOD FOR TESTING CIRCUIT UNITS TO BE TESTED
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|
|
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Patent #:
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|
Issue Dt:
|
04/15/2008
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Application #:
|
11147260
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Filing Dt:
|
06/08/2005
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|
Publication #:
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Pub Dt:
|
12/14/2006
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR AUTOMATED BEAM OPTIMIZATION IN A SCANNING ELECTRON MICROSCOPE
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|
|
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|
Patent #:
|
|
Issue Dt:
|
04/15/2008
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Application #:
|
11147892
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Filing Dt:
|
06/08/2005
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|
Publication #:
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Pub Dt:
|
12/15/2005
| | | | |
|
Title:
|
COATING PROCESS FOR PATTERNED SUBSTRATE SURFACES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
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Application #:
|
11151650
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Filing Dt:
|
06/14/2005
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|
Publication #:
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|
Pub Dt:
|
01/11/2007
| | | | |
|
Title:
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MEMORY DEVICE WITH ERROR CORRECTION CODE MODULE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
11152769
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Filing Dt:
|
06/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
|
Title:
|
HIGH-SPEED INTERFACE CIRCUIT FOR SEMICONDUCTOR MEMORY CHIPS AND MEMORY SYSTEM INCLUDING SEMICONDUCTOR MEMORY CHIPS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
11152793
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Filing Dt:
|
06/15/2005
|
|
Publication #:
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|
Pub Dt:
|
12/21/2006
| | | | |
|
Title:
|
MEMORY CELL ARRAY AND METHOD OF FORMING THE SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11153187
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Filing Dt:
|
06/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
|
Title:
|
MEMORY HAVING PARITY GENERATION CIRCUIT
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|
|
|
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Patent #:
|
|
Issue Dt:
|
05/15/2007
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Application #:
|
11153510
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Filing Dt:
|
06/15/2005
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|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
|
Title:
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METHOD FOR CONNECTING AN INTEGRATED CIRCUIT TO A SUBSTRATE AND CORRESPONDING CIRCUIT ARRANGEMENT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
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Application #:
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11153795
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Filing Dt:
|
06/15/2005
|
|
Publication #:
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|
Pub Dt:
|
12/21/2006
| | | | |
|
Title:
|
MEMORY HAVING PARITY ERROR CORRECTION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2008
|
Application #:
|
11153811
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Filing Dt:
|
06/15/2005
|
|
Publication #:
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|
Pub Dt:
|
01/12/2006
| | | | |
|
Title:
|
METHOD FOR PRODUCING A PACKAGE FOR AN ELECTRONIC CIRCUIT AND A SUBSTRATE FOR A PACKAGE
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|
|
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|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
11153829
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Filing Dt:
|
06/15/2005
|
|
Publication #:
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Pub Dt:
|
12/29/2005
| | | | |
|
Title:
|
MEMORY DEVICE WITH MULTISTAGE SENSE AMPLIFIER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
11153969
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Filing Dt:
|
06/16/2005
|
|
Publication #:
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|
Pub Dt:
|
10/19/2006
| | | | |
|
Title:
|
RANDOM ACCESS MEMORY HAVING VOLTAGE PROVIDED OUT OF BOOSTED SUPPLY VOLTAGE
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|
