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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10688692
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Filing Dt:
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10/17/2003
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Publication #:
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Pub Dt:
|
04/21/2005
| | | | |
Title:
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DOUBLE SILICON-ON-INSULATOR (SOI) METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) STRUCTURES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10688744
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Filing Dt:
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10/17/2003
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Publication #:
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Pub Dt:
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01/06/2005
| | | | |
Title:
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Output driver impedance control for addressable memory devices
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Patent #:
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Issue Dt:
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12/04/2007
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Application #:
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10689506
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Filing Dt:
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10/20/2003
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Publication #:
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Pub Dt:
|
04/21/2005
| | | | |
Title:
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HIGH PERFORMANCE STRESS-ENHANCED MOSFETS USING SI:C AND SIGE EPITAXIAL SOURCE/DRAIN AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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12/08/2009
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Application #:
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10689675
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Filing Dt:
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10/22/2003
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Publication #:
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Pub Dt:
|
04/28/2005
| | | | |
Title:
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CONTROL OF CARBON NANOTUBE DIAMETER USING CVD OR PECVD GROWTH
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Patent #:
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Issue Dt:
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07/25/2006
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Application #:
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10691299
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Filing Dt:
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10/22/2003
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Publication #:
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Pub Dt:
|
05/06/2004
| | | | |
Title:
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Structure for controlling the interface roughness of cobalt disilicide
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|
Patent #:
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Issue Dt:
|
09/18/2007
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Application #:
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10691881
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Filing Dt:
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10/23/2003
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Publication #:
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Pub Dt:
|
05/06/2004
| | | | |
Title:
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CHANGING AN ELECTRICAL RESISTANCE OF A RESISTOR
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Patent #:
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Issue Dt:
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02/12/2008
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Application #:
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10691882
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Filing Dt:
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10/23/2003
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Publication #:
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Pub Dt:
|
05/06/2004
| | | | |
Title:
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DRILL STACK FORMATION
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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10693199
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Filing Dt:
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10/24/2003
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Publication #:
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Pub Dt:
|
04/28/2005
| | | | |
Title:
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LOW-ACTIVATION ENERGY SILICON-CONTAINING RESIST SYSTEM
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Patent #:
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Issue Dt:
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07/17/2007
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Application #:
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10693276
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Filing Dt:
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10/23/2003
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Publication #:
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Pub Dt:
|
10/21/2004
| | | | |
Title:
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METHOD TO ACHIEVE LOW AND STABLE FERROMAGNETIC COUPLING FIELD
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Patent #:
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Issue Dt:
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04/29/2008
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Application #:
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10694299
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Filing Dt:
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10/27/2003
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Publication #:
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Pub Dt:
|
04/28/2005
| | | | |
Title:
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SIMULTANEOUS COMPUTATION OF MULTIPLE POINTS ON ONE OR MULTIPLE CUT LINES
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Patent #:
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Issue Dt:
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05/30/2006
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Application #:
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10694339
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Filing Dt:
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10/27/2003
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Publication #:
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Pub Dt:
|
04/28/2005
| | | | |
Title:
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RENESTING INTERACTION MAP INTO DESIGN FOR EFFICIENT LONG RANGE CALCULATIONS
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Patent #:
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Issue Dt:
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03/11/2008
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Application #:
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10694465
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Filing Dt:
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10/27/2003
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Publication #:
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Pub Dt:
|
04/28/2005
| | | | |
Title:
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INCORPORATION OF A PHASE MAP INTO FAST MODEL-BASED OPTICAL PROXIMITY CORRECTION SIMULATION KERNELS TO ACCOUNT FOR NEAR AND MID-RANGE FLARE
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Patent #:
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Issue Dt:
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03/07/2006
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Application #:
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10694466
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Filing Dt:
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10/27/2003
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Publication #:
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Pub Dt:
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04/28/2005
| | | | |
Title:
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EXTENDING THE RANGE OF LITHOGRAPHIC SIMULATION INTEGRALS
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Patent #:
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Issue Dt:
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10/23/2007
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Application #:
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10694473
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Filing Dt:
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10/27/2003
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Publication #:
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Pub Dt:
|
04/28/2005
| | | | |
Title:
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PERFORMANCE IN MODEL-BASED OPC ENGINE UTILIZING EFFICIENT POLYGON PINNING METHOD
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Patent #:
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Issue Dt:
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01/16/2007
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Application #:
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10694500
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Filing Dt:
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10/27/2003
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Publication #:
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Pub Dt:
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05/06/2004
| | | | |
Title:
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EDGE SEAL FOR A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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02/06/2007
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Application #:
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10695335
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Filing Dt:
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10/28/2003
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Publication #:
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Pub Dt:
|
05/13/2004
| | | | |
Title:
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FIN FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE
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Patent #:
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Issue Dt:
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07/24/2007
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Application #:
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10695336
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Filing Dt:
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10/28/2003
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Publication #:
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Pub Dt:
|
05/06/2004
| | | | |
Title:
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METHOD OF CONTROLLING GRAIN SIZE IN A POLYSILICON LAYER AND IN SEMICONDUCTOR DEVICES HAVING POLYSILICON STRUCTURES
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Patent #:
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Issue Dt:
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08/30/2011
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Application #:
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10695748
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Filing Dt:
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10/30/2003
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Publication #:
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Pub Dt:
|
05/05/2005
| | | | |
Title:
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STRUCTURE AND METHOD TO ENHANCE BOTH NFET AND PFET PERFORMANCE USING DIFFERENT KINDS OF STRESSED LAYERS
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Patent #:
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Issue Dt:
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12/20/2005
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Application #:
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10695752
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Filing Dt:
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10/30/2003
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Publication #:
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Pub Dt:
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05/05/2005
| | | | |
Title:
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STRUCTURE AND METHOD TO IMPROVE CHANNEL MOBILITY BY GATE ELECTRODE STRESS MODIFICATION
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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10696139
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
|
05/05/2005
| | | | |
Title:
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SEMIDIGITAL DELAY-LOCKED LOOP USING AN ANALOG-BASED FINITE STATE MACHINE
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Patent #:
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Issue Dt:
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04/01/2008
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Application #:
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10696511
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Filing Dt:
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10/28/2003
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Publication #:
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Pub Dt:
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04/28/2005
| | | | |
Title:
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AFFINITY-BASED CLUSTERING OF VECTORS FOR PARTITIONING THE COLUMNS OF A MATRIX
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Patent #:
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Issue Dt:
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03/01/2005
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Application #:
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10696601
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
|
12/02/2004
| | | | |
Title:
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FORMATION OF SILICON-GERMANIUM-ON-INSULATOR (SGOI) BY AN INTEGRAL HIGH TEMPERATURE SIMOX-GE INTERDIFFUSION ANNEAL
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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10696634
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
|
05/05/2005
| | | | |
Title:
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CMOS ON HYBRID SUBSTRATE WITH DIFFERENT CRYSTAL ORIENTATIONS USING SILICON-TO-SILICON DIRECT WAFER BONDING
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Patent #:
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Issue Dt:
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02/12/2008
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Application #:
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10696771
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Filing Dt:
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10/29/2003
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Publication #:
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Pub Dt:
|
05/05/2005
| | | | |
Title:
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METHOD AND APPARATUS FOR FABRICATING OR ALTERING MICROSTRUCTURES USING LOCAL CHEMICAL ALTERATIONS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10697012
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
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05/13/2004
| | | | |
Title:
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Semiconductor device and method for making the device having an electrically modulated conduction channel
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Patent #:
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Issue Dt:
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10/16/2007
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Application #:
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10697077
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Filing Dt:
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10/30/2003
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Publication #:
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Pub Dt:
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05/05/2005
| | | | |
Title:
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POROUS SILICON COMPOSITE STRUCTURE AS LARGE FILTRATION ARRAY
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Patent #:
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Issue Dt:
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07/13/2010
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Application #:
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10697271
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
|
05/05/2005
| | | | |
Title:
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METHOD AND STRUCTURE FOR ULTRA-HIGH DENSITY, HIGH DATA RATE FERROELECTRIC STORAGE DISK TECHNOLOGY USING STABILIZATION BY A SURFACE CONDUCTING LAYER
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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10698122
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
|
05/05/2005
| | | | |
Title:
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HIGH MOBILITY HETEROJUNCTION COMPLEMENTARY FIELD EFFECT TRANSISTORS AND METHODS THEREOF
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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10698483
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Filing Dt:
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11/03/2003
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Publication #:
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Pub Dt:
|
05/05/2005
| | | | |
Title:
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STRUCTURE AND METHOD FOR FORMING A DIELECTRIC CHAMBER AND ELECTRONIC DEVICE INCLUDING THE DIELECTRIC CHAMBER
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Patent #:
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Issue Dt:
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05/01/2007
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Application #:
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10698884
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
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05/13/2004
| | | | |
Title:
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METHOD AND APPARATUS FOR PERFORMING LASER CVD
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10699122
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Filing Dt:
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10/30/2003
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Publication #:
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Pub Dt:
|
05/05/2005
| | | | |
Title:
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COOLING OF SURFACE TEMPERATURE OF A DEVICE
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Patent #:
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Issue Dt:
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03/06/2007
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Application #:
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10699226
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
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05/05/2005
| | | | |
Title:
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PLASMA ENHANCED ALD OF TANTALUM NITRIDE AND BILAYER
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Patent #:
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Issue Dt:
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03/06/2007
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Application #:
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10699238
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
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07/29/2004
| | | | |
Title:
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POLYCARBOSILANE BURIED ETCH STOPS IN INTERCONNECT STRUCTURES
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Patent #:
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Issue Dt:
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02/24/2009
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Application #:
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10699283
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Filing Dt:
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10/31/2003
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Publication #:
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Pub Dt:
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05/05/2005
| | | | |
Title:
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TECHNIQUES FOR RECONSTRUCTING SYNTHETIC NETWORKS USING PAIR-WISE CORRELATION ANALYSIS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10699399
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Filing Dt:
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10/30/2003
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Publication #:
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Pub Dt:
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05/05/2005
| | | | |
Title:
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Transparent cooling duct
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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10700085
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Filing Dt:
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11/03/2003
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Publication #:
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Pub Dt:
|
05/05/2005
| | | | |
Title:
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METHOD FOR FABRICATING SIGE-ON-INSULATOR (SGOI) AND GE-ON-INSULATOR (GOI) SUBSTRATES
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Patent #:
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Issue Dt:
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11/11/2008
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Application #:
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10700327
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Filing Dt:
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11/03/2003
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Publication #:
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Pub Dt:
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05/19/2005
| | | | |
Title:
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METHOD AND APPARATUS FOR FILLING VIAS
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Patent #:
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Issue Dt:
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05/20/2008
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Application #:
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10700989
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Filing Dt:
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11/04/2003
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Publication #:
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Pub Dt:
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05/05/2005
| | | | |
Title:
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METHOD FOR CONTROLLING POWER CHANGE FOR A SEMICONDUCTOR MODULE
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10701191
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Filing Dt:
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11/04/2003
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Publication #:
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Pub Dt:
|
05/05/2005
| | | | |
Title:
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METHOD FOR FORMING AN ELECTRONIC DEVICE
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10701311
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Filing Dt:
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11/04/2003
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Publication #:
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Pub Dt:
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05/05/2005
| | | | |
Title:
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HIGH DENSITY MICROVIA SUBSTRATE WITH HIGH WIREABILITY
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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10701526
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Filing Dt:
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11/06/2003
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Publication #:
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Pub Dt:
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05/12/2005
| | | | |
Title:
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HIGH MOBILITY CMOS CIRCUITS
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Patent #:
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Issue Dt:
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08/25/2009
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Application #:
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10702280
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Filing Dt:
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11/06/2003
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Publication #:
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Pub Dt:
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05/12/2005
| | | | |
Title:
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NEGATIVE COEFFICIENT OF THERMAL EXPANSION PARTICLES AND METHOD OF FORMING THE SAME
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
10702416
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Filing Dt:
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11/06/2003
|
Publication #:
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Pub Dt:
|
05/12/2005
| | | | |
Title:
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Apparatus and method for low pressure wirebond
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Patent #:
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Issue Dt:
|
05/31/2011
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Application #:
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10703355
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Filing Dt:
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11/07/2003
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Publication #:
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Pub Dt:
|
05/12/2005
| | | | |
Title:
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METHODS FOR FABRICATING A METAL-OXIDE-SEMICONDUCTOR DEVICE STRUCTURE
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Patent #:
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|
Issue Dt:
|
07/20/2004
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Application #:
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10704052
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Filing Dt:
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11/07/2003
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Publication #:
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Pub Dt:
|
06/03/2004
| | | | |
Title:
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OXYNITRIDE SHALLOW TRENCH ISOLATION AND METHOD OF FORMATION
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Patent #:
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Issue Dt:
|
12/14/2004
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Application #:
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10705115
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Filing Dt:
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11/10/2003
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Publication #:
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Pub Dt:
|
06/03/2004
| | | | |
Title:
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SEMICONDUCTOR STRUCTURE HAVING IN-SITU FORMED UNIT RESISTORS AND METHOD FOR FABRICATION
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Patent #:
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Issue Dt:
|
12/07/2004
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Application #:
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10705116
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Filing Dt:
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11/10/2003
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Publication #:
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Pub Dt:
|
05/20/2004
| | | | |
Title:
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SEMICONDUCTOR STRUCTURE HAVING IN-SITU FORMED UNIT RESISTORS AND METHOD FOR FABRICATION
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10706061
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Filing Dt:
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11/13/2003
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Publication #:
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Pub Dt:
|
05/19/2005
| | | | |
Title:
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A METHOD OF MANUFACTURING A STRAINED SILICON ON A SIGE ON SOI SUBSTRATE
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Patent #:
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Issue Dt:
|
02/28/2006
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Application #:
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10706228
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Filing Dt:
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11/12/2003
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Publication #:
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Pub Dt:
|
05/12/2005
| | | | |
Title:
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DATABASE MINING SYSTEM AND METHOD FOR COVERAGE ANALYSIS OF FUNCTIONAL VERIFICATION OF INTEGRATED CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
|
03/08/2005
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Application #:
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10706538
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Filing Dt:
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11/12/2003
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Publication #:
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Pub Dt:
|
05/20/2004
| | | | |
Title:
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METHOD FOR INSERTION OF TEST POINTS INTO INTEGRATED LOGIC CIRCUIT DESIGNS
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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10706773
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Filing Dt:
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11/12/2003
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Publication #:
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Pub Dt:
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09/09/2004
| | | | |
Title:
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ADVANCED BEOL INTERCONNECT STRUCTURES WITH LOW-K PE CVD CAP LAYER AND METHOD THEREOF
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Patent #:
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Issue Dt:
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02/14/2006
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Application #:
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10707009
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Filing Dt:
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11/13/2003
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Publication #:
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Pub Dt:
|
05/19/2005
| | | | |
Title:
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ALTERNATING PHASE MASK BUILT BY ADDITIVE FILM DEPOSITION
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Patent #:
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Issue Dt:
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10/17/2006
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Application #:
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10707018
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Filing Dt:
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11/14/2003
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Publication #:
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Pub Dt:
|
05/19/2005
| | | | |
Title:
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STRESSED SEMICONDUCTOR DEVICE STRUCTURES HAVING GRANULAR SEMICONDUCTOR MATERIAL
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Patent #:
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Issue Dt:
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01/12/2010
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Application #:
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10707053
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Filing Dt:
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11/18/2003
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Publication #:
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Pub Dt:
|
05/19/2005
| | | | |
Title:
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MEMORY DEVICE WITH PROGRAMMABLE RECEIVERS TO IMPROVE PERFORMANCE
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Patent #:
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Issue Dt:
|
01/30/2007
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Application #:
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10707064
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Filing Dt:
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11/19/2003
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Publication #:
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Pub Dt:
|
05/19/2005
| | | | |
Title:
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OPTIMUM PADSET FOR WIRE BONDING RF TECHNOLOGIES WITH HIGH-Q INDUCTORS
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Patent #:
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Issue Dt:
|
10/31/2006
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Application #:
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10707065
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Filing Dt:
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11/19/2003
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Publication #:
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Pub Dt:
|
05/19/2005
| | | | |
Title:
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TRI-METAL AND DUAL-METAL STACKED INDUCTORS
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Patent #:
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Issue Dt:
|
08/08/2006
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Application #:
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10707069
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Filing Dt:
|
11/19/2003
|
Publication #:
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|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
METHODOLOGY FOR PLACEMENT BASED ON CIRCUIT FUNCTION AND LATCHUP SENSITIVITY
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10707075
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Filing Dt:
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11/19/2003
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Publication #:
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Pub Dt:
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05/19/2005
| | | | |
Title:
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SEEDLESS WIREBOND PAD PLATING
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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10707089
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Filing Dt:
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11/20/2003
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Publication #:
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Pub Dt:
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05/26/2005
| | | | |
Title:
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IMPROVED BOND PAD
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Patent #:
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Issue Dt:
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08/29/2006
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Application #:
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10707117
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
| | | | |
Title:
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INTERCONNECT STRUCTURE DIFFUSION BARRIER WITH HIGH NITROGEN CONTENT
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Patent #:
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Issue Dt:
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12/28/2004
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Application #:
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10707120
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Filing Dt:
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11/21/2003
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Title:
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ENDPOINT DETECTION IN CHEMICAL-MECHANICAL POLISHING OF PATTERNED WAFERS HAVING A LOW PATTERN DENSITY
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Patent #:
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Issue Dt:
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09/06/2005
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Application #:
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10707121
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
| | | | |
Title:
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VARIATION OF EFFECTIVE FILTER CAPACITANCE IN PHASE LOCK LOOP CIRCUIT LOOP FILTERS
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Patent #:
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Issue Dt:
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10/17/2006
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Application #:
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10707122
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Filing Dt:
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11/21/2003
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Publication #:
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Pub Dt:
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05/26/2005
| | | | |
Title:
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BACK END INTERCONNECT WITH A SHAPED INTERFACE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10707150
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Filing Dt:
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11/24/2003
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Publication #:
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Pub Dt:
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05/26/2005
| | | | |
Title:
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DYNAMIC RELEASE WAFER GRIP AND METHOD OF USE
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10707175
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Filing Dt:
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11/25/2003
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Publication #:
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Pub Dt:
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05/26/2005
| | | | |
Title:
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METHOD OF FORMING ULTRA-THIN SILICIDATION-STOP EXTENSIONS IN MOSFET DEVICES
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Patent #:
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Issue Dt:
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09/20/2005
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Application #:
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10707178
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Filing Dt:
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11/25/2003
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Publication #:
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Pub Dt:
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05/26/2005
| | | | |
Title:
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PHASE FREQUENCY DETECTOR WITH PROGRAMMABLE MINIMUM PULSE WIDTH
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Patent #:
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Issue Dt:
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06/13/2006
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Application #:
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10707200
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Filing Dt:
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11/26/2003
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Publication #:
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Pub Dt:
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05/26/2005
| | | | |
Title:
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ULTRA-THIN SOI MOSFET METHOD AND STRUCTURE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10707282
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Filing Dt:
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12/03/2003
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Publication #:
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Pub Dt:
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06/16/2005
| | | | |
Title:
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APPARATUS AND METHOD FOR ELECTRONIC FUSE WITH IMPROVED ESD TOLERANCE
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Patent #:
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Issue Dt:
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09/12/2006
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Application #:
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10707283
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Filing Dt:
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12/03/2003
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Publication #:
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Pub Dt:
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06/09/2005
| | | | |
Title:
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APPARATUS AND METHOD FOR ELECTRONIC FUSE WITH IMPROVED ESD TOLERANCE
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Patent #:
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Issue Dt:
|
07/03/2007
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Application #:
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10707373
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Filing Dt:
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12/09/2003
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Publication #:
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Pub Dt:
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06/23/2005
| | | | |
Title:
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SCAN CHAIN DIAGNOSTICS USING LOGIC PATHS
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
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10707388
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Filing Dt:
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12/10/2003
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Publication #:
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Pub Dt:
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06/16/2005
| | | | |
Title:
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SILICIDE RESISTOR IN BEOL LAYER OF SEMICONDUCTOR DEVICE AND METHOD
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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10707449
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Filing Dt:
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12/15/2003
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Publication #:
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Pub Dt:
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06/17/2004
| | | | |
Title:
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METHOD AND STRUCTURE FOR FORMING PRECISION MIM FUSIBLE CIRCUIT ELEMENTS USING FUSES AND ANTIFUSES
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|
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Patent #:
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Issue Dt:
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06/24/2008
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Application #:
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10707479
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Filing Dt:
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12/17/2003
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Publication #:
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Pub Dt:
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10/21/2004
| | | | |
Title:
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SYSTEM FOR IMPROVING POWER DISTRIBUTION CURRENT MEASUREMENT ON PRINTED CIRCUIT BOARDS
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|
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Patent #:
|
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Issue Dt:
|
07/24/2007
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Application #:
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10707690
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Filing Dt:
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01/05/2004
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Publication #:
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|
Pub Dt:
|
07/07/2005
| | | | |
Title:
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STRUCTURES AND METHODS FOR MAKING STRAINED MOSFETS
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|
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Patent #:
|
|
Issue Dt:
|
08/29/2006
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Application #:
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10707713
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Filing Dt:
|
01/06/2004
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Publication #:
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Pub Dt:
|
07/07/2005
| | | | |
Title:
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EDGE SEAL FOR INTEGRATED CIRCUIT CHIPS
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Patent #:
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Issue Dt:
|
10/10/2006
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Application #:
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10707722
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Filing Dt:
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01/07/2004
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Publication #:
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Pub Dt:
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07/14/2005
| | | | |
Title:
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TUNABLE SEMICONDUCTOR DIODES
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10707725
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Filing Dt:
|
01/07/2004
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Publication #:
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Pub Dt:
|
07/07/2005
| | | | |
Title:
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METHOD OF MAKING FIELD EFFECT TRANSISTORS HAVING SELF-ALIGNED SOURCE AND DRAIN REGIONS USING INDEPENDENTLY CONTROLLED SPACER WIDTHS
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Patent #:
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|
Issue Dt:
|
07/18/2006
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Application #:
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10707746
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Filing Dt:
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01/08/2004
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Publication #:
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Pub Dt:
|
07/14/2005
| | | | |
Title:
|
Method for integrating thermistor
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|
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Patent #:
|
|
Issue Dt:
|
06/06/2006
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Application #:
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10707757
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Filing Dt:
|
01/09/2004
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Publication #:
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Pub Dt:
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07/14/2005
| | | | |
Title:
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FET GATE STRUCTURE WITH METAL GATE ELECTRODE AND SILICIDE CONTACT
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|
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Patent #:
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Issue Dt:
|
12/13/2005
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Application #:
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10707759
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Filing Dt:
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01/09/2004
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Publication #:
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Pub Dt:
|
07/14/2005
| | | | |
Title:
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METHOD OF FORMING FET SILICIDE GATE STRUCTURES INCORPORATING INNER SPACERS
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|
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Patent #:
|
|
Issue Dt:
|
01/01/2008
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Application #:
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10707776
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Filing Dt:
|
01/12/2004
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Publication #:
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Pub Dt:
|
07/14/2005
| | | | |
Title:
|
METHOD AND SYSTEM FOR CREATING, VIEWING, EDITING, AND SHARING OUTPUT FROM A DESIGN CHECKING SYSTEM
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|
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Patent #:
|
|
Issue Dt:
|
01/17/2006
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Application #:
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10707810
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Filing Dt:
|
01/14/2004
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Publication #:
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|
Pub Dt:
|
07/14/2005
| | | | |
Title:
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MULTILAYER CERAMIC SUBSTRATE WITH SINGLE VIA ANCHORED PAD AND METHOD OF FORMING
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|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
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Application #:
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10707811
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Filing Dt:
|
01/14/2004
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Publication #:
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|
Pub Dt:
|
07/14/2005
| | | | |
Title:
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SACRIFICIAL INORGANIC POLYMER INTERMETAL DIELECTRIC DAMASCENE WIRE AND VIA LINER
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|
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Patent #:
|
|
Issue Dt:
|
04/10/2007
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Application #:
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10707840
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Filing Dt:
|
01/16/2004
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Publication #:
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Pub Dt:
|
07/21/2005
| | | | |
Title:
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PROTECTING SILICON GERMANIUM SIDEWALL WITH SILICON FOR STRAINED SILICON/SILICON GERMANIUM MOSFETS
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|
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Patent #:
|
|
Issue Dt:
|
06/03/2008
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Application #:
|
10707841
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Filing Dt:
|
01/16/2004
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Publication #:
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|
Pub Dt:
|
07/21/2005
| | | | |
Title:
|
METHOD AND STRUCTURE FOR CONTROLLING STRESS IN A TRANSISTOR CHANNEL
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|
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Patent #:
|
|
Issue Dt:
|
10/10/2006
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Application #:
|
10707842
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Filing Dt:
|
01/16/2004
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Publication #:
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|
Pub Dt:
|
07/21/2005
| | | | |
Title:
|
METHOD AND APPARATUS TO INCREASE STRAIN EFFECT IN A TRANSISTOR CHANNEL
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|
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Patent #:
|
|
Issue Dt:
|
11/29/2005
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Application #:
|
10707863
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Filing Dt:
|
01/19/2004
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Publication #:
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|
Pub Dt:
|
07/21/2005
| | | | |
Title:
|
HIGH TOLERANCE TCR BALANCED HIGH CURRENT RESISTOR FOR RF CMOS AND RF SIGE BICMOS APPLICATIONS AND CADENCED BASED HIERARCHICAL PARAMETERIZED CELL DESIGN KIT WITH TUNABLE TCR AND ESD RESISTOR BALLASTING FEATURE
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|
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Patent #:
|
|
Issue Dt:
|
11/25/2008
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Application #:
|
10707864
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Filing Dt:
|
01/19/2004
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Publication #:
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Pub Dt:
|
07/21/2005
| | | | |
Title:
|
ALIGNMENT MARK SYSTEM AND METHOD TO IMPROVE WAFER ALIGNMENT SEARCH RANGE
|
|
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Patent #:
|
|
Issue Dt:
|
10/19/2004
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Application #:
|
10707890
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Filing Dt:
|
01/21/2004
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Title:
|
INTEGRATION SCHEME FOR ENHANCING CAPACITANCE OF TRENCH CAPACITORS
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|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10707891
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Filing Dt:
|
01/21/2004
|
Publication #:
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|
Pub Dt:
|
07/21/2005
| | | | |
Title:
|
LOW-VOLTAGE DIFFERENTIAL AMPLIFIER
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|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
10707896
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Filing Dt:
|
01/22/2004
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Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
Title:
|
Method of manufacturing high performance copper inductors with bond pads
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|
|
Patent #:
|
|
Issue Dt:
|
11/21/2006
|
Application #:
|
10707897
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Filing Dt:
|
01/22/2004
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
Title:
|
SELECTIVE NITRIDATION OF GATE OXIDES
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|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
10707962
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Filing Dt:
|
01/28/2004
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
Title:
|
ALTERNATING PHASE SHIFT MASK DESIGN FOR HIGH PERFORMANCE CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10707963
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Filing Dt:
|
01/28/2004
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
Title:
|
FUSE LATCH WITH COMPENSATED PROGRAMMABLE RESISTIVE TRIP POINT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
10707964
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Filing Dt:
|
01/28/2004
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
Title:
|
METHOD AND STRUCTURE TO CREATE MULTIPLE DEVICE WIDTHS IN FINFET TECHNOLOGY IN BOTH BULK AND SOI
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
10707996
|
Filing Dt:
|
01/30/2004
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
Title:
|
DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2007
|
Application #:
|
10708023
|
Filing Dt:
|
02/03/2004
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
Title:
|
STRUCTURE AND METHOD FOR LOCAL RESISTOR ELEMENT IN INTEGRATED CIRCUIT TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
10708039
|
Filing Dt:
|
02/04/2004
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
Title:
|
IC DESIGN MODELING ALLOWING DIMENSION-DEPENDENT RULE CHECKING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
10708184
|
Filing Dt:
|
02/13/2004
|
Publication #:
|
|
Pub Dt:
|
09/01/2005
| | | | |
Title:
|
A COMMAND MULTIPLIER FOR BUILT-IN-SELF-TEST
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10708233
|
Filing Dt:
|
02/18/2004
|
Publication #:
|
|
Pub Dt:
|
08/18/2005
| | | | |
Title:
|
DYNAMIC THRESHOLD FOR VCO CALIBRATION
|
|