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02/24/2009
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10729511
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12/04/2003
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06/09/2005
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Title:
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PRECURSORS TO FLUOROALKANOL-CONTAINING OLEFIN MONOMERS, AND ASSOCIATED METHODS OF SYNTHESIS AND USE
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02/07/2006
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10729750
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12/04/2003
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06/09/2005
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Title:
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DATA PROCESSING IN DIGITAL SYSTEMS
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10/23/2007
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10729751
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12/04/2003
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06/09/2005
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Title:
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DIGITAL RELIABILITY MONITOR HAVING AUTONOMIC REPAIR AND NOTIFICATION CAPABILITY
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07/04/2006
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10730892
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12/10/2003
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06/16/2005
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Title:
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FIELD EFFECT TRANSISTOR WITH ETCHED-BACK GATE DIELECTRIC
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01/03/2006
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10731298
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12/09/2003
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06/09/2005
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Title:
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METHOD AND CIRCUIT FOR COMPENSATING FOR TUNNELING CURRENT
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08/01/2006
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10731377
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12/08/2003
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06/16/2005
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Title:
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LINE LEVEL AIR GAPS
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11/04/2008
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10731520
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12/09/2003
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06/09/2005
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Title:
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APPARATUS AND METHODS FOR CONSTRUCTING ANTENNAS USING VIAS AS RADIATING ELEMENTS FORMED IN A SUBSTRATE
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08/29/2006
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10731840
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12/09/2003
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06/09/2005
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Title:
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SYSTEM AND METHOD FOR TOPOLOGY SELECTION TO MINIMIZE LEAKAGE POWER DURING SYNTHESIS
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NONE
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10732015
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12/10/2003
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06/16/2005
| | | | |
Title:
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Local reduction of compliant thermally conductive material layer thickness on chips
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01/16/2007
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10732277
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12/11/2003
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Pub Dt:
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07/22/2004
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Title:
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SOI MOSFETS EXHIBITING REDUCED FLOATING-BODY EFFECTS
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06/17/2008
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10732322
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12/10/2003
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06/16/2005
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Title:
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SECTIONAL FIELD EFFECT DEVICES
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05/17/2011
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10732579
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12/10/2003
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06/16/2005
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Title:
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INTEGRATED CIRCUIT WITH UPSTANDING STYLUS
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04/19/2011
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10732580
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12/10/2003
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06/16/2005
| | | | |
Title:
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PHASE CHANGE TIP STORAGE CELL
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09/25/2007
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10732953
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12/11/2003
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06/16/2005
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Title:
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SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SIO2
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09/18/2007
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10732958
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12/11/2003
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Pub Dt:
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06/16/2005
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Title:
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WRAP-AROUND GATE FIELD EFFECT TRANSISTOR
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04/03/2007
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10733378
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12/12/2003
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06/16/2005
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Title:
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STRAINED FINFETS AND METHOD OF MANUFACTURE
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05/20/2008
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10733974
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12/11/2003
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Pub Dt:
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06/16/2005
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Title:
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METHODS AND STRUCTURES FOR PROMOTING STABLE SYNTHESIS OF CARBON NANOTUBES
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NONE
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10734504
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12/12/2003
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Pub Dt:
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07/29/2004
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Title:
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Incorporation of an impurity into a thin film
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Patent #:
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Issue Dt:
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05/21/2013
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10735061
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12/11/2003
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Pub Dt:
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06/16/2005
| | | | |
Title:
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GATED DIODE MEMORY CELLS
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06/27/2006
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10735167
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12/12/2003
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Pub Dt:
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09/23/2004
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Title:
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SEMICONDUCTOR STRUCTURE HAVING AN ABRUPT DOPING PROFILE
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04/29/2008
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10735845
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12/16/2003
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Pub Dt:
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06/16/2005
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Title:
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INTERCONNECT STRUCTURES AND METHODS OF MAKING THEREOF
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Patent #:
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Issue Dt:
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06/29/2010
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10736424
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12/15/2003
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Pub Dt:
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06/16/2005
| | | | |
Title:
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TESTING OF TRANSIMPEDANCE AMPLIFIERS
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Patent #:
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02/24/2009
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10736890
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12/16/2003
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Pub Dt:
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08/05/2004
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Title:
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ANGLED FLYING LEAD WIRE BONDING PROCESS
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Issue Dt:
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12/29/2009
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10737563
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12/15/2003
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Pub Dt:
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06/30/2005
| | | | |
Title:
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REAL-TIME CHANNEL ADAPTATION
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Patent #:
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Issue Dt:
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10/24/2006
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10737626
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12/16/2003
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Pub Dt:
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06/16/2005
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Title:
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METHOD FOR OPTIMIZING A NUMBER OF KERNELS USED IN A SUM OF COHERENT SOURCES FOR OPTICAL PROXIMITY CORRECTION IN AN OPTICAL MICROLITHOGRAPHY PROCESS
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12/11/2007
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10737989
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12/17/2003
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Pub Dt:
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07/07/2005
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Title:
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METHOD, SYSTEM AND PROGRAM PRODUCT FOR FACILITATING FORWARDING OF DATA PACKETS THROUGH A NODE OF A DATA TRANSFER NETWORK USING MULTIPLE TYPES OF FORWARDING TABLES
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Patent #:
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Issue Dt:
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06/06/2006
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10738064
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12/17/2003
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Publication #:
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Pub Dt:
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06/23/2005
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Title:
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SILICON CARRIER FOR OPTICAL INTERCONNECT MODULES
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Patent #:
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Issue Dt:
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10/24/2006
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10738711
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12/17/2003
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Publication #:
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Pub Dt:
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06/23/2005
| | | | |
Title:
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METHOD AND APPARATUS FOR GENERATING STEINER TREES USING SIMULTANEOUS BLOCKAGE AVOIDANCE, DELAY OPTIMIZATION AND DESIGN DENSITY MANAGEMENT
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Patent #:
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Issue Dt:
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11/14/2006
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10738714
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12/17/2003
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Publication #:
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Pub Dt:
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06/23/2005
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Title:
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METHOD AND APPARATUS FOR PERFORMING DENSITY-BIASED BUFFER INSERTION IN AN INTEGRATED CIRCUIT DESIGN
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Issue Dt:
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03/21/2006
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10738799
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12/17/2003
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Pub Dt:
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07/08/2004
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Title:
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CONCURRENT ELECTRICAL SIGNAL WIRING OPTIMIZATION FOR AN ELECTRONIC PACKAGE
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Issue Dt:
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07/01/2008
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10739966
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12/18/2003
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Pub Dt:
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06/23/2005
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Title:
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DATA STORAGE SYSTEMS
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10/17/2006
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10741203
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12/19/2003
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Pub Dt:
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06/23/2005
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Title:
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DEEP TRENCH CAPACITOR WITH BURIED PLATE ELECTRODE AND ISOLATION COLLAR
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Issue Dt:
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11/22/2005
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10744368
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12/23/2003
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07/15/2004
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Title:
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WAFER WITH SEMICONDUCTOR CHIPS MOUNTED THEREON
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03/13/2007
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10745821
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12/23/2003
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Pub Dt:
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09/30/2004
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Title:
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FUZZY LOCATION OF A TESTABLE OBJECT IN A FUNCTIONAL TESTING TOOL
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Issue Dt:
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09/04/2012
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10745822
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12/23/2003
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Pub Dt:
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09/30/2004
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Title:
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LOCATING A TESTABLE OBJECT IN A FUNCTIONAL TESTING TOOL
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Issue Dt:
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09/12/2006
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10746536
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12/23/2003
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Pub Dt:
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10/14/2004
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Title:
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DISAMBIGUATING LIKE TESTABLE OBJECTS IN A FUNCTIONAL TESTING TOOL
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Issue Dt:
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06/26/2007
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10749607
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12/31/2003
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Pub Dt:
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07/07/2005
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Title:
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METHOD AND SYSTEM FOR SELECTIVE COMPILATION OF INSTRUMENTATION ENTITIES INTO A SIMULATION MODEL OF A DIGITAL DESIGN
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Issue Dt:
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08/22/2006
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10749759
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12/31/2003
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Publication #:
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Pub Dt:
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07/07/2005
| | | | |
Title:
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METHOD, SYSTEM AND PROGRAM PRODUCT PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING ARBITRARY MAPPING FUNCTIONS FOR CONFIGURATION CONSTRUCTS
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Issue Dt:
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05/19/2009
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10750590
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12/31/2003
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Pub Dt:
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07/07/2005
| | | | |
Title:
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METHOD, SYSTEM AND PROGRAM PRODUCT SUPPORTING USER TRACING IN A SIMULATOR
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Patent #:
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Issue Dt:
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12/06/2005
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10750697
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01/02/2004
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Pub Dt:
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07/22/2004
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Title:
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ENHANCED T-GATE STRUCTURE FOR MODULATION DOPED FIELD EFFECT TRANSISTORS
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Issue Dt:
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04/11/2006
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10751713
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01/05/2004
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Pub Dt:
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07/07/2005
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Title:
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3T1D MEMORY CELLS USING GATED DIODES AND METHODS OF USE THEREOF
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Patent #:
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Issue Dt:
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12/04/2012
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10751714
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01/05/2004
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Pub Dt:
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07/07/2005
| | | | |
Title:
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AMPLIFIERS USING GATED DIODES
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Patent #:
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Issue Dt:
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02/08/2005
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10751758
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01/05/2004
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Pub Dt:
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07/15/2004
| | | | |
Title:
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BACKSIDE INTEGRATED CIRCUIT DIE SURFACE FINISHING TECHNIQUE AND TOOL
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Patent #:
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Issue Dt:
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01/20/2009
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10751831
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01/05/2004
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Pub Dt:
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12/02/2004
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Title:
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STI STRESS MODIFICATION BY NITROGEN PLASMA TREATMENT FOR IMPROVING PERFORMANCE IN SMALL WIDTH DEVICES
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Issue Dt:
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04/27/2010
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10751916
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01/07/2004
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Pub Dt:
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07/07/2005
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Title:
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HIGH PERFORMANCE STRAINED SILICON FINFETS DEVICE AND METHOD FOR FORMING SAME
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Patent #:
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Issue Dt:
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03/21/2006
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10752162
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01/06/2004
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Pub Dt:
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07/07/2005
| | | | |
Title:
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METHOD OF PROCESSING BACKSIDE UNLAYERING OF MOSFET DEVICES FOR ELECTRICAL AND PHYSICAL CHARACTERIZATION INCLUDING A COLLIMATED ION PLASMA
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Issue Dt:
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11/15/2005
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10752255
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01/06/2004
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Pub Dt:
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07/22/2004
| | | | |
Title:
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STRESS RESISTANT LAND GRID ARRAY (LGA) MODULE AND METHOD OF FORMING THE SAME
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Patent #:
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NONE
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Application #:
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10753001
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Filing Dt:
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01/07/2004
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Pub Dt:
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07/22/2004
| | | | |
Title:
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Optimized blocking impurity placement for SiGe HBTs
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Issue Dt:
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04/01/2008
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10753241
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01/08/2004
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Pub Dt:
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07/22/2004
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Title:
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INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY OXIDATION OR NITRIDIZATION
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03/07/2006
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10753431
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01/09/2004
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Pub Dt:
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07/22/2004
| | | | |
Title:
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METHOD OF BUILDING A CMOS STRUCTURE ON THIN SOI WITH SOURCE/DRAIN ELECTRODES FORMED BY IN SITU DOPED SELECTIVE AMORPHOUS SILICON
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Issue Dt:
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06/20/2006
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10753989
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01/08/2004
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Pub Dt:
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07/14/2005
| | | | |
Title:
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POSITIVE PHOTORESIST COMPOSITION WITH A POLYMER INCLUDING A FLUOROSULFONAMIDE GROUP AND PROCESS FOR ITS USE
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Issue Dt:
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05/02/2006
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10754020
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01/08/2004
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Pub Dt:
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07/22/2004
| | | | |
Title:
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NON-PLANAR SURFACE FOR SEMICONDUCTOR CHIPS
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Issue Dt:
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08/29/2006
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10754232
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01/08/2004
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Pub Dt:
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07/14/2005
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Title:
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AUTOMATED MATERIAL HANDLING LASER ALIGNMENT TOOL
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Issue Dt:
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10/25/2005
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10754320
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01/08/2004
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Publication #:
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Pub Dt:
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07/14/2005
| | | | |
Title:
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DISCRIMINATIVE SOI WITH OXIDE HOLES UNDERNEATH DC SOURCE/DRAIN
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Issue Dt:
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06/27/2006
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10755816
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Filing Dt:
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01/12/2004
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04/21/2005
| | | | |
Title:
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METHOD AND APPARATUS FOR THERMO-OPTIC MODULATION OF OPTICAL SIGNALS
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04/22/2008
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10755875
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01/13/2004
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Pub Dt:
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07/14/2005
| | | | |
Title:
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REAL-TIME CONFIGURABLE MASKING
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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10756556
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Filing Dt:
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01/12/2004
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Publication #:
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Pub Dt:
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09/02/2004
| | | | |
Title:
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THIN FILM PROTECTIVE LAYER WITH BUFFERING INTERFACE
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10757199
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Filing Dt:
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01/14/2004
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Publication #:
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Pub Dt:
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07/14/2005
| | | | |
Title:
|
A METHOD OF FORMING A DIELECTIC SUBSTRATE HAVING A MULTITURN INDUCTOR
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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10757846
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Filing Dt:
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01/15/2004
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Publication #:
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Pub Dt:
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07/21/2005
| | | | |
Title:
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CONCURRENT REFRESH MODE WITH DISTRIBUTED ROW ADDRESS COUNTERS IN AN EMBEDDED DRAM
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10758724
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Filing Dt:
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01/16/2004
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Publication #:
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Pub Dt:
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07/21/2005
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Title:
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LOW K AND ULTRA LOW K SICOH DIELECTRIC FILMS AND METHODS TO FORM THE SAME
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Patent #:
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Issue Dt:
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03/13/2007
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Application #:
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10763308
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Filing Dt:
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01/23/2004
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Publication #:
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Pub Dt:
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09/30/2004
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Title:
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CMOS DEVICE INTEGRATION FOR LOW EXTERNAL RESISTANCE
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Patent #:
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Issue Dt:
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02/07/2006
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Application #:
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10765042
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Filing Dt:
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01/28/2004
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Publication #:
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Pub Dt:
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07/28/2005
| | | | |
Title:
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HIGH PERFORMANCE INTERPOSER FOR A CHIP PACKAGE USING DEFORMABLE BUTTON CONTACTS
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Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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10766249
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Filing Dt:
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01/27/2004
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Publication #:
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Pub Dt:
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09/30/2004
| | | | |
Title:
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ELECTRONIC STRUCTURES WITH REDUCED CAPACITANCE
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Patent #:
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Issue Dt:
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08/30/2005
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Application #:
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10766936
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Filing Dt:
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01/30/2004
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Publication #:
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Pub Dt:
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08/04/2005
| | | | |
Title:
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PHASE-CHANGE MEMORY CELL AND METHOD OF FABRICATING THE PHASE-CHANGE MEMORY CELL
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10767065
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Filing Dt:
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01/29/2004
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Publication #:
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Pub Dt:
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08/04/2005
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Title:
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Vertical nanotube semiconductor device structures and methods of forming the same
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10768341
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Filing Dt:
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01/30/2004
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Publication #:
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Pub Dt:
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08/04/2005
| | | | |
Title:
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High electrical quality buried oxide in simox
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Patent #:
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Issue Dt:
|
09/16/2008
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Application #:
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10768347
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Filing Dt:
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01/29/2004
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Publication #:
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Pub Dt:
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08/04/2005
| | | | |
Title:
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ENHANCEMENT OF MAGNETIC MEDIA RECORDING PERFORMANCE USING ION IRRADIATION TO TAILOR EXCHANGE COUPLING
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10768773
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Filing Dt:
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01/29/2004
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Publication #:
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Pub Dt:
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08/04/2005
| | | | |
Title:
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HIGH Q FACTOR INTEGRATED CIRCUIT INDUCTOR
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Patent #:
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Issue Dt:
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05/16/2006
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Application #:
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10769132
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Filing Dt:
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01/29/2004
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Publication #:
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Pub Dt:
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08/04/2005
| | | | |
Title:
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APPARATUS FOR CHARACTERIZATION OF PHOTORESIST RESOLUTION, AND METHOD OF USE
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Patent #:
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Issue Dt:
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12/13/2005
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Application #:
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10770264
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Filing Dt:
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02/02/2004
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Publication #:
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Pub Dt:
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08/04/2005
| | | | |
Title:
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METHOD OF MAKING ENCAPSULATED SPACERS IN VERTICAL PASS GATE DRAM AND DAMASCENE LOGIC GATES
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Patent #:
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Issue Dt:
|
08/02/2005
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Application #:
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10770278
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Filing Dt:
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02/02/2004
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Publication #:
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Pub Dt:
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01/27/2005
| | | | |
Title:
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COLLAR FORMATION USING SELECTIVE SIGE/SI ETCH
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|
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Patent #:
|
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Issue Dt:
|
03/13/2007
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Application #:
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10771817
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Filing Dt:
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06/16/2004
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Publication #:
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Pub Dt:
|
11/18/2004
| | | | |
Title:
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METHOD OF MANUFACTURE OF SILICON BASED PACKAGE AND DEVICES MANUFACTURED THEREBY
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|
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Patent #:
|
|
Issue Dt:
|
02/15/2005
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Application #:
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10771824
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Filing Dt:
|
02/03/2004
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Title:
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SRAM CELL WITH WELL CONTACTS AND P+ DIFFUSION CROSSING TO GROUND OR N+ DIFFUSION CROSSING TO VDD
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|
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Patent #:
|
|
Issue Dt:
|
09/20/2005
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Application #:
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10773434
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Filing Dt:
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02/09/2004
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Publication #:
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Pub Dt:
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11/18/2004
| | | | |
Title:
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ELECTROPLATED INTERCONNECTION STRUCTURES ON INTEGRATED CIRCUIT CHIPS
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|
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Patent #:
|
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Issue Dt:
|
01/31/2006
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Application #:
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10773930
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Filing Dt:
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02/06/2004
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Publication #:
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Pub Dt:
|
08/11/2005
| | | | |
Title:
|
NEGATIVE PHOTORESIST COMPOSITION INVOLVING NON-CROSSLINKING CHEMISTRY
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|
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Patent #:
|
|
Issue Dt:
|
06/20/2006
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Application #:
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10774773
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Filing Dt:
|
02/09/2004
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Publication #:
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|
Pub Dt:
|
08/19/2004
| | | | |
Title:
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FIN-TYPE RESISTORS
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|
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Patent #:
|
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Issue Dt:
|
07/17/2007
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Application #:
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10774827
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Filing Dt:
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02/09/2004
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Publication #:
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Pub Dt:
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08/11/2005
| | | | |
Title:
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LINE MASK DEFINED ACTIVE AREAS FOR 8F2 DRAM CELLS WITH FOLDED BIT LINES AND DEEP TRENCH PATTERNS
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|
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Patent #:
|
|
Issue Dt:
|
06/05/2007
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Application #:
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10775440
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Filing Dt:
|
02/10/2004
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Publication #:
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|
Pub Dt:
|
09/02/2004
| | | | |
Title:
|
LOW K-GATE SPACERS BY FLUORINE IMPLANTATION
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|
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Patent #:
|
|
Issue Dt:
|
02/27/2007
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Application #:
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10775514
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Filing Dt:
|
02/10/2004
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Publication #:
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|
Pub Dt:
|
08/19/2004
| | | | |
Title:
|
EPITAXIAL AND POLYCRYSTALLINE GROWTH OF SI1-X-YGEXCY AND SI1-YCY ALLOY LAYERS ON SI BY UHV-CVD
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|
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Patent #:
|
|
Issue Dt:
|
06/21/2005
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Application #:
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10775515
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Filing Dt:
|
02/10/2004
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Publication #:
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|
Pub Dt:
|
08/19/2004
| | | | |
Title:
|
EPITAXIAL AND POLYCRYSTALLINE GROWTH OF SI1-X-YGEXCY AND SI1-YCY ALLOY LAYERS ON SI BY UHV-CVD
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|
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Patent #:
|
|
Issue Dt:
|
05/01/2007
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Application #:
|
10775854
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Filing Dt:
|
02/10/2004
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Publication #:
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|
Pub Dt:
|
08/11/2005
| | | | |
Title:
|
CIRCUIT BOARD INTEGRATED OPTICAL COUPLING ELEMENTS
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|
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Patent #:
|
|
Issue Dt:
|
07/18/2006
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Application #:
|
10775922
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Filing Dt:
|
02/10/2004
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Publication #:
|
|
Pub Dt:
|
08/19/2004
| | | | |
Title:
|
LAND GRID ARRAY STRUCTURES AND METHODS FOR ENGINEERING CHANGE
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|
|
Patent #:
|
|
Issue Dt:
|
09/20/2005
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Application #:
|
10776737
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Filing Dt:
|
02/10/2004
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Publication #:
|
|
Pub Dt:
|
08/11/2005
| | | | |
Title:
|
INTEGRATED CIRCUIT REDISTRIBUTION PACKAGE
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|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
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Application #:
|
10776901
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Filing Dt:
|
02/10/2004
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Publication #:
|
|
Pub Dt:
|
08/11/2005
| | | | |
Title:
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LITHOGRAPHIC PROCESS WINDOW OPTIMIZATION UNDER COMPLEX CONSTRAINTS ON EDGE PLACEMENT
|
|
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Patent #:
|
|
Issue Dt:
|
11/09/2010
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Application #:
|
10777576
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Filing Dt:
|
02/12/2004
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Publication #:
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Pub Dt:
|
08/18/2005
| | | | |
Title:
|
VERTICAL CARBON NANOTUBE FIELD EFFECT TRANSISTORS AND ARRAYS
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|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
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Application #:
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10777952
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Filing Dt:
|
02/12/2004
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Publication #:
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Pub Dt:
|
08/18/2005
| | | | |
Title:
|
METHOD AND CIRCUIT FOR INCREASED NOISE IMMUNITY FOR CLOCKING SIGNALS IN HIGH SPEED DIGITAL SYSTEMS
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|
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Patent #:
|
|
Issue Dt:
|
08/07/2007
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Application #:
|
10780341
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Filing Dt:
|
02/17/2004
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Publication #:
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Pub Dt:
|
08/19/2004
| | | | |
Title:
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SYSTEM AND METHOD FOR ABATING THE SIMULTANEOUS FLOW OF SILANE AND ARSINE
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|
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Patent #:
|
|
Issue Dt:
|
09/05/2006
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Application #:
|
10780393
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Filing Dt:
|
02/17/2004
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Publication #:
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Pub Dt:
|
08/19/2004
| | | | |
Title:
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DUAL DOUBLE GATE TRANSISTOR AND METHOD FOR FORMING
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|
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Patent #:
|
|
Issue Dt:
|
08/08/2006
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Application #:
|
10780554
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Filing Dt:
|
02/19/2004
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Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
Title:
|
STRUCTURES AND METHODS FOR INTERGRATION OF ULTRALOW-K DIELECTRICS WITH IMPROVED RELIABILITY
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|
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Patent #:
|
|
Issue Dt:
|
09/13/2005
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Application #:
|
10782808
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Filing Dt:
|
02/23/2004
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Publication #:
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Pub Dt:
|
09/16/2004
| | | | |
Title:
|
SOFT METAL CONDUCTOR AND METHOD OF MAKING
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|
|
Patent #:
|
|
Issue Dt:
|
01/22/2008
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Application #:
|
10782811
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Filing Dt:
|
02/23/2004
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Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
Title:
|
METHOD AND STRUCTURE TO ISOLATE A QUBIT FROM THE ENVIRONMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10782922
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Filing Dt:
|
02/23/2004
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Publication #:
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Pub Dt:
|
08/19/2004
| | | | |
Title:
|
POLISHING PADS WITH POLYMER FILLED FIBROUS WEB, AND METHODS FOR FABRICATING AND USING SAME
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|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10783462
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Filing Dt:
|
02/20/2004
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Publication #:
|
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Pub Dt:
|
08/25/2005
| | | | |
Title:
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METHOD AND STRUCTURE FOR DETERMINING THERMAL CYCLE RELIABILITY
|
|
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Patent #:
|
|
Issue Dt:
|
07/18/2006
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Application #:
|
10783938
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Filing Dt:
|
02/20/2004
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Publication #:
|
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Pub Dt:
|
08/25/2005
| | | | |
Title:
|
FAST MODEL-BASED OPTICAL PROXIMITY CORRECTION
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
10784591
|
Filing Dt:
|
02/23/2004
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Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
Title:
|
Method for fabricating crystalline-dielectric thin films and devices formed using same
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10784593
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Filing Dt:
|
02/23/2004
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Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
Title:
|
METHOD FOR FABRICATING CRYSTALLINE-DIELECTRIC THIN FILMS AND DEVICES FORMED USING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2006
|
Application #:
|
10785894
|
Filing Dt:
|
02/24/2004
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Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
Title:
|
STRUCTURE FOR AND METHOD OF FABRICATING A HIGH-SPEED CMOS-COMPATIBLE GE-ON-INSULATOR PHOTODETECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10786901
|
Filing Dt:
|
02/25/2004
|
Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
Title:
|
CMOS SILICIDE METAL GATE INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2008
|
Application #:
|
10787002
|
Filing Dt:
|
02/25/2004
|
Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
Title:
|
ULTRA-THIN SOI VERTICAL BIPOLAR TRANSISTORS WITH AN INVERSION COLLECTOR ON THIN-BURIED OXIDE (BOX) FOR LOW SUBSTRATE-BIAS OPERATION AND METHODS THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10787471
|
Filing Dt:
|
02/26/2004
|
Publication #:
|
|
Pub Dt:
|
08/26/2004
| | | | |
Title:
|
MODULE WITH ADHESIVELY ATTACHED HEAT SINK
|
|