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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036779/0001   Pages: 985
Recorded: 10/05/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
07/29/2008
Application #:
10873672
Filing Dt:
06/22/2004
Publication #:
Pub Dt:
12/22/2005
Title:
REDUCING POWER CONSUMPTION IN SIGNAL DETECTION
2
Patent #:
Issue Dt:
10/03/2006
Application #:
10873733
Filing Dt:
06/22/2004
Publication #:
Pub Dt:
12/22/2005
Title:
METHOD OF FORMING METAL/HIGH-K GATE STACKS WITH HIGH MOBILITY
3
Patent #:
Issue Dt:
10/09/2007
Application #:
10875699
Filing Dt:
06/24/2004
Publication #:
Pub Dt:
12/29/2005
Title:
COMMON CARRIER
4
Patent #:
Issue Dt:
03/06/2007
Application #:
10875727
Filing Dt:
06/24/2004
Publication #:
Pub Dt:
12/29/2005
Title:
COMPRESSIVE SIGE <110> GROWTH AND STRUCTURE OF MOSFET DEVICES
5
Patent #:
Issue Dt:
07/17/2007
Application #:
10876155
Filing Dt:
06/24/2004
Publication #:
Pub Dt:
12/29/2005
Title:
INTEGRATION OF STRAINED GE INTO ADVANCED CMOS TECHNOLOGY
6
Patent #:
Issue Dt:
04/12/2005
Application #:
10876873
Filing Dt:
06/25/2004
Publication #:
Pub Dt:
12/09/2004
Title:
LOW-GIDL MOSFET STRUCTURE AND METHOD FOR FABRICATION
7
Patent #:
Issue Dt:
04/12/2005
Application #:
10879538
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
01/06/2005
Title:
CMOS PERFORMANCE ENHANCEMENT USING LOCALIZED VOIDS AND EXTENDED DEFECTS
8
Patent #:
Issue Dt:
02/22/2005
Application #:
10879550
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
01/06/2005
Title:
CMOS PERFORMANCE ENHANCEMENT USING LOCALIZED VOIDS AND EXTENDED DEFECTS
9
Patent #:
Issue Dt:
09/19/2006
Application #:
10879815
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
12/29/2005
Title:
HORIZONTAL MEMORY GAIN CELLS
10
Patent #:
Issue Dt:
11/29/2005
Application #:
10879833
Filing Dt:
06/29/2004
Title:
DUAL GATED FINFET GAIN CELL
11
Patent #:
Issue Dt:
09/16/2008
Application #:
10880853
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
METHOD, SYSTEM AND PROGRAM PRODUCT FOR PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING INCOMPLETELY SPECIFIED CONFIGURATION ENTITIES
12
Patent #:
Issue Dt:
02/22/2005
Application #:
10881449
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
12/09/2004
Title:
MOSFET DEVICE WITH IN-SITU DOPED, RAISED SOURCE AND DRAIN STRUCTURES
13
Patent #:
Issue Dt:
03/31/2009
Application #:
10881853
Filing Dt:
06/29/2004
Publication #:
Pub Dt:
12/29/2005
Title:
WEAR GAUGE AND METHOD OF USE
14
Patent #:
Issue Dt:
11/21/2006
Application #:
10883392
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
01/05/2006
Title:
APPARATUS AND METHODS FOR MICROCHANNEL COOLING OF SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGES
15
Patent #:
Issue Dt:
08/01/2006
Application #:
10883434
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
02/03/2005
Title:
SI/SIGE OPTOELECTRONIC INTEGRATED CIRCUITS
16
Patent #:
Issue Dt:
05/15/2007
Application #:
10883443
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
01/05/2006
Title:
STRAINED SI MOSFET ON TENSILE-STRAINED SIGE-ON-INSULATOR (SGOI)
17
Patent #:
Issue Dt:
01/31/2006
Application #:
10883883
Filing Dt:
07/02/2004
Publication #:
Pub Dt:
01/05/2006
Title:
ULTRA-THIN, HIGH QUALITY STRAINED SILICON-ON-INSULATOR FORMED BY ELASTIC STRAIN TRANSFER
18
Patent #:
Issue Dt:
02/06/2007
Application #:
10883887
Filing Dt:
07/02/2004
Publication #:
Pub Dt:
01/05/2006
Title:
STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED P+ SILICON GERMANIUM LAYER
19
Patent #:
Issue Dt:
04/27/2010
Application #:
10885462
Filing Dt:
07/06/2004
Publication #:
Pub Dt:
01/12/2006
Title:
METHODS FOR THE FORMATION OF FULLY SILICIDED METAL GATES
20
Patent #:
Issue Dt:
09/13/2005
Application #:
10885856
Filing Dt:
07/08/2004
Publication #:
Pub Dt:
12/09/2004
Title:
INTERPOSER CAPACITOR BUILT ON SILICON WAFER AND JOINED TO A CERAMIC SUBSTRATE
21
Patent #:
Issue Dt:
03/27/2007
Application #:
10886439
Filing Dt:
07/06/2004
Publication #:
Pub Dt:
03/24/2005
Title:
TRENCH CAPACITOR DRAM CELL USING BURIED OXIDE AS ARRAY TOP OXIDE
22
Patent #:
Issue Dt:
10/10/2006
Application #:
10887087
Filing Dt:
07/09/2004
Publication #:
Pub Dt:
01/12/2006
Title:
COPPER CONDUCTOR
23
Patent #:
Issue Dt:
12/13/2005
Application #:
10887983
Filing Dt:
07/08/2004
Title:
QUASI-STATIC RANDOM ACCESS MEMORY
24
Patent #:
NONE
Issue Dt:
Application #:
10889437
Filing Dt:
07/12/2004
Publication #:
Pub Dt:
01/12/2006
Title:
Processing for overcoming extreme topography
25
Patent #:
Issue Dt:
10/10/2006
Application #:
10890463
Filing Dt:
07/12/2004
Publication #:
Pub Dt:
01/12/2006
Title:
METHOD, SYSTEM AND STORAGE MEDIUM FOR DETERMINING CIRCUIT PLACEMENT
26
Patent #:
Issue Dt:
09/18/2007
Application #:
10890753
Filing Dt:
07/14/2004
Publication #:
Pub Dt:
02/02/2006
Title:
FORMATION OF FULLY SILICIDED METAL GATE USING DUAL SELF-ALIGNED SILICIDE PROCESS
27
Patent #:
NONE
Issue Dt:
Application #:
10890765
Filing Dt:
07/14/2004
Publication #:
Pub Dt:
01/19/2006
Title:
Ion implantation for suppression of defects in annealed SiGe layers
28
Patent #:
NONE
Issue Dt:
Application #:
10891605
Filing Dt:
07/15/2004
Publication #:
Pub Dt:
01/19/2006
Title:
Reliability of low-k dielectric devices with energy dissipative layer
29
Patent #:
Issue Dt:
03/25/2008
Application #:
10892211
Filing Dt:
07/16/2004
Publication #:
Pub Dt:
01/19/2006
Title:
METHOD AND SYSTEM FOR REAL-TIME ESTIMATION AND PREDICTION OF THE THERMAL STATE OF A MICROPROCESSOR UNIT
30
Patent #:
Issue Dt:
09/05/2006
Application #:
10892467
Filing Dt:
07/15/2004
Publication #:
Pub Dt:
01/19/2006
Title:
STRAINED SEMICONDUCTOR DEVICE STRUCTURES
31
Patent #:
Issue Dt:
07/11/2006
Application #:
10894219
Filing Dt:
07/19/2004
Publication #:
Pub Dt:
12/30/2004
Title:
ELEVATED SOURCE DRAIN DISPOSABLE SPACER CMOS
32
Patent #:
NONE
Issue Dt:
Application #:
10894750
Filing Dt:
07/19/2004
Publication #:
Pub Dt:
12/23/2004
Title:
Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors
33
Patent #:
NONE
Issue Dt:
Application #:
10896495
Filing Dt:
07/22/2004
Publication #:
Pub Dt:
02/09/2006
Title:
Clustering-based multilevel quadratic placement
34
Patent #:
Issue Dt:
10/31/2006
Application #:
10896504
Filing Dt:
07/22/2004
Publication #:
Pub Dt:
02/16/2006
Title:
METHOD AND APPARATUS FOR MINIMIZING THRESHOLD VARIATION FROM BODY CHARGE IN SILICON-ON-INSULATOR CIRCUITRY
35
Patent #:
NONE
Issue Dt:
Application #:
10896547
Filing Dt:
07/22/2004
Publication #:
Pub Dt:
12/23/2004
Title:
Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts
36
Patent #:
Issue Dt:
02/17/2009
Application #:
10896812
Filing Dt:
07/22/2004
Publication #:
Pub Dt:
01/06/2005
Title:
CONTROL OF BURIED OXIDE IN SIMOX
37
Patent #:
Issue Dt:
06/06/2006
Application #:
10897456
Filing Dt:
07/23/2004
Publication #:
Pub Dt:
01/06/2005
Title:
LIQUID CRYSTAL STRUCTURE WITH IMPROVED BLACK STATE, AND PROJECTOR USING SAME
38
Patent #:
Issue Dt:
02/13/2007
Application #:
10899768
Filing Dt:
07/27/2004
Publication #:
Pub Dt:
02/02/2006
Title:
TEMPERATURE SENSOR FOR HIGH POWER VERY LARGE SCALE INTEGRATION CIRCUITS
39
Patent #:
Issue Dt:
10/02/2007
Application #:
10899937
Filing Dt:
07/27/2004
Publication #:
Pub Dt:
02/02/2006
Title:
DRAM ACCESS COMMAND QUEUING STRUCTURE
40
Patent #:
Issue Dt:
07/03/2007
Application #:
10900487
Filing Dt:
07/28/2004
Publication #:
Pub Dt:
01/13/2005
Title:
TUNNELING MAGNETORESISTIVE (TMR) SENSOR HAVING A MAGNESIUM OXIDE BARRIER LAYER FORMED BY A MULTI-LAYER PROCESS
41
Patent #:
Issue Dt:
06/27/2006
Application #:
10900523
Filing Dt:
07/28/2004
Publication #:
Pub Dt:
01/13/2005
Title:
SILICON-ON-INSULATOR (SOI) INTEGRATED CIRCUIT (IC) CHIP WITH THE SILICON LAYERS CONSISTING OF REGIONS OF DIFFERENT THICKNESS
42
Patent #:
Issue Dt:
10/03/2006
Application #:
10900733
Filing Dt:
07/28/2004
Publication #:
Pub Dt:
02/02/2006
Title:
INTEGRATED SPECTRUM ANALYZER CIRCUITS AND METHODS FOR PROVIDING ON-CHIP DIAGNOSTICS
43
Patent #:
Issue Dt:
10/31/2006
Application #:
10901858
Filing Dt:
07/29/2004
Publication #:
Pub Dt:
02/02/2006
Title:
INTEGRATED CIRCUIT CHIP UTILIZING ORIENTED CARBON NANOTUBE CONDUCTIVE LAYERS
44
Patent #:
Issue Dt:
11/14/2006
Application #:
10901868
Filing Dt:
07/29/2004
Publication #:
Pub Dt:
02/03/2005
Title:
RELIABLE LOW-K INTERCONNECT STRUCTURE WITH HYBRID DIELECTRIC
45
Patent #:
Issue Dt:
04/27/2010
Application #:
10902601
Filing Dt:
07/30/2004
Publication #:
Pub Dt:
02/02/2006
Title:
AUTONOMIC CLIENT MIGRATION SYSTEM FOR SERVICE ENGAGEMENTS
46
Patent #:
Issue Dt:
05/29/2007
Application #:
10902653
Filing Dt:
07/28/2004
Publication #:
Pub Dt:
02/02/2006
Title:
ESD DISSIPATIVE COATING ON CABLES
47
Patent #:
NONE
Issue Dt:
Application #:
10903365
Filing Dt:
07/30/2004
Publication #:
Pub Dt:
02/02/2006
Title:
Prevention and control of intermetallic alloy inclusions that form during reflow of Pb free, Sn rich, solders in contacts in microelectronic packaging in integrated circuit contact structures where electroless Ni(P) metallization is present
48
Patent #:
Issue Dt:
07/31/2007
Application #:
10904056
Filing Dt:
10/21/2004
Publication #:
Pub Dt:
04/27/2006
Title:
SIMULATION TESTING OF DIGITAL LOGIC CIRCUIT DESIGNS
49
Patent #:
Issue Dt:
08/29/2006
Application #:
10904059
Filing Dt:
10/21/2004
Publication #:
Pub Dt:
05/11/2006
Title:
STRUCTURE FOR STRAINED CHANNEL FIELD EFFECT TRANSISTOR PAIR HAVING A MEMBER AND A CONTACT VIA
50
Patent #:
Issue Dt:
09/05/2006
Application #:
10904060
Filing Dt:
10/21/2004
Publication #:
Pub Dt:
05/11/2006
Title:
STRUCTURE FOR STRAINED CHANNEL FIELD EFFECT TRANSISTOR PAIR HAVING UNDERLAPPED DUAL LINERS
51
Patent #:
Issue Dt:
02/07/2006
Application #:
10904200
Filing Dt:
10/28/2004
Title:
IRRADIATION ASSISTED REACTIVE ION ETCHING
52
Patent #:
Issue Dt:
11/27/2007
Application #:
10904225
Filing Dt:
10/29/2004
Publication #:
Pub Dt:
05/11/2006
Title:
TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS
53
Patent #:
NONE
Issue Dt:
Application #:
10904262
Filing Dt:
11/01/2004
Publication #:
Pub Dt:
05/19/2005
Title:
SLURRY AND USE THEREOF FOR POLISHING
54
Patent #:
Issue Dt:
12/29/2009
Application #:
10904307
Filing Dt:
11/03/2004
Publication #:
Pub Dt:
05/11/2006
Title:
CIRCUIT STATISTICAL MODELING FOR PARTIALLY CORRELATED MODEL PARAMETERS
55
Patent #:
Issue Dt:
07/15/2008
Application #:
10904309
Filing Dt:
11/03/2004
Publication #:
Pub Dt:
05/11/2006
Title:
SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS
56
Patent #:
Issue Dt:
04/01/2008
Application #:
10904323
Filing Dt:
11/04/2004
Publication #:
Pub Dt:
05/04/2006
Title:
MULTIPLE LAYER RESIST SCHEME IMPLEMENTING ETCH RECIPE PARTICULAR TO EACH LAYER
57
Patent #:
Issue Dt:
03/25/2008
Application #:
10904355
Filing Dt:
11/05/2004
Publication #:
Pub Dt:
05/11/2006
Title:
METHOD FOR IMPROVING OPTICAL PROXIMITY CORRECTION
58
Patent #:
Issue Dt:
06/13/2006
Application #:
10904356
Filing Dt:
11/05/2004
Publication #:
Pub Dt:
03/31/2005
Title:
IN-SITU PELLICLE MONITOR
59
Patent #:
Issue Dt:
09/25/2007
Application #:
10904357
Filing Dt:
11/05/2004
Publication #:
Pub Dt:
05/11/2006
Title:
FIN DEVICE WITH CAPACITOR INTEGRATED UNDER GATE ELECTRODE
60
Patent #:
Issue Dt:
06/12/2007
Application #:
10904391
Filing Dt:
11/08/2004
Publication #:
Pub Dt:
05/11/2006
Title:
SELF-ALIGNED LOW-K GATE CAP
61
Patent #:
Issue Dt:
08/14/2007
Application #:
10904397
Filing Dt:
11/08/2004
Publication #:
Pub Dt:
05/11/2006
Title:
METHOD AND APPARATUS FOR CONVERTING GLOBALLY CLOCK-GATED CIRCUITS TO LOCALLY CLOCK-GATED CIRCUITS
62
Patent #:
Issue Dt:
09/26/2006
Application #:
10904435
Filing Dt:
11/10/2004
Publication #:
Pub Dt:
05/11/2006
Title:
APPARATUS AND METHOD FOR SINGLE DIE BACKSIDE PROBING OF SEMICONDUCTOR DEVICES
63
Patent #:
Issue Dt:
10/30/2007
Application #:
10904437
Filing Dt:
11/10/2004
Publication #:
Pub Dt:
05/11/2006
Title:
BIPOLAR TRANSISTOR WITH SELF-ALIGNED RETROGRADE EXTRINSIC BASE IMPLANT PROFILE AND SELF-ALIGNED SILICIDE
64
Patent #:
Issue Dt:
10/10/2006
Application #:
10904438
Filing Dt:
11/10/2004
Publication #:
Pub Dt:
05/11/2006
Title:
IMPROVED ION DETECTOR FOR IONBEAM APPLICATIONS
65
Patent #:
Issue Dt:
09/12/2006
Application #:
10904460
Filing Dt:
11/11/2004
Publication #:
Pub Dt:
05/11/2006
Title:
CIRCUIT AND METHOD OF CONTROLLING INTEGRATED CIRCUIT POWER CONSUMPTION USING PHASE CHANGE SWITCHES
66
Patent #:
Issue Dt:
01/15/2008
Application #:
10904528
Filing Dt:
11/15/2004
Publication #:
Pub Dt:
05/18/2006
Title:
STRUCTURE AND METHOD FOR ACCURATE DEEP TRENCH RESISTANCE MEASUREMENT
67
Patent #:
Issue Dt:
07/18/2006
Application #:
10904555
Filing Dt:
11/16/2004
Publication #:
Pub Dt:
05/18/2006
Title:
FLUIDIC COOLING SYSTEMS AND METHODS FOR ELECTRONIC COMPONENTS
68
Patent #:
Issue Dt:
10/17/2006
Application #:
10904582
Filing Dt:
11/17/2004
Publication #:
Pub Dt:
05/18/2006
Title:
METHOD OF FABRICATING A BOTTLE TRENCH AND A BOTTLE TRENCH CAPACITOR
69
Patent #:
Issue Dt:
04/22/2008
Application #:
10904601
Filing Dt:
11/18/2004
Publication #:
Pub Dt:
05/18/2006
Title:
METHOD AND APPARATUS FOR CLEANING A SEMICONDUCTOR SUBSTRATE IN AN IMMERSION LITHOGRAPHY SYSTEM
70
Patent #:
NONE
Issue Dt:
Application #:
10904660
Filing Dt:
11/22/2004
Publication #:
Pub Dt:
05/25/2006
Title:
Lowered Source/Drain Transistors
71
Patent #:
Issue Dt:
09/19/2006
Application #:
10904680
Filing Dt:
11/23/2004
Publication #:
Pub Dt:
05/25/2006
Title:
DENDRITE GROWTH CONTROL CIRCUIT
72
Patent #:
Issue Dt:
07/10/2007
Application #:
10904681
Filing Dt:
11/23/2004
Publication #:
Pub Dt:
05/25/2006
Title:
AN ELECTRICALLY PROGRAMMABLE FUSE FOR SILICON-ON-INSULATOR (SOI) TECHNOLOGY
73
Patent #:
Issue Dt:
03/20/2007
Application #:
10904808
Filing Dt:
11/30/2004
Publication #:
Pub Dt:
06/01/2006
Title:
STRUCTURE AND METHOD OF APPLYING STRESSES TO PFET AND NFET TRANSISTOR CHANNELS FOR IMPROVED PERFORMANCE
74
Patent #:
Issue Dt:
11/21/2006
Application #:
10904827
Filing Dt:
12/01/2004
Publication #:
Pub Dt:
06/01/2006
Title:
IMPROVED HDP-BASED ILD CAPPING LAYER
75
Patent #:
Issue Dt:
06/20/2006
Application #:
10904884
Filing Dt:
12/02/2004
Publication #:
Pub Dt:
06/08/2006
Title:
METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES
76
Patent #:
Issue Dt:
07/03/2007
Application #:
10904950
Filing Dt:
12/07/2004
Publication #:
Pub Dt:
06/08/2006
Title:
METHOD, SYSTEM AND PROGRAM PRODUCT FOR EVALUATING A CIRCUIT
77
Patent #:
Issue Dt:
11/07/2006
Application #:
10905002
Filing Dt:
12/09/2004
Publication #:
Pub Dt:
06/15/2006
Title:
SOI DEVICE WITH DIFFERENT CRYSTALLOGRAPHIC ORIENTATIONS
78
Patent #:
Issue Dt:
08/14/2007
Application #:
10905008
Filing Dt:
12/09/2004
Publication #:
Pub Dt:
05/11/2006
Title:
TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS
79
Patent #:
Issue Dt:
12/11/2007
Application #:
10905024
Filing Dt:
12/10/2004
Publication #:
Pub Dt:
06/15/2006
Title:
METHOD FOR FORMING DUAL ETCH STOP LINER AND PROTECTIVE LAYER IN A SEMICONDUCTOR DEVICE
80
Patent #:
Issue Dt:
03/25/2008
Application #:
10905025
Filing Dt:
12/10/2004
Publication #:
Pub Dt:
06/15/2006
Title:
DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS
81
Patent #:
Issue Dt:
11/04/2008
Application #:
10905027
Filing Dt:
12/10/2004
Publication #:
Pub Dt:
06/15/2006
Title:
DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND RELATED METHODS
82
Patent #:
Issue Dt:
07/08/2008
Application #:
10905041
Filing Dt:
12/13/2004
Publication #:
Pub Dt:
06/15/2006
Title:
SIDEWALL SEMICONDUCTOR TRANSISTORS
83
Patent #:
Issue Dt:
08/28/2007
Application #:
10905062
Filing Dt:
12/14/2004
Publication #:
Pub Dt:
06/15/2006
Title:
DUAL STRESSED SOI SUBSTRATES
84
Patent #:
Issue Dt:
02/05/2008
Application #:
10905068
Filing Dt:
12/14/2004
Publication #:
Pub Dt:
04/14/2005
Title:
METHOD FOR FORMING DAMASCENE STRUCTURE UTILIZING PLANARIZING MATERIAL COUPLED WITH COMPRESSIVE DIFFUSION BARRIER MATERIAL
85
Patent #:
Issue Dt:
03/20/2007
Application #:
10905094
Filing Dt:
12/15/2004
Publication #:
Pub Dt:
06/15/2006
Title:
LOW-COST DEEP TRENCH DECOUPLING CAPACITOR DEVICE AND PROCESS OF MANUFACTURE
86
Patent #:
Issue Dt:
08/07/2007
Application #:
10905230
Filing Dt:
12/22/2004
Publication #:
Pub Dt:
06/22/2006
Title:
MANUFACTURABLE COWP METAL CAP PROCESS FOR COPPER INTERCONNECTS
87
Patent #:
Issue Dt:
09/11/2007
Application #:
10905474
Filing Dt:
01/06/2005
Publication #:
Pub Dt:
07/06/2006
Title:
CIRCUIT ELEMENT FUNCTION MATCHING DESPITE AUTO-GENERATED DUMMY SHAPES
88
Patent #:
Issue Dt:
01/13/2009
Application #:
10905475
Filing Dt:
01/06/2005
Publication #:
Pub Dt:
07/06/2006
Title:
ERASABLE NONVOLATILE MEMORY WITH SIDEWALL STORAGE
89
Patent #:
Issue Dt:
10/30/2007
Application #:
10905480
Filing Dt:
01/06/2005
Publication #:
Pub Dt:
07/06/2006
Title:
ON-CHIP SIGNAL TRANSFORMER FOR GROUND NOISE ISOLATION
90
Patent #:
Issue Dt:
04/14/2009
Application #:
10905486
Filing Dt:
01/06/2005
Publication #:
Pub Dt:
07/06/2006
Title:
ONE MASK HYPERABRUPT JUNCTION VARACTOR USING A COMPENSATED CATHODE CONTACT
91
Patent #:
Issue Dt:
09/18/2007
Application #:
10905586
Filing Dt:
01/12/2005
Publication #:
Pub Dt:
07/13/2006
Title:
TRANSISTOR STRUCTURE HAVING STRESSED REGIONS OF OPPOSITE TYPES UNDERLYING CHANNEL AND SOURCE/DRAIN REGIONS
92
Patent #:
Issue Dt:
04/27/2010
Application #:
10905587
Filing Dt:
09/12/2005
Publication #:
Pub Dt:
03/15/2007
Title:
SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE
93
Patent #:
Issue Dt:
09/25/2007
Application #:
10905589
Filing Dt:
01/12/2005
Publication #:
Pub Dt:
07/13/2006
Title:
ENHANCED PFET USING SHEAR STRESS
94
Patent #:
Issue Dt:
03/18/2008
Application #:
10905590
Filing Dt:
01/12/2005
Publication #:
Pub Dt:
07/13/2006
Title:
WIRING PATTERNS FORMED BY SELECTIVE METAL PLATING
95
Patent #:
NONE
Issue Dt:
Application #:
10905595
Filing Dt:
01/12/2005
Publication #:
Pub Dt:
07/13/2006
Title:
LOW CONCENTRATION SiGe BUFFER DURING STRAINED Si GROWTH OF SSGOI MATERIAL FOR DOPANT DIFFUSION CONTROL AND DEFECT REDUCTION
96
Patent #:
Issue Dt:
05/23/2006
Application #:
10905643
Filing Dt:
01/14/2005
Title:
METHOD AND DEVICE FOR HEAT DISSIPATION IN SEMICONDUCTOR MODULES
97
Patent #:
Issue Dt:
08/29/2006
Application #:
10905682
Filing Dt:
01/17/2005
Publication #:
Pub Dt:
07/20/2006
Title:
LOW TRIGGER VOLTAGE, LOW LEAKAGE ESD NFET
98
Patent #:
Issue Dt:
12/26/2006
Application #:
10905684
Filing Dt:
01/17/2005
Publication #:
Pub Dt:
07/20/2006
Title:
SELF-ALIGNED, SILICIDED, TRENCH-BASED, DRAM/EDRAM PROCESSES WITH IMPROVED RETENTION
99
Patent #:
Issue Dt:
09/05/2006
Application #:
10905704
Filing Dt:
01/18/2005
Publication #:
Pub Dt:
07/20/2006
Title:
IMPROVED SIGNAL DETECTOR FOR HIGH-SPEED SERDES
100
Patent #:
Issue Dt:
04/08/2008
Application #:
10905816
Filing Dt:
01/21/2005
Publication #:
Pub Dt:
07/27/2006
Title:
DETECTION OF DIAMOND CONTAMINATION IN POLISHING PAD
Assignors
1
Exec Dt:
09/10/2015
2
Exec Dt:
09/10/2015
Assignee
1
PO BOX 309
UGLAND HOUSE
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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