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Patent #:
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|
Issue Dt:
|
07/29/2008
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Application #:
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10873672
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Filing Dt:
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06/22/2004
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Publication #:
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Pub Dt:
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12/22/2005
| | | | |
Title:
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REDUCING POWER CONSUMPTION IN SIGNAL DETECTION
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10873733
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Filing Dt:
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06/22/2004
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Publication #:
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Pub Dt:
|
12/22/2005
| | | | |
Title:
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METHOD OF FORMING METAL/HIGH-K GATE STACKS WITH HIGH MOBILITY
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Patent #:
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Issue Dt:
|
10/09/2007
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Application #:
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10875699
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Filing Dt:
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06/24/2004
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Publication #:
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Pub Dt:
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12/29/2005
| | | | |
Title:
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COMMON CARRIER
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Patent #:
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Issue Dt:
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03/06/2007
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Application #:
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10875727
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Filing Dt:
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06/24/2004
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Publication #:
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Pub Dt:
|
12/29/2005
| | | | |
Title:
|
COMPRESSIVE SIGE <110> GROWTH AND STRUCTURE OF MOSFET DEVICES
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Patent #:
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Issue Dt:
|
07/17/2007
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Application #:
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10876155
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Filing Dt:
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06/24/2004
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Publication #:
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|
Pub Dt:
|
12/29/2005
| | | | |
Title:
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INTEGRATION OF STRAINED GE INTO ADVANCED CMOS TECHNOLOGY
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Patent #:
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Issue Dt:
|
04/12/2005
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Application #:
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10876873
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Filing Dt:
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06/25/2004
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Publication #:
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Pub Dt:
|
12/09/2004
| | | | |
Title:
|
LOW-GIDL MOSFET STRUCTURE AND METHOD FOR FABRICATION
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Patent #:
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Issue Dt:
|
04/12/2005
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Application #:
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10879538
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Filing Dt:
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06/29/2004
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Publication #:
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Pub Dt:
|
01/06/2005
| | | | |
Title:
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CMOS PERFORMANCE ENHANCEMENT USING LOCALIZED VOIDS AND EXTENDED DEFECTS
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Patent #:
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Issue Dt:
|
02/22/2005
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Application #:
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10879550
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Filing Dt:
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06/29/2004
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Publication #:
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|
Pub Dt:
|
01/06/2005
| | | | |
Title:
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CMOS PERFORMANCE ENHANCEMENT USING LOCALIZED VOIDS AND EXTENDED DEFECTS
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Patent #:
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Issue Dt:
|
09/19/2006
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Application #:
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10879815
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Filing Dt:
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06/29/2004
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Publication #:
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Pub Dt:
|
12/29/2005
| | | | |
Title:
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HORIZONTAL MEMORY GAIN CELLS
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Patent #:
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|
Issue Dt:
|
11/29/2005
|
Application #:
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10879833
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Filing Dt:
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06/29/2004
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Title:
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DUAL GATED FINFET GAIN CELL
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Patent #:
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Issue Dt:
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09/16/2008
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Application #:
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10880853
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Filing Dt:
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06/30/2004
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Publication #:
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Pub Dt:
|
01/05/2006
| | | | |
Title:
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METHOD, SYSTEM AND PROGRAM PRODUCT FOR PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING INCOMPLETELY SPECIFIED CONFIGURATION ENTITIES
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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10881449
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Filing Dt:
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06/30/2004
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Publication #:
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Pub Dt:
|
12/09/2004
| | | | |
Title:
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MOSFET DEVICE WITH IN-SITU DOPED, RAISED SOURCE AND DRAIN STRUCTURES
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Patent #:
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Issue Dt:
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03/31/2009
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Application #:
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10881853
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Filing Dt:
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06/29/2004
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Publication #:
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Pub Dt:
|
12/29/2005
| | | | |
Title:
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WEAR GAUGE AND METHOD OF USE
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Patent #:
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Issue Dt:
|
11/21/2006
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Application #:
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10883392
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Filing Dt:
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07/01/2004
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Publication #:
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Pub Dt:
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01/05/2006
| | | | |
Title:
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APPARATUS AND METHODS FOR MICROCHANNEL COOLING OF SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGES
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Patent #:
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Issue Dt:
|
08/01/2006
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Application #:
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10883434
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Filing Dt:
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07/01/2004
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Publication #:
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Pub Dt:
|
02/03/2005
| | | | |
Title:
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SI/SIGE OPTOELECTRONIC INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
05/15/2007
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Application #:
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10883443
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Filing Dt:
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07/01/2004
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Publication #:
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Pub Dt:
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01/05/2006
| | | | |
Title:
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STRAINED SI MOSFET ON TENSILE-STRAINED SIGE-ON-INSULATOR (SGOI)
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Patent #:
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Issue Dt:
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01/31/2006
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Application #:
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10883883
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Filing Dt:
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07/02/2004
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Publication #:
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Pub Dt:
|
01/05/2006
| | | | |
Title:
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ULTRA-THIN, HIGH QUALITY STRAINED SILICON-ON-INSULATOR FORMED BY ELASTIC STRAIN TRANSFER
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Patent #:
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Issue Dt:
|
02/06/2007
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Application #:
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10883887
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Filing Dt:
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07/02/2004
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Publication #:
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Pub Dt:
|
01/05/2006
| | | | |
Title:
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STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED P+ SILICON GERMANIUM LAYER
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Patent #:
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Issue Dt:
|
04/27/2010
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Application #:
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10885462
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Filing Dt:
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07/06/2004
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Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
Title:
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METHODS FOR THE FORMATION OF FULLY SILICIDED METAL GATES
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10885856
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Filing Dt:
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07/08/2004
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Publication #:
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Pub Dt:
|
12/09/2004
| | | | |
Title:
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INTERPOSER CAPACITOR BUILT ON SILICON WAFER AND JOINED TO A CERAMIC SUBSTRATE
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Patent #:
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Issue Dt:
|
03/27/2007
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Application #:
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10886439
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Filing Dt:
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07/06/2004
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Publication #:
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Pub Dt:
|
03/24/2005
| | | | |
Title:
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TRENCH CAPACITOR DRAM CELL USING BURIED OXIDE AS ARRAY TOP OXIDE
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Patent #:
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Issue Dt:
|
10/10/2006
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Application #:
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10887087
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Filing Dt:
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07/09/2004
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Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
Title:
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COPPER CONDUCTOR
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Patent #:
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Issue Dt:
|
12/13/2005
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Application #:
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10887983
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Filing Dt:
|
07/08/2004
|
Title:
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QUASI-STATIC RANDOM ACCESS MEMORY
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10889437
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Filing Dt:
|
07/12/2004
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Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
Title:
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Processing for overcoming extreme topography
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Patent #:
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Issue Dt:
|
10/10/2006
|
Application #:
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10890463
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Filing Dt:
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07/12/2004
|
Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
Title:
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METHOD, SYSTEM AND STORAGE MEDIUM FOR DETERMINING CIRCUIT PLACEMENT
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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10890753
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Filing Dt:
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07/14/2004
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Publication #:
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Pub Dt:
|
02/02/2006
| | | | |
Title:
|
FORMATION OF FULLY SILICIDED METAL GATE USING DUAL SELF-ALIGNED SILICIDE PROCESS
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
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10890765
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Filing Dt:
|
07/14/2004
|
Publication #:
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|
Pub Dt:
|
01/19/2006
| | | | |
Title:
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Ion implantation for suppression of defects in annealed SiGe layers
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|
Patent #:
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NONE
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Issue Dt:
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Application #:
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10891605
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Filing Dt:
|
07/15/2004
|
Publication #:
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Pub Dt:
|
01/19/2006
| | | | |
Title:
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Reliability of low-k dielectric devices with energy dissipative layer
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|
Patent #:
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Issue Dt:
|
03/25/2008
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Application #:
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10892211
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Filing Dt:
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07/16/2004
|
Publication #:
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Pub Dt:
|
01/19/2006
| | | | |
Title:
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METHOD AND SYSTEM FOR REAL-TIME ESTIMATION AND PREDICTION OF THE THERMAL STATE OF A MICROPROCESSOR UNIT
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Patent #:
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Issue Dt:
|
09/05/2006
|
Application #:
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10892467
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Filing Dt:
|
07/15/2004
|
Publication #:
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Pub Dt:
|
01/19/2006
| | | | |
Title:
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STRAINED SEMICONDUCTOR DEVICE STRUCTURES
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Patent #:
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Issue Dt:
|
07/11/2006
|
Application #:
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10894219
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Filing Dt:
|
07/19/2004
|
Publication #:
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Pub Dt:
|
12/30/2004
| | | | |
Title:
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ELEVATED SOURCE DRAIN DISPOSABLE SPACER CMOS
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
10894750
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Filing Dt:
|
07/19/2004
|
Publication #:
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Pub Dt:
|
12/23/2004
| | | | |
Title:
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Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
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10896495
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Filing Dt:
|
07/22/2004
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Publication #:
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Pub Dt:
|
02/09/2006
| | | | |
Title:
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Clustering-based multilevel quadratic placement
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|
Patent #:
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|
Issue Dt:
|
10/31/2006
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Application #:
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10896504
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Filing Dt:
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07/22/2004
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Publication #:
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Pub Dt:
|
02/16/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR MINIMIZING THRESHOLD VARIATION FROM BODY CHARGE IN SILICON-ON-INSULATOR CIRCUITRY
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
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10896547
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Filing Dt:
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07/22/2004
|
Publication #:
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|
Pub Dt:
|
12/23/2004
| | | | |
Title:
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Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts
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Patent #:
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Issue Dt:
|
02/17/2009
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Application #:
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10896812
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Filing Dt:
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07/22/2004
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Publication #:
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Pub Dt:
|
01/06/2005
| | | | |
Title:
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CONTROL OF BURIED OXIDE IN SIMOX
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|
Patent #:
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|
Issue Dt:
|
06/06/2006
|
Application #:
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10897456
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Filing Dt:
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07/23/2004
|
Publication #:
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|
Pub Dt:
|
01/06/2005
| | | | |
Title:
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LIQUID CRYSTAL STRUCTURE WITH IMPROVED BLACK STATE, AND PROJECTOR USING SAME
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Patent #:
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Issue Dt:
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02/13/2007
|
Application #:
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10899768
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Filing Dt:
|
07/27/2004
|
Publication #:
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|
Pub Dt:
|
02/02/2006
| | | | |
Title:
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TEMPERATURE SENSOR FOR HIGH POWER VERY LARGE SCALE INTEGRATION CIRCUITS
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|
Patent #:
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|
Issue Dt:
|
10/02/2007
|
Application #:
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10899937
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Filing Dt:
|
07/27/2004
|
Publication #:
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|
Pub Dt:
|
02/02/2006
| | | | |
Title:
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DRAM ACCESS COMMAND QUEUING STRUCTURE
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|
Patent #:
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|
Issue Dt:
|
07/03/2007
|
Application #:
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10900487
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Filing Dt:
|
07/28/2004
|
Publication #:
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|
Pub Dt:
|
01/13/2005
| | | | |
Title:
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TUNNELING MAGNETORESISTIVE (TMR) SENSOR HAVING A MAGNESIUM OXIDE BARRIER LAYER FORMED BY A MULTI-LAYER PROCESS
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Patent #:
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|
Issue Dt:
|
06/27/2006
|
Application #:
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10900523
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Filing Dt:
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07/28/2004
|
Publication #:
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|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
SILICON-ON-INSULATOR (SOI) INTEGRATED CIRCUIT (IC) CHIP WITH THE SILICON LAYERS CONSISTING OF REGIONS OF DIFFERENT THICKNESS
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Patent #:
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|
Issue Dt:
|
10/03/2006
|
Application #:
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10900733
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Filing Dt:
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07/28/2004
|
Publication #:
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|
Pub Dt:
|
02/02/2006
| | | | |
Title:
|
INTEGRATED SPECTRUM ANALYZER CIRCUITS AND METHODS FOR PROVIDING ON-CHIP DIAGNOSTICS
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|
Patent #:
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|
Issue Dt:
|
10/31/2006
|
Application #:
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10901858
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Filing Dt:
|
07/29/2004
|
Publication #:
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|
Pub Dt:
|
02/02/2006
| | | | |
Title:
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INTEGRATED CIRCUIT CHIP UTILIZING ORIENTED CARBON NANOTUBE CONDUCTIVE LAYERS
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|
Patent #:
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Issue Dt:
|
11/14/2006
|
Application #:
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10901868
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Filing Dt:
|
07/29/2004
|
Publication #:
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|
Pub Dt:
|
02/03/2005
| | | | |
Title:
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RELIABLE LOW-K INTERCONNECT STRUCTURE WITH HYBRID DIELECTRIC
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|
Patent #:
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|
Issue Dt:
|
04/27/2010
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Application #:
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10902601
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Filing Dt:
|
07/30/2004
|
Publication #:
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Pub Dt:
|
02/02/2006
| | | | |
Title:
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AUTONOMIC CLIENT MIGRATION SYSTEM FOR SERVICE ENGAGEMENTS
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Patent #:
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Issue Dt:
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05/29/2007
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Application #:
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10902653
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Filing Dt:
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07/28/2004
|
Publication #:
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|
Pub Dt:
|
02/02/2006
| | | | |
Title:
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ESD DISSIPATIVE COATING ON CABLES
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|
|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
10903365
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Filing Dt:
|
07/30/2004
|
Publication #:
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|
Pub Dt:
|
02/02/2006
| | | | |
Title:
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Prevention and control of intermetallic alloy inclusions that form during reflow of Pb free, Sn rich, solders in contacts in microelectronic packaging in integrated circuit contact structures where electroless Ni(P) metallization is present
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Patent #:
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|
Issue Dt:
|
07/31/2007
|
Application #:
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10904056
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Filing Dt:
|
10/21/2004
|
Publication #:
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|
Pub Dt:
|
04/27/2006
| | | | |
Title:
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SIMULATION TESTING OF DIGITAL LOGIC CIRCUIT DESIGNS
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|
Patent #:
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|
Issue Dt:
|
08/29/2006
|
Application #:
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10904059
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Filing Dt:
|
10/21/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
STRUCTURE FOR STRAINED CHANNEL FIELD EFFECT TRANSISTOR PAIR HAVING A MEMBER AND A CONTACT VIA
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|
Patent #:
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|
Issue Dt:
|
09/05/2006
|
Application #:
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10904060
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Filing Dt:
|
10/21/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
STRUCTURE FOR STRAINED CHANNEL FIELD EFFECT TRANSISTOR PAIR HAVING UNDERLAPPED DUAL LINERS
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|
|
Patent #:
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|
Issue Dt:
|
02/07/2006
|
Application #:
|
10904200
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Filing Dt:
|
10/28/2004
|
Title:
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IRRADIATION ASSISTED REACTIVE ION ETCHING
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|
Patent #:
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|
Issue Dt:
|
11/27/2007
|
Application #:
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10904225
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Filing Dt:
|
10/29/2004
|
Publication #:
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|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
10904262
|
Filing Dt:
|
11/01/2004
|
Publication #:
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|
Pub Dt:
|
05/19/2005
| | | | |
Title:
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SLURRY AND USE THEREOF FOR POLISHING
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|
Patent #:
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|
Issue Dt:
|
12/29/2009
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Application #:
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10904307
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Filing Dt:
|
11/03/2004
|
Publication #:
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|
Pub Dt:
|
05/11/2006
| | | | |
Title:
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CIRCUIT STATISTICAL MODELING FOR PARTIALLY CORRELATED MODEL PARAMETERS
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|
Patent #:
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|
Issue Dt:
|
07/15/2008
|
Application #:
|
10904309
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Filing Dt:
|
11/03/2004
|
Publication #:
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|
Pub Dt:
|
05/11/2006
| | | | |
Title:
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SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS
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|
|
Patent #:
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|
Issue Dt:
|
04/01/2008
|
Application #:
|
10904323
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Filing Dt:
|
11/04/2004
|
Publication #:
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|
Pub Dt:
|
05/04/2006
| | | | |
Title:
|
MULTIPLE LAYER RESIST SCHEME IMPLEMENTING ETCH RECIPE PARTICULAR TO EACH LAYER
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|
|
Patent #:
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|
Issue Dt:
|
03/25/2008
|
Application #:
|
10904355
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Filing Dt:
|
11/05/2004
|
Publication #:
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|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
METHOD FOR IMPROVING OPTICAL PROXIMITY CORRECTION
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|
Patent #:
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|
Issue Dt:
|
06/13/2006
|
Application #:
|
10904356
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Filing Dt:
|
11/05/2004
|
Publication #:
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|
Pub Dt:
|
03/31/2005
| | | | |
Title:
|
IN-SITU PELLICLE MONITOR
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|
|
Patent #:
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|
Issue Dt:
|
09/25/2007
|
Application #:
|
10904357
|
Filing Dt:
|
11/05/2004
|
Publication #:
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|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
FIN DEVICE WITH CAPACITOR INTEGRATED UNDER GATE ELECTRODE
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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10904391
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Filing Dt:
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11/08/2004
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Publication #:
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Pub Dt:
|
05/11/2006
| | | | |
Title:
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SELF-ALIGNED LOW-K GATE CAP
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Patent #:
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Issue Dt:
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08/14/2007
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Application #:
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10904397
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Filing Dt:
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11/08/2004
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Publication #:
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Pub Dt:
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05/11/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR CONVERTING GLOBALLY CLOCK-GATED CIRCUITS TO LOCALLY CLOCK-GATED CIRCUITS
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Patent #:
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Issue Dt:
|
09/26/2006
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Application #:
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10904435
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Filing Dt:
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11/10/2004
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Publication #:
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Pub Dt:
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05/11/2006
| | | | |
Title:
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APPARATUS AND METHOD FOR SINGLE DIE BACKSIDE PROBING OF SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
10/30/2007
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Application #:
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10904437
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Filing Dt:
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11/10/2004
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Publication #:
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Pub Dt:
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05/11/2006
| | | | |
Title:
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BIPOLAR TRANSISTOR WITH SELF-ALIGNED RETROGRADE EXTRINSIC BASE IMPLANT PROFILE AND SELF-ALIGNED SILICIDE
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Patent #:
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Issue Dt:
|
10/10/2006
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Application #:
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10904438
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Filing Dt:
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11/10/2004
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Publication #:
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Pub Dt:
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05/11/2006
| | | | |
Title:
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IMPROVED ION DETECTOR FOR IONBEAM APPLICATIONS
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|
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Patent #:
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Issue Dt:
|
09/12/2006
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Application #:
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10904460
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Filing Dt:
|
11/11/2004
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Publication #:
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Pub Dt:
|
05/11/2006
| | | | |
Title:
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CIRCUIT AND METHOD OF CONTROLLING INTEGRATED CIRCUIT POWER CONSUMPTION USING PHASE CHANGE SWITCHES
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|
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Patent #:
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|
Issue Dt:
|
01/15/2008
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Application #:
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10904528
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Filing Dt:
|
11/15/2004
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Publication #:
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Pub Dt:
|
05/18/2006
| | | | |
Title:
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STRUCTURE AND METHOD FOR ACCURATE DEEP TRENCH RESISTANCE MEASUREMENT
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|
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Patent #:
|
|
Issue Dt:
|
07/18/2006
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Application #:
|
10904555
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Filing Dt:
|
11/16/2004
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Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
FLUIDIC COOLING SYSTEMS AND METHODS FOR ELECTRONIC COMPONENTS
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|
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Patent #:
|
|
Issue Dt:
|
10/17/2006
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Application #:
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10904582
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Filing Dt:
|
11/17/2004
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Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
METHOD OF FABRICATING A BOTTLE TRENCH AND A BOTTLE TRENCH CAPACITOR
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|
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Patent #:
|
|
Issue Dt:
|
04/22/2008
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Application #:
|
10904601
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Filing Dt:
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11/18/2004
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Publication #:
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|
Pub Dt:
|
05/18/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR CLEANING A SEMICONDUCTOR SUBSTRATE IN AN IMMERSION LITHOGRAPHY SYSTEM
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|
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
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10904660
|
Filing Dt:
|
11/22/2004
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Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
Lowered Source/Drain Transistors
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
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Application #:
|
10904680
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Filing Dt:
|
11/23/2004
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Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
DENDRITE GROWTH CONTROL CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
10904681
|
Filing Dt:
|
11/23/2004
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Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
AN ELECTRICALLY PROGRAMMABLE FUSE FOR SILICON-ON-INSULATOR (SOI) TECHNOLOGY
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|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
10904808
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Filing Dt:
|
11/30/2004
|
Publication #:
|
|
Pub Dt:
|
06/01/2006
| | | | |
Title:
|
STRUCTURE AND METHOD OF APPLYING STRESSES TO PFET AND NFET TRANSISTOR CHANNELS FOR IMPROVED PERFORMANCE
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|
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Patent #:
|
|
Issue Dt:
|
11/21/2006
|
Application #:
|
10904827
|
Filing Dt:
|
12/01/2004
|
Publication #:
|
|
Pub Dt:
|
06/01/2006
| | | | |
Title:
|
IMPROVED HDP-BASED ILD CAPPING LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2006
|
Application #:
|
10904884
|
Filing Dt:
|
12/02/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
10904950
|
Filing Dt:
|
12/07/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
METHOD, SYSTEM AND PROGRAM PRODUCT FOR EVALUATING A CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
10905002
|
Filing Dt:
|
12/09/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
SOI DEVICE WITH DIFFERENT CRYSTALLOGRAPHIC ORIENTATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
10905008
|
Filing Dt:
|
12/09/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS
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|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
10905024
|
Filing Dt:
|
12/10/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
METHOD FOR FORMING DUAL ETCH STOP LINER AND PROTECTIVE LAYER IN A SEMICONDUCTOR DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
10905025
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Filing Dt:
|
12/10/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS
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|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
10905027
|
Filing Dt:
|
12/10/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND RELATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
10905041
|
Filing Dt:
|
12/13/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
SIDEWALL SEMICONDUCTOR TRANSISTORS
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|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
10905062
|
Filing Dt:
|
12/14/2004
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Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
DUAL STRESSED SOI SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
10905068
|
Filing Dt:
|
12/14/2004
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
Title:
|
METHOD FOR FORMING DAMASCENE STRUCTURE UTILIZING PLANARIZING MATERIAL COUPLED WITH COMPRESSIVE DIFFUSION BARRIER MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
10905094
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Filing Dt:
|
12/15/2004
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Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
LOW-COST DEEP TRENCH DECOUPLING CAPACITOR DEVICE AND PROCESS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
10905230
|
Filing Dt:
|
12/22/2004
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
| | | | |
Title:
|
MANUFACTURABLE COWP METAL CAP PROCESS FOR COPPER INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
10905474
|
Filing Dt:
|
01/06/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
CIRCUIT ELEMENT FUNCTION MATCHING DESPITE AUTO-GENERATED DUMMY SHAPES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2009
|
Application #:
|
10905475
|
Filing Dt:
|
01/06/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
ERASABLE NONVOLATILE MEMORY WITH SIDEWALL STORAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
10905480
|
Filing Dt:
|
01/06/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
ON-CHIP SIGNAL TRANSFORMER FOR GROUND NOISE ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
10905486
|
Filing Dt:
|
01/06/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
ONE MASK HYPERABRUPT JUNCTION VARACTOR USING A COMPENSATED CATHODE CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
10905586
|
Filing Dt:
|
01/12/2005
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
TRANSISTOR STRUCTURE HAVING STRESSED REGIONS OF OPPOSITE TYPES UNDERLYING CHANNEL AND SOURCE/DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
10905587
|
Filing Dt:
|
09/12/2005
|
Publication #:
|
|
Pub Dt:
|
03/15/2007
| | | | |
Title:
|
SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
10905589
|
Filing Dt:
|
01/12/2005
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
ENHANCED PFET USING SHEAR STRESS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
10905590
|
Filing Dt:
|
01/12/2005
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
WIRING PATTERNS FORMED BY SELECTIVE METAL PLATING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10905595
|
Filing Dt:
|
01/12/2005
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
LOW CONCENTRATION SiGe BUFFER DURING STRAINED Si GROWTH OF SSGOI MATERIAL FOR DOPANT DIFFUSION CONTROL AND DEFECT REDUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
10905643
|
Filing Dt:
|
01/14/2005
|
Title:
|
METHOD AND DEVICE FOR HEAT DISSIPATION IN
SEMICONDUCTOR MODULES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10905682
|
Filing Dt:
|
01/17/2005
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
LOW TRIGGER VOLTAGE, LOW LEAKAGE ESD NFET
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
10905684
|
Filing Dt:
|
01/17/2005
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
SELF-ALIGNED, SILICIDED, TRENCH-BASED, DRAM/EDRAM PROCESSES WITH IMPROVED RETENTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10905704
|
Filing Dt:
|
01/18/2005
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
IMPROVED SIGNAL DETECTOR FOR HIGH-SPEED SERDES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
10905816
|
Filing Dt:
|
01/21/2005
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
DETECTION OF DIAMOND CONTAMINATION IN POLISHING PAD
|
|