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NONE
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10914433
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Filing Dt:
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08/09/2004
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Publication #:
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Pub Dt:
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03/31/2005
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Title:
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Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
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08/16/2005
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10915087
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Filing Dt:
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08/10/2004
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Pub Dt:
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01/13/2005
| | | | |
Title:
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PATTERNING LAYERS COMPRISED OF SPIN-ON CERAMIC FILMS
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Patent #:
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Issue Dt:
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01/12/2010
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10915374
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Filing Dt:
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08/11/2004
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Publication #:
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Pub Dt:
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03/10/2005
| | | | |
Title:
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THERMOPLASTIC ADHESIVE PREFORM FOR HEAT SINK ATTACHMENT
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07/08/2008
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10915790
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Filing Dt:
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08/11/2004
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Publication #:
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Pub Dt:
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03/02/2006
| | | | |
Title:
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METHODS AND ARRANGEMENTS FOR LINK POWER REDUCTION
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Patent #:
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Issue Dt:
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10/31/2006
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Application #:
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10916201
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Filing Dt:
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08/11/2004
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Publication #:
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Pub Dt:
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02/16/2006
| | | | |
Title:
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MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS
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Patent #:
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12/29/2009
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10916755
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Filing Dt:
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08/12/2004
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Publication #:
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Pub Dt:
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02/16/2006
| | | | |
Title:
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ULTRATHIN POLYMERIC PHOTOACID GENERATOR LAYER AND METHOD OF FABRICATING AT LEAST ONE OF A DEVICE AND A MASK BY USING SAID LAYER
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Patent #:
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09/18/2007
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10916814
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Filing Dt:
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08/12/2004
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Publication #:
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Pub Dt:
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01/20/2005
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Title:
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ULTRA-THIN CHANNEL DEVICE WITH RAISED SOURCE AND DRAIN AND SOLID SOURCE EXTENSION DOPING
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03/21/2006
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10916934
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Filing Dt:
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08/12/2004
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Publication #:
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Pub Dt:
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01/27/2005
| | | | |
Title:
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PHOTORESIST COMPOSITION
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Patent #:
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05/19/2009
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10917193
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Filing Dt:
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08/12/2004
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Pub Dt:
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02/16/2006
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Title:
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PHYSICAL DESIGN SYSTEM AND METHOD
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Patent #:
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12/25/2007
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10919121
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Filing Dt:
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08/16/2004
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Publication #:
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Pub Dt:
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02/16/2006
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Title:
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THREE DIMENSIONAL INTEGRATED CIRCUIT
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Patent #:
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08/09/2005
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10920762
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Filing Dt:
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08/18/2004
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Publication #:
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Pub Dt:
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01/27/2005
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Title:
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UNDERLAYER COMPOSITIONS FOR MULTILAYER LITHOGRAPHIC PROCESSES
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12/30/2008
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10920786
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08/18/2004
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Publication #:
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02/23/2006
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Title:
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METHOD FOR DESIGNING ALTERNATING PHASE SHIFT MASKS
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02/13/2007
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10920936
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08/18/2004
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Publication #:
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02/03/2005
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Title:
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DAMASCENE RESISTOR AND METHOD FOR MEASURING THE WIDTH OF SAME
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10/31/2006
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10921007
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08/17/2004
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Publication #:
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Pub Dt:
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02/23/2006
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Title:
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INTEGRATED DUAL DAMASCENE RIE PROCESS WITH ORGANIC PATTERNING LAYER
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05/29/2007
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10923247
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08/20/2004
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Publication #:
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Pub Dt:
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02/23/2006
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Title:
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DUV LASER ANNEALING AND STABILIZATION OF SICOH FILMS
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11/22/2005
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10925021
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Filing Dt:
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08/25/2004
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Publication #:
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Pub Dt:
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01/27/2005
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Title:
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LAMINATION OF LIQUID CRYSTAL POLYMER DIELECTRIC FILMS
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Patent #:
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03/04/2008
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10926587
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08/26/2004
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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METHOD AND SYSTEM FOR BUILDING BINARY DECISION DIAGRAMS EFFICIENTLY IN A STRUCTURAL NETWORK REPRESENTATION OF A DIGITAL CIRCUIT
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Patent #:
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07/04/2006
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10928178
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Filing Dt:
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08/30/2004
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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UV ABSORBING GLASS CLOTH AND USE THEREOF
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Patent #:
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07/01/2008
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10929935
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Filing Dt:
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08/30/2004
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Publication #:
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03/02/2006
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Title:
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TEST-CASES FOR FUNCTIONAL VERIFICATION OF SYSTEM-LEVEL INTERCONNECT
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11/08/2005
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10930304
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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HIGH DENSITY CHIP CARRIER WITH INTEGRATED PASSIVE DEVICES
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06/05/2007
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10930404
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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12/29/2005
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Title:
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STRAINED-SILICON CMOS DEVICE AND METHOD
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12/25/2007
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10930823
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Filing Dt:
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09/01/2004
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Pub Dt:
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04/14/2005
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Title:
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PLATING APPARATUS FOR SUBSTRATE
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Patent #:
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Issue Dt:
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08/21/2007
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10931100
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Filing Dt:
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08/31/2004
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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APPARATUS, SYSTEM, AND METHOD FOR REDUCING ROTATIONAL VIBRATION TRANSMISSION WITHIN A DATA STORAGE SYSTEM
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09/05/2006
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10931660
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Filing Dt:
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09/01/2004
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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BIPOLAR TRANSISTOR WITH EXTRINSIC STRESS LAYER
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10/03/2006
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10931855
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09/01/2004
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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VERTICAL BIPOLAR TRANSISTOR WITH A MAJORITY CARRIER ACCUMULATION LAYER AS A SUBCOLLECTOR FOR SOI BICMOS WITH REDUCED BURIED OXIDE THICKNESS FOR LOW-SUBSTRATE BIAS OPERATION
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11/28/2006
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10932598
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09/02/2004
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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METHOD OF PRODUCING SILICON-GERMANIUM-ON-INSULATOR MATERIAL USING UNSTRAINED GE-CONTAINING SOURCE LAYERS
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08/29/2006
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10932982
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09/02/2004
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Publication #:
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Pub Dt:
|
03/03/2005
| | | | |
Title:
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ULTRA-THIN SILICON-ON-INSULATOR AND STRAINED-SILICON-DIRECT-ON-INSULATOR WITH HYBRID CRYSTAL ORIENTATIONS
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10/14/2008
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10933051
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09/02/2004
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Publication #:
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Pub Dt:
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03/02/2006
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Title:
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COOLING OF SUBSTRATE USING INTERPOSER CHANNELS
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Issue Dt:
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10/03/2006
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10933706
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09/03/2004
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Publication #:
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Pub Dt:
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03/09/2006
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Title:
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SENSE AMPLIFIER CIRCUITS AND HIGH SPEED LATCH CIRCUITS USING GATED DIODES
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Patent #:
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Issue Dt:
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05/20/2008
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10935136
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09/07/2004
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Publication #:
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Pub Dt:
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02/24/2005
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Title:
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STRESS INDUCING SPACERS
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06/09/2009
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10935497
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09/07/2004
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Publication #:
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Pub Dt:
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03/09/2006
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Title:
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METHOD AND PROCESS FOR FORMING A SELF-ALIGNED SILICIDE CONTACT
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Patent #:
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07/03/2007
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10939230
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09/10/2004
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Publication #:
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Pub Dt:
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03/16/2006
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Title:
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FLEXURE PLATE FOR MAINTAINING CONTACT BETWEEN A COOLING PLATE/HEAT SINK AND A MICROCHIP
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06/26/2007
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10939736
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09/13/2004
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Pub Dt:
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03/16/2006
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Title:
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METHOD OF CREATING DEFECT FREE HIGH GE CONTENT (>25%) SIGE-ON-INSULATOR (SGOI) SUBSTRATES USING WAFER BONDING TECHNIQUES
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03/17/2009
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10939823
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09/13/2004
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03/16/2006
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Title:
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METHOD FOR EVOLVING EFFICIENT COMMUNICATIONS
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12/04/2007
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10940543
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09/14/2004
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03/16/2006
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Title:
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POWER NETWORK RECONFIGURATION USING MEM SWITCHES
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NONE
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10941415
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Filing Dt:
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09/15/2004
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Pub Dt:
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03/16/2006
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Title:
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Method for creating and synthesizing multiple instances of a component from a single logical model
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08/21/2007
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10942559
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09/16/2004
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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FAST FIRING FLATTENING APPARATUS FOR SINTERED MULTILAYER CERAMIC ELECTRONIC SUBSTRATES
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Issue Dt:
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08/22/2006
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10946552
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Filing Dt:
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09/21/2004
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Publication #:
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Pub Dt:
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02/17/2005
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Title:
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MACRO DESIGN TECHNIQUES TO ACCOMMODATE CHIP LEVEL WIRING AND CIRCUIT PLACEMENT ACROSS THE MACRO
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Issue Dt:
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09/23/2008
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10948421
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09/23/2004
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Pub Dt:
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05/19/2005
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Title:
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LAYER TRANSFER OF LOW DEFECT SIGE USING AN ETCH-BACK PROCESS
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Issue Dt:
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01/06/2009
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10948772
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09/23/2004
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Publication #:
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Pub Dt:
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03/23/2006
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Title:
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SINGLE PASS VARIABLE BIT RATE CONTROL STRATEGY AND ENCODER FOR PROCESSING A VIDEO FRAME OF A SEQUENCE OF VIDEO FRAMES
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Patent #:
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Issue Dt:
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08/29/2006
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10949837
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09/24/2004
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Pub Dt:
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02/17/2005
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Title:
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MULTILAYER INTERCONNECT STRUCTURE CONTAINING AIR GAPS AND METHOD FOR MAKING
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Issue Dt:
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04/15/2008
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10951745
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09/28/2004
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Pub Dt:
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04/06/2006
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SILICON-ON-INSULATOR WAFER HAVING REENTRANT SHAPE DIELECTRIC TRENCHES
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03/13/2007
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10952269
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09/28/2004
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02/24/2005
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Title:
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METHOD AND APPARATUS FOR ADDRESS DECODING OF EMBEDDED DRAM DEVICES
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02/06/2007
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10953378
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09/29/2004
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Pub Dt:
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03/10/2005
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Title:
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INCORPORATION OF CARBON IN SILICON/SILICON GERMANIUM EPITAXIAL LAYER TO ENHANCE YIELD FOR SI-GE BIPOLAR TECHNOLOGY
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02/12/2008
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10953752
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09/29/2004
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Pub Dt:
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03/30/2006
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Title:
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UV-CURABLE SOLVENT FREE COMPOSITIONS AND USE THEREOF IN CERAMIC CHIP DEFECT REPAIR
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NONE
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10954672
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Filing Dt:
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09/30/2004
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Publication #:
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04/06/2006
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Title:
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Device and method for reducing dishing of critical on-chip interconnect lines
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09/11/2007
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10954838
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09/30/2004
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Pub Dt:
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03/30/2006
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Title:
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STRUCTURE AND METHOD FOR MANUFACTURING MOSFET WITH SUPER-STEEP RETROGRADED ISLAND
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04/14/2009
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10956466
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09/30/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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SYSTEM AND METHOD FOR TOLERATING MULTIPLE STORAGE DEVICE FAILURES IN A STORAGE SYSTEM WITH CONSTRAINED PARITY IN-DEGREE
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08/07/2007
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10956851
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10/01/2004
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Pub Dt:
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03/17/2005
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Title:
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SELF-ALIGNED NANOTUBE FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING SAME
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Issue Dt:
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01/20/2009
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10957342
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Filing Dt:
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10/01/2004
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Publication #:
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Pub Dt:
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12/08/2005
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Title:
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SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-K DIELECTRICS
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Issue Dt:
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01/23/2007
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10957833
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10/04/2004
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Publication #:
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Pub Dt:
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02/24/2005
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Title:
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SOI WAFERS WITH 30-100 ¿ BURIED OXIDE (BOX) CREATED BY WAFER BONDING USING 30-100 ¿ THIN OXIDE AS BONDING LAYER
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Issue Dt:
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10/21/2008
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10958717
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10/05/2004
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Publication #:
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Pub Dt:
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04/06/2006
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Title:
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HYBRID ORIENTATION CMOS WITH PARTIAL INSULATION PROCESS
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Patent #:
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Issue Dt:
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09/30/2008
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Application #:
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10959938
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Filing Dt:
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10/06/2004
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Publication #:
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Pub Dt:
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04/21/2005
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Title:
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SYSTEM AND METHOD OF TRANSFER PRINTING AN ORGANIC SEMICONDUCTOR
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Patent #:
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Issue Dt:
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07/24/2007
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Application #:
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10960730
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Filing Dt:
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10/07/2004
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Publication #:
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Pub Dt:
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04/13/2006
| | | | |
Title:
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ARCHITECTURAL LEVEL THROUGHPUT BASED POWER MODELING METHODOLOGY AND APPARATUS FOR PERVASIVELY CLOCK-GATED PROCESSOR CORES
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Issue Dt:
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05/29/2007
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Application #:
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10962121
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Filing Dt:
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10/08/2004
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Publication #:
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Pub Dt:
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03/31/2005
| | | | |
Title:
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METHODS FOR MODELING LATCH TRANSPARENCY
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Patent #:
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Issue Dt:
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08/08/2006
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Application #:
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10963228
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Filing Dt:
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10/12/2004
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Publication #:
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Pub Dt:
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07/07/2005
| | | | |
Title:
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METHOD FOR SCALABLE, LOW-COST POLYSILICON CAPACITOR IN A PLANAR DRAM
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Patent #:
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Issue Dt:
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01/20/2009
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Application #:
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10963475
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Filing Dt:
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10/12/2004
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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APPARATUS, SYSTEM, AND METHOD FOR FACILITATING PORT TESTING OF A MULTI-PORT HOST ADAPTER
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Patent #:
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Issue Dt:
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02/17/2009
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Application #:
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10964254
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Filing Dt:
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10/13/2004
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Publication #:
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Pub Dt:
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04/13/2006
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Title:
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ULTRA LOW K PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION PROCESSES USING A SINGLE BIFUNCTIONAL PRECURSOR CONTAINING BOTH A SICOH MATRIX FUNCTIONALITY AND ORGANIC POROGEN FUNCTIONALITY
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Patent #:
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Issue Dt:
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10/16/2007
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Application #:
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10964882
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Filing Dt:
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10/14/2004
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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MODIFIED VIA BOTTOM STRUCTURE FOR RELIABILITY ENHANCEMENT
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Patent #:
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Issue Dt:
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05/29/2007
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Application #:
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10965031
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Filing Dt:
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10/14/2004
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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METHOD OF FORMING LOW RESISTANCE AND RELIABLE VIA IN INTER-LEVEL DIELECTRIC INTERCONNECT
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Patent #:
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Issue Dt:
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08/08/2006
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Application #:
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10965106
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Filing Dt:
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10/14/2004
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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MULTI-THRESHOLD COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (MTCMOS) BUS CIRCUIT AND METHOD FOR REDUCING BUS POWER CONSUMPTION VIA PULSED STANDBY SWITCHING
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Patent #:
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Issue Dt:
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09/25/2007
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Application #:
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10965992
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Filing Dt:
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10/15/2004
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Publication #:
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Pub Dt:
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03/03/2005
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Title:
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METHOD TO CONTROL DEVICE THRESHOLD OF SOI MOSFET'S
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Patent #:
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Issue Dt:
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02/12/2008
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Application #:
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10966202
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Filing Dt:
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10/15/2004
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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MICROELECTRONIC DEVICES AND METHODS
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Patent #:
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Issue Dt:
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02/19/2008
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Application #:
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10966301
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Filing Dt:
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10/15/2004
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Publication #:
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Pub Dt:
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10/13/2005
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Title:
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PROCESS OF REMOVING RESIDUE FROM A PRECISION SURFACE USING LIQUID OR SUPERCRITICAL CARBON DIOXIDE COMPOSITION
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Patent #:
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Issue Dt:
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07/17/2007
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Application #:
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10966492
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Filing Dt:
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10/15/2004
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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METHOD FOR OPTIMIZING INTEGRATED CIRCUIT DEVICE DESIGN AND SERVICE
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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10967035
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Filing Dt:
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10/15/2004
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Publication #:
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Pub Dt:
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03/03/2005
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Title:
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METHOD OF MAKING A CIRCUITIZED SUBSTRATE
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Patent #:
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Issue Dt:
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09/16/2008
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Application #:
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10968181
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Filing Dt:
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10/20/2004
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Publication #:
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Pub Dt:
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04/20/2006
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Title:
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SYSTEM AND METHOD FOR SENSOR REPLICATION FOR ENSEMBLE AVERAGING IN MICRO-ELECTROMECHANICAL SYSTEMS (MEMS)
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Patent #:
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Issue Dt:
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10/14/2008
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Application #:
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10968917
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Filing Dt:
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10/21/2004
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Publication #:
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Pub Dt:
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05/11/2006
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Title:
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SYSTEM AND METHOD FOR PROBLEM DETERMINATION USING DEPENDENCY GRAPHS AND RUN-TIME BEHAVIOR MODELS
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Patent #:
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Issue Dt:
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05/27/2008
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Application #:
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10969684
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Filing Dt:
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10/20/2004
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Publication #:
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Pub Dt:
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03/17/2005
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Title:
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METHOD OF MAKING A PRINTED WIRING BOARD WITH CONFORMALLY PLATED CIRCUIT TRACES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10969705
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Filing Dt:
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10/20/2004
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Publication #:
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Pub Dt:
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03/24/2005
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Title:
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Structure and method for eliminating metal contact to P-well or N-well shorts or high leakage paths using polysilicon liner
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Patent #:
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Issue Dt:
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09/25/2007
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Application #:
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10970458
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Filing Dt:
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10/21/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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HANDLING OF THE TRANSMIT ENABLE SIGNAL IN A DYNAMIC RANDOM ACCESS MEMORY CONTROLLER
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Patent #:
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Issue Dt:
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06/24/2008
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Application #:
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10970469
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Filing Dt:
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10/21/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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METHOD, SYSTEM AND PROGRAM PRODUCT FOR DEFINING AND RECORDING MINIUM AND MAXIMUM EVENT COUNTS OF A SIMULATION UTILIZING A HIGH LEVEL LANGUAGE
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10970522
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Filing Dt:
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10/21/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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METHOD AND SUM ADDRESSED CELL ENCODER FOR ENHANCED COMPARE AND SEARCH TIMING FOR CAM COMPARE
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Patent #:
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Issue Dt:
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08/08/2006
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Application #:
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10970524
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Filing Dt:
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10/21/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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METHOD AND STRUCTURE TO CONTROL COMMON MODE IMPEDANCE IN FAN-OUT REGIONS
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10971238
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Filing Dt:
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10/22/2004
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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METHOD OF CLOSING AN ANTIFUSE USING LASER ENERGY
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Patent #:
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Issue Dt:
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11/13/2007
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Application #:
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10971947
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Filing Dt:
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10/22/2004
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Publication #:
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Pub Dt:
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03/10/2005
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Title:
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SYSTEM ON A CHIP BUS WITH AUTOMATIC PIPELINE STAGE INSERTION FOR TIMING CLOSURE
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10972696
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Filing Dt:
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10/25/2004
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Publication #:
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Pub Dt:
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05/11/2006
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Title:
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SYSTEM AND METHOD FOR IMPROVING SPATIAL RESOLUTION OF ELECTRON HOLOGRAPHY
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Patent #:
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Issue Dt:
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11/28/2006
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Application #:
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10973366
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Filing Dt:
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10/26/2004
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Publication #:
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Pub Dt:
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05/11/2006
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Title:
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SRAM RING OSCILLATOR
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10973683
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Filing Dt:
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10/26/2004
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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Material and process for etched structure filling and planarizing
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Patent #:
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Issue Dt:
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02/10/2009
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Application #:
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10976068
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Filing Dt:
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10/29/2004
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Publication #:
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Pub Dt:
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04/28/2005
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Title:
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ALUMINUM NITRIDE AND ALUMINUM OXIDE/ALUMINUM NITRIDE HETEROSTRUCTURE GATE DIELECTRIC STACK BASED FIELD EFFECT TRANSISTORS AND METHOD FOR FORMING SAME
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Patent #:
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Issue Dt:
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12/13/2005
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Application #:
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10976598
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Filing Dt:
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10/29/2004
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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MAGNETIC RANDOM ACCESS MEMORY USING MEMORY CELLS WITH ROTATED MAGNETIC STORAGE ELEMENTS
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Patent #:
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Issue Dt:
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06/30/2009
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Application #:
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10977159
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Filing Dt:
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10/29/2004
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Publication #:
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Pub Dt:
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05/04/2006
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Title:
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METHOD FOR HIGH-DENSITY PACKAGING AND COOLING OF HIGH-POWERED COMPUTE AND STORAGE SERVER BLADES
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Patent #:
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Issue Dt:
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10/30/2007
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Application #:
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10977432
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Filing Dt:
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10/29/2004
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Publication #:
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Pub Dt:
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05/18/2006
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Title:
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DYNAMIC MEMORY ARCHITECTURE EMPLOYING PASSIVE EXPIRATION OF DATA
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Patent #:
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Issue Dt:
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09/12/2006
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Application #:
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10977667
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Filing Dt:
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10/29/2004
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Publication #:
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Pub Dt:
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05/05/2005
| | | | |
Title:
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INTEGRATED LINE DRIVER
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Patent #:
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Issue Dt:
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07/10/2007
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Application #:
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10977768
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Filing Dt:
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10/29/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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FINFET BODY CONTACT STRUCTURE
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Patent #:
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Issue Dt:
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02/17/2009
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Application #:
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10978028
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Filing Dt:
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10/29/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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SCANNING PROBE-BASED LITHOGRAPHY METHOD
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Patent #:
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Issue Dt:
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06/10/2008
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Application #:
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10978056
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Filing Dt:
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10/30/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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SYSTEMS AND METHODS FOR STORAGE AREA NETWORK DESIGN
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Patent #:
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Issue Dt:
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10/24/2006
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Application #:
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10978067
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Filing Dt:
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10/28/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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POWER GATING TECHNIQUES ABLE TO HAVE DATA RETENTION AND VARIABILITY IMMUNITY PROPERTIES
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Patent #:
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Issue Dt:
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01/11/2011
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Application #:
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10978389
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Filing Dt:
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11/02/2004
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Publication #:
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Pub Dt:
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05/18/2006
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Title:
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SYSTEM AND METHOD FOR RECOVERY OF DATA FOR A LOST SECTOR IN A STORAGE SYSTEM
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Patent #:
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Issue Dt:
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09/25/2007
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Application #:
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10978715
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Filing Dt:
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11/01/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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HETERO-INTEGRATED STRAINED SILICON N-AND P-MOSFETS
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Patent #:
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Issue Dt:
|
12/13/2005
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Application #:
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10979366
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Filing Dt:
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11/01/2004
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Publication #:
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Pub Dt:
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03/24/2005
| | | | |
Title:
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PRINTED WIRING BOARD INTERPOSER SUB-ASSEMBLY AND METHOD
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Patent #:
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Issue Dt:
|
01/20/2009
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Application #:
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10979633
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Filing Dt:
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11/02/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
|
Field effect transistor including damascene gate with an internal spacer structure
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Patent #:
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|
Issue Dt:
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01/09/2007
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Application #:
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10980220
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Filing Dt:
|
11/03/2004
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Publication #:
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Pub Dt:
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07/07/2005
| | | | |
Title:
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ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> SI UNDER BIAXIAL COMPRESSIVE STRAIN
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Patent #:
|
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Issue Dt:
|
01/22/2008
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Application #:
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10980365
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Filing Dt:
|
11/03/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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SILICON CONTAINING TARC / BARRIER LAYER
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Patent #:
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Issue Dt:
|
11/07/2006
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Application #:
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10981155
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Filing Dt:
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11/04/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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NOVEL CIRCUIT FOR MINIMIZING FILTER CAPACITANCE LEAKAGE INDUCED JITTER IN PHASE LOCKED LOOPS (PLLS)
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Patent #:
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Issue Dt:
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02/26/2008
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Application #:
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10981233
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Filing Dt:
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11/04/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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HARDMASK FOR RELIABILITY OF SILICON BASED DIELECTRICS
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|
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Patent #:
|
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Issue Dt:
|
03/13/2012
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Application #:
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10981926
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Filing Dt:
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11/05/2004
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Publication #:
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Pub Dt:
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03/24/2005
| | | | |
Title:
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DUAL MAGNETIC TUNNEL JUNCTION SENSOR WITH A LONGITUDINAL BIAS STACK
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Patent #:
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Issue Dt:
|
12/04/2007
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Application #:
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10982411
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Filing Dt:
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11/05/2004
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Publication #:
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Pub Dt:
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06/16/2005
| | | | |
Title:
|
USE OF HYDROGEN IMPLANTATION TO IMPROVE MATERIAL PROPERTIES OF SILICON-GERMANIUM-ON-INSULATOR MATERIAL MADE BY THERMAL DIFFUSION
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Patent #:
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Issue Dt:
|
10/04/2011
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Application #:
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10982575
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Filing Dt:
|
11/05/2004
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Publication #:
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Pub Dt:
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05/11/2006
| | | | |
Title:
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METHOD FOR THERMAL CHARACTERIZATION UNDER NON-UNIFORM HEAT LOAD
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Patent #:
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Issue Dt:
|
03/27/2007
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Application #:
|
10983345
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Filing Dt:
|
11/08/2004
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Publication #:
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Pub Dt:
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05/11/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR PLASMA INDUCED MODIFICATION AND IMPROVEMENT OF CRITICAL DIMENSION UNIFORMITY
|
|