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Reel/Frame:048746/0001   Pages: 69
Recorded: 03/29/2019
Attorney Dkt #:69008/27
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 782
Page 4 of 8
Pages: 1 2 3 4 5 6 7 8
1
Patent #:
Issue Dt:
06/30/2009
Application #:
11488494
Filing Dt:
07/18/2006
Publication #:
Pub Dt:
01/24/2008
Title:
DRAM INTERFACE CIRCUITS THAT SUPPORT FAST DESKEW CALIBRATION AND METHODS OF OPERATING SAME
2
Patent #:
Issue Dt:
10/14/2008
Application #:
11494847
Filing Dt:
07/27/2006
Publication #:
Pub Dt:
01/31/2008
Title:
LOW VARIATION VOLTAGE OUTPUT DIFFERENTIAL FOR DIFFERENTIAL DRIVERS
3
Patent #:
Issue Dt:
08/10/2010
Application #:
11521886
Filing Dt:
09/14/2006
Publication #:
Pub Dt:
03/20/2008
Title:
METHOD FOR DETERMINISTIC TIMED TRANSFER OF DATA WITH MEMORY USING A SERIAL INTERFACE
4
Patent #:
Issue Dt:
11/02/2010
Application #:
11524660
Filing Dt:
09/20/2006
Publication #:
Pub Dt:
05/29/2008
Title:
METHOD OF HANDLING FLOW CONTROL IN DAISY-CHAIN PROTOCOLS
5
Patent #:
Issue Dt:
01/06/2009
Application #:
11527374
Filing Dt:
09/25/2006
Publication #:
Pub Dt:
05/29/2008
Title:
METHOD FOR IMPROVED SINGLE EVENT LATCH UP RESISTANCE IN AN INTEGRATED CIRCUIT
6
Patent #:
Issue Dt:
10/09/2007
Application #:
11532657
Filing Dt:
09/18/2006
Title:
DELAY CHAIN INTEGRATED CIRCUITS HAVING BINARY-WEIGHTED DELAY CHAIN UNITS WITH BUILT-IN PHASE COMPARATORS THEREIN
7
Patent #:
Issue Dt:
04/05/2011
Application #:
11533729
Filing Dt:
09/20/2006
Publication #:
Pub Dt:
05/10/2007
Title:
SOLID STATE ELECTROCHEMICAL GAS SENSOR AND METHOD FOR FABRICATING SAME
8
Patent #:
Issue Dt:
02/12/2008
Application #:
11536210
Filing Dt:
09/28/2006
Title:
METHOD AND APPARATUS WITH POWER AND GROUND STRIPS FOR CONNECTING TO DECOUPLING CAPACITORS
9
Patent #:
Issue Dt:
07/21/2009
Application #:
11557320
Filing Dt:
11/07/2006
Publication #:
Pub Dt:
05/29/2008
Title:
LOW POWER LOGIC OUTPUT BUFFER
10
Patent #:
Issue Dt:
07/01/2008
Application #:
11587105
Filing Dt:
10/19/2006
Publication #:
Pub Dt:
09/27/2007
Title:
ERROR REDUCTION IN A DIGITAL-TO-ANALOG (DAC) CONVERTER
11
Patent #:
Issue Dt:
02/02/2010
Application #:
11590940
Filing Dt:
11/01/2006
Publication #:
Pub Dt:
05/01/2008
Title:
PACKAGE SUBSTRATE WITH INSERTED DISCRETE CAPACITORS
12
Patent #:
Issue Dt:
06/08/2010
Application #:
11599895
Filing Dt:
11/14/2006
Publication #:
Pub Dt:
05/15/2008
Title:
PHASE DIFFERENCE DETECTOR HAVING CONCURRENT FINE AND COARSE CAPABILITIES
13
Patent #:
Issue Dt:
03/01/2011
Application #:
11608234
Filing Dt:
12/07/2006
Publication #:
Pub Dt:
06/12/2008
Title:
INPUT TERMINATION FOR DELAY LOCKED LOOP FEEDBACK WITH IMPEDANCE MATCHING
14
Patent #:
Issue Dt:
10/05/2010
Application #:
11608236
Filing Dt:
12/07/2006
Publication #:
Pub Dt:
06/12/2008
Title:
COMMON ACCESS RING SYSTEM
15
Patent #:
Issue Dt:
10/12/2010
Application #:
11608239
Filing Dt:
12/07/2006
Publication #:
Pub Dt:
06/12/2008
Title:
COMMON ACCESS RING/SUB-RING SYSTEM
16
Patent #:
Issue Dt:
01/12/2010
Application #:
11612740
Filing Dt:
12/19/2006
Publication #:
Pub Dt:
06/19/2008
Title:
USING A DELAY CLOCK TO OPTIMIZE THE TIMING MARGIN OF SEQUENTIAL LOGIC
17
Patent #:
Issue Dt:
10/13/2009
Application #:
11618545
Filing Dt:
12/29/2006
Title:
METHOD AND APPARATUS FOR CLOCK GENERATION
18
Patent #:
Issue Dt:
08/04/2009
Application #:
11621105
Filing Dt:
01/08/2007
Publication #:
Pub Dt:
07/10/2008
Title:
MODULAR DISTRIBUTIVE ARITHMETIC LOGIC UNIT
19
Patent #:
Issue Dt:
03/02/2010
Application #:
11626594
Filing Dt:
01/24/2007
Title:
METHOD AND APPARATUS FOR CROSS-POINT DETECTION
20
Patent #:
Issue Dt:
04/27/2010
Application #:
11668360
Filing Dt:
01/29/2007
Title:
ELECTRICAL OVERSTRESS (EOS) AND ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUIT AND METHOD OF USE
21
Patent #:
Issue Dt:
01/11/2011
Application #:
11679817
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
METHOD AND STRUCTURE TO SUPPORT SYSTEM RESOURCE ACCESS OF A SERIAL DEVICE IMPLEMENTING A LITE-WEIGHT PROTOCOL
22
Patent #:
Issue Dt:
08/20/2013
Application #:
11679820
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
Hardware-Based Concurrent Direct Memory Access (DMA) Engines On Serial Rapid Input/Output SRIO Interface
23
Patent #:
Issue Dt:
11/10/2009
Application #:
11679823
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
RAPID INPUT/OUTPUT DOORBELL COALESCING TO MINIMIZE CPU UTILIZATION AND REDUCE SYSTEM INTERRUPT LATENCY
24
Patent #:
Issue Dt:
01/10/2012
Application #:
11679824
Filing Dt:
02/27/2007
Publication #:
Pub Dt:
08/28/2008
Title:
MULTI-BUS STRUCTURE FOR OPTIMIZING SYSTEM PERFORMANCE OF A SERIAL BUFFER
25
Patent #:
Issue Dt:
08/24/2010
Application #:
11683800
Filing Dt:
03/08/2007
Publication #:
Pub Dt:
09/11/2008
Title:
PHASE LOCKED LOOP AND DELAY LOCKED LOOP WITH CHOPPER STABILIZED PHASE OFFSET
26
Patent #:
Issue Dt:
10/12/2010
Application #:
11692129
Filing Dt:
03/27/2007
Publication #:
Pub Dt:
08/16/2007
Title:
CIRCUIT STRUCTURE WITH MULTIFUNCTION CIRCUIT COVER
27
Patent #:
Issue Dt:
01/05/2010
Application #:
11693660
Filing Dt:
03/29/2007
Publication #:
Pub Dt:
10/02/2008
Title:
SIMPLE TECHNIQUE FOR REDUCTION OF GAIN IN A VOLTAGE CONTROLLED OSCILLATOR
28
Patent #:
Issue Dt:
07/28/2009
Application #:
11694861
Filing Dt:
03/30/2007
Publication #:
Pub Dt:
10/02/2008
Title:
INPUT CLOCK DETECTION CIRCUIT FOR POWERING DOWN A PLL-BASED SYSTEM
29
Patent #:
Issue Dt:
06/30/2009
Application #:
11710371
Filing Dt:
02/23/2007
Publication #:
Pub Dt:
08/28/2008
Title:
HIGH-SPEED, LOW-POWER LEVEL SHIFTER FOR MIXED SIGNAL-LEVEL ENVIRONMENTS
30
Patent #:
Issue Dt:
10/14/2008
Application #:
11713466
Filing Dt:
03/02/2007
Title:
TUNABLE OPTICAL OSCILLATOR
31
Patent #:
Issue Dt:
07/14/2009
Application #:
11739459
Filing Dt:
04/24/2007
Title:
METHOD AND APPARATUS FOR GROUND BOUNCE AND POWER SUPPLY BOUNCE DETECTION
32
Patent #:
Issue Dt:
06/07/2011
Application #:
11739546
Filing Dt:
04/24/2007
Title:
METHOD AND APPARATUS FOR ADJUSTING PLL AND/OR DLL TIMING OFFSETS
33
Patent #:
Issue Dt:
04/06/2010
Application #:
11743080
Filing Dt:
05/01/2007
Title:
PROCESSING SWITCH FOR ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING
34
Patent #:
Issue Dt:
07/03/2012
Application #:
11745449
Filing Dt:
05/07/2007
Publication #:
Pub Dt:
11/08/2007
Title:
COMPOSITE MEMBRANES AND METHODS FOR MAKING SAME
35
Patent #:
Issue Dt:
08/11/2009
Application #:
11781452
Filing Dt:
07/23/2007
Title:
DIGITALLY CONTROLLED SYSTEM ON-CHIP (SOC) CLOCK GENERATOR
36
Patent #:
Issue Dt:
03/23/2010
Application #:
11781629
Filing Dt:
07/23/2007
Title:
FOLDED-CASCODE AMPLIFIER WITH ADJUSTABLE CONTINUOUS TIME EQUALIZER
37
Patent #:
Issue Dt:
10/18/2011
Application #:
11786175
Filing Dt:
04/10/2007
Publication #:
Pub Dt:
10/16/2008
Title:
BEHAVIORAL MODELING OF HIGH SPEED DIFFERENTIAL SIGNALS BASED ON PHYSICAL CHARACTERISTICS
38
Patent #:
Issue Dt:
06/09/2009
Application #:
11796820
Filing Dt:
04/28/2007
Publication #:
Pub Dt:
09/06/2007
Title:
TRANSCONDUCTANCE AND CURRENT MODULATION FOR RESONANT FREQUENCY CONTROL AND SELECTION
39
Patent #:
Issue Dt:
06/16/2009
Application #:
11796821
Filing Dt:
04/28/2007
Publication #:
Pub Dt:
09/06/2007
Title:
MONOLITHIC CLOCK GENERATOR AND TIMING/FREQUENCY REFERENCE
40
Patent #:
Issue Dt:
09/08/2009
Application #:
11800438
Filing Dt:
05/04/2007
Publication #:
Pub Dt:
12/13/2007
Title:
OUTPUT DRIVE CIRCUIT THAT ACCOMMODATES VARIABLE SUPPLY VOLTAGES
41
Patent #:
Issue Dt:
03/16/2010
Application #:
11805368
Filing Dt:
05/23/2007
Publication #:
Pub Dt:
09/27/2007
Title:
MULTI-TERMINAL HARMONIC OSCILLATOR INTEGRATED CIRCUIT WITH FREQUENCY CALIBRATION AND FREQUENCY CONFIGURATION
42
Patent #:
Issue Dt:
06/16/2009
Application #:
11805427
Filing Dt:
05/23/2007
Publication #:
Pub Dt:
09/27/2007
Title:
FREQUENCY CALIBRATION FOR A MONOLITHIC CLOCK GENERATOR AND TIMING/FREQUENCY REFERENCE
43
Patent #:
Issue Dt:
10/11/2011
Application #:
11857249
Filing Dt:
09/18/2007
Title:
METHOD AND APPARATUS FOR PACKET CUT-THROUGH
44
Patent #:
Issue Dt:
11/22/2011
Application #:
11857326
Filing Dt:
09/18/2007
Title:
METHOD AND APPARATUS FOR QUEUE CONCATENATION
45
Patent #:
Issue Dt:
03/17/2009
Application #:
11857361
Filing Dt:
09/18/2007
Title:
METHOD AND APPARATUS FOR LOGICAL IDENTIFICATION PRIORITY
46
Patent #:
Issue Dt:
03/29/2011
Application #:
11858834
Filing Dt:
09/20/2007
Title:
ADAPTIVE DECISION FEEDBACK EQUALIZER FOR HIGH DATA RATE SERIAL LINK RECEIVER
47
Patent #:
Issue Dt:
02/08/2011
Application #:
11860110
Filing Dt:
09/24/2007
Title:
DDR MEMORY SYSTEM FOR MEASURING A CLOCK SIGNAL BY IDENTIFYING A DELAY VALUE CORRESPONDING TO A CHANGED LOGIC STATE DURING CLOCK SIGNAL TRANSITIONS
48
Patent #:
Issue Dt:
07/07/2009
Application #:
11860910
Filing Dt:
09/25/2007
Title:
METHODS AND CIRCUITS FOR DDR-2 MEMORY DEVICE READ DATA RESYNCHRONIZATION
49
Patent #:
Issue Dt:
06/15/2010
Application #:
11861399
Filing Dt:
09/26/2007
Title:
INTEGRATED CIRCUIT MEMORY SYSTEMS HAVING WRITE-BACK BUFFERS THEREIN THAT SUPPORT READ-WRITE-MODIFY (RWM) OPERATIONS WITHIN HIGH CAPACITY MEMORY DEVICES
50
Patent #:
Issue Dt:
05/10/2011
Application #:
11861869
Filing Dt:
09/26/2007
Title:
CLOCK GENERATOR AND METHOD FOR PROVIDING RELIABLE CLOCK SIGNAL USING ARRAY OF MEMS RESONATORS
51
Patent #:
Issue Dt:
09/08/2009
Application #:
11862653
Filing Dt:
09/27/2007
Title:
CLOCK GENERATOR WITH SELF-BIAS BANDWIDTH CONTROL
52
Patent #:
Issue Dt:
05/17/2011
Application #:
11863176
Filing Dt:
09/27/2007
Publication #:
Pub Dt:
04/02/2009
Title:
SERIAL BUFFER SUPPORTING VIRTUAL QUEUE TO PHYSICAL MEMORY MAPPING
53
Patent #:
Issue Dt:
09/28/2010
Application #:
11863184
Filing Dt:
09/27/2007
Publication #:
Pub Dt:
04/02/2009
Title:
MULTI-FUNCTION QUEUE TO SUPPORT DATA OFFLOAD, PROTOCOL TRANSLATION AND PASS-THROUGH FIFO
54
Patent #:
Issue Dt:
10/19/2010
Application #:
11863192
Filing Dt:
09/27/2007
Publication #:
Pub Dt:
04/02/2009
Title:
ADAPTIVE INTERRUPT ON SERIAL RAPID INPUT/OUTPUT (SRIO) ENDPOINT
55
Patent #:
Issue Dt:
12/08/2009
Application #:
11872027
Filing Dt:
10/14/2007
Title:
METHOD AND APPARATUS FOR PRE-CLOCKING
56
Patent #:
Issue Dt:
11/29/2011
Application #:
11873357
Filing Dt:
10/16/2007
Title:
ERROR CORRECTION CODE SYSTEM AND METHOD
57
Patent #:
Issue Dt:
05/04/2010
Application #:
11904225
Filing Dt:
09/25/2007
Publication #:
Pub Dt:
03/26/2009
Title:
VOLTAGE-TO-CURRENT CONVERTER
58
Patent #:
Issue Dt:
12/06/2011
Application #:
11904687
Filing Dt:
09/27/2007
Publication #:
Pub Dt:
04/02/2009
Title:
METHOD FOR RELIABLE INJECTION OF DETERMINISTIC JITTER FOR HIGH SPEED TRANSCEIVER SIMULATION
59
Patent #:
Issue Dt:
02/21/2012
Application #:
11904752
Filing Dt:
09/28/2007
Publication #:
Pub Dt:
04/02/2009
Title:
PACKAGE WITH IMPROVED CONNECTION OF A DECOUPLING CAPACITOR
60
Patent #:
Issue Dt:
08/04/2009
Application #:
11904803
Filing Dt:
09/28/2007
Publication #:
Pub Dt:
04/02/2009
Title:
COMMON MODE VOLTAGE EXTRACTION CIRCUIT
61
Patent #:
Issue Dt:
07/19/2011
Application #:
11904875
Filing Dt:
09/28/2007
Publication #:
Pub Dt:
04/02/2009
Title:
METHODS AND SYSTEMS FOR PROVIDING VARIABLE CLOCK RATES AND DATA RATES FOR A SERDES
62
Patent #:
Issue Dt:
08/30/2011
Application #:
11904895
Filing Dt:
09/28/2007
Publication #:
Pub Dt:
04/02/2009
Title:
DIGITAL SPREAD SPECTRUM METHOD BASED ON PRECISE PHASE DELTA-SIGMA ALGORITHM
63
Patent #:
Issue Dt:
08/09/2011
Application #:
11906004
Filing Dt:
09/28/2007
Publication #:
Pub Dt:
04/02/2009
Title:
METHOD FOR BINARY CLOCK AND DATA RECOVERY FOR FAST ACQUISITION AND SMALL TRACKING ERROR
64
Patent #:
Issue Dt:
06/09/2009
Application #:
11926013
Filing Dt:
10/28/2007
Publication #:
Pub Dt:
05/01/2008
Title:
LOW-LATENCY START-UP FOR A MONOLITHIC CLOCK GENERATOR AND TIMING/FREQUENCY REFERENCE
65
Patent #:
Issue Dt:
10/26/2010
Application #:
11931191
Filing Dt:
10/31/2007
Publication #:
Pub Dt:
02/28/2008
Title:
LOW POWER OUTPUT DRIVER
66
Patent #:
Issue Dt:
06/24/2008
Application #:
11932257
Filing Dt:
10/31/2007
Publication #:
Pub Dt:
05/01/2008
Title:
AUTOMATED BALL MOUNTING PROCESS WITH SOLDER BALL TESTING
67
Patent #:
Issue Dt:
09/21/2010
Application #:
11935241
Filing Dt:
11/05/2007
Title:
SEMICONDUCTOR DIE AND METHOD FOR FORMING A SEMICONDUCTOR DIE HAVING POWER AND GROUND STRIPS THAT ARE ORIENTED DIAGONALLY
68
Patent #:
Issue Dt:
11/30/2010
Application #:
11948993
Filing Dt:
11/30/2007
Publication #:
Pub Dt:
06/05/2008
Title:
OUTPUT SLEW RATE CONTROL IN LOW VOLTAGE DIFFERENTIAL SIGNAL (LVDS) DRIVER
69
Patent #:
Issue Dt:
06/15/2010
Application #:
11955340
Filing Dt:
12/12/2007
Title:
PHASE STEP CLOCK GENERATOR
70
Patent #:
Issue Dt:
10/18/2011
Application #:
11958313
Filing Dt:
12/17/2007
Title:
PACKET SWITCH WITH PORT ROUTE TABLES
71
Patent #:
Issue Dt:
01/25/2011
Application #:
11960618
Filing Dt:
12/19/2007
Title:
LOOK-AHEAD BUILT-IN SELF TESTS
72
Patent #:
Issue Dt:
05/18/2010
Application #:
11967234
Filing Dt:
12/30/2007
Publication #:
Pub Dt:
05/01/2008
Title:
SPREAD SPECTRUM CLOCK AND REFERENCE SIGNAL GENERATOR
73
Patent #:
Issue Dt:
01/10/2012
Application #:
11967236
Filing Dt:
12/30/2007
Publication #:
Pub Dt:
05/01/2008
Title:
INTEGRATED CIRCUIT SYSTEMS HAVING PROCESSOR-CONTROLLED CLOCK SIGNAL GENERATORS THEREIN THAT SUPPORT EFFICIENT POWER MANAGEMENT
74
Patent #:
Issue Dt:
05/13/2014
Application #:
11971779
Filing Dt:
01/09/2008
Publication #:
Pub Dt:
07/09/2009
Title:
COMBINED TOUCH SENSOR AND LED DRIVER WITH N-TYPE MOSFET PROTECTING TOUCH SENSOR
75
Patent #:
Issue Dt:
04/20/2010
Application #:
12002614
Filing Dt:
12/17/2007
Publication #:
Pub Dt:
06/18/2009
Title:
HIGH SPEED HYBRID STRUCTURE COUNTER HAVING SYNCHRONOUS TIMING AND ASYNCHRONOUS COUNTER CELLS
76
Patent #:
Issue Dt:
09/15/2009
Application #:
12004177
Filing Dt:
12/19/2007
Publication #:
Pub Dt:
06/25/2009
Title:
SYSTEMS AND METHODS FOR CLEAN DQS SIGNAL GENERATION IN SOURCE-SYNCHRONOUS DDR2 INTERFACE DESIGN
77
Patent #:
Issue Dt:
10/06/2009
Application #:
12004271
Filing Dt:
12/19/2007
Publication #:
Pub Dt:
06/25/2009
Title:
PHASE AND FREQUENCY DETECTOR WITH ZERO STATIC PHASE ERROR
78
Patent #:
Issue Dt:
04/06/2010
Application #:
12006368
Filing Dt:
12/31/2007
Publication #:
Pub Dt:
07/02/2009
Title:
DIGITALLY COMPENSATED HIGHLY STABLE HOLDOVER CLOCK GENERATION TECHNIQUES USING ADAPTIVE FILTERING
79
Patent #:
Issue Dt:
01/10/2012
Application #:
12006599
Filing Dt:
01/04/2008
Publication #:
Pub Dt:
07/09/2009
Title:
BUFFERED DRAM
80
Patent #:
Issue Dt:
07/12/2011
Application #:
12013438
Filing Dt:
01/12/2008
Publication #:
Pub Dt:
06/11/2009
Title:
CONTROL VOLTAGE GENERATOR FOR A CLOCK, FREQUENCY REFERENCE, AND OTHER REFERENCE SIGNAL GENERATOR
81
Patent #:
Issue Dt:
01/10/2012
Application #:
12013440
Filing Dt:
01/12/2008
Publication #:
Pub Dt:
06/11/2009
Title:
CLOCK, FREQUENCY REFERENCE, AND OTHER REFERENCE SIGNAL GENERATOR WITH A CONTROLLED QUALITY FACTOR
82
Patent #:
Issue Dt:
08/09/2011
Application #:
12030571
Filing Dt:
02/13/2008
Publication #:
Pub Dt:
08/13/2009
Title:
AUTOMATED CLOCK RELATIONSHIP DETECTION
83
Patent #:
Issue Dt:
02/02/2010
Application #:
12036165
Filing Dt:
02/22/2008
Publication #:
Pub Dt:
06/26/2008
Title:
DISCRETE CLOCK GENERATOR AND TIMING/FREQUENCY REFERENCE
84
Patent #:
Issue Dt:
02/02/2010
Application #:
12036185
Filing Dt:
02/22/2008
Publication #:
Pub Dt:
06/19/2008
Title:
INTEGRATED CLOCK GENERATOR AND TIMING/FREQUENCY REFERENCE
85
Patent #:
Issue Dt:
05/04/2010
Application #:
12039536
Filing Dt:
02/28/2008
Publication #:
Pub Dt:
09/03/2009
Title:
MERGED-FILTER MULTIPLEXER
86
Patent #:
Issue Dt:
09/15/2009
Application #:
12042144
Filing Dt:
03/04/2008
Publication #:
Pub Dt:
06/26/2008
Title:
CHIP MOUNTING WITH FLOWABLE LAYER
87
Patent #:
Issue Dt:
01/07/2014
Application #:
12043918
Filing Dt:
03/06/2008
Publication #:
Pub Dt:
09/10/2009
Title:
Method To Support Flexible Data Transport On Serial Protocols
88
Patent #:
Issue Dt:
11/13/2012
Application #:
12043929
Filing Dt:
03/06/2008
Publication #:
Pub Dt:
09/10/2009
Title:
PROTOCOL TRANSLATION IN A SERIAL BUFFER
89
Patent #:
Issue Dt:
11/13/2012
Application #:
12043943
Filing Dt:
03/06/2008
Publication #:
Pub Dt:
09/10/2009
Title:
SERIAL BUFFER TO SUPPORT REQUEST PACKETS WITH OUT OF ORDER RESPONSE PACKETS
90
Patent #:
Issue Dt:
07/03/2012
Application #:
12043944
Filing Dt:
03/06/2008
Publication #:
Pub Dt:
09/10/2009
Title:
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05/10/2011
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01/10/2012
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12077651
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03/19/2008
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Pub Dt:
09/24/2009
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94
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07/06/2010
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11/26/2009
Title:
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Assignor
1
Exec Dt:
03/29/2019
Assignees
1
6024 SILVER CREEK VALLEY ROAD
SAN JOSE, CALIFORNIA 95138
2
130 BAYTECH DRIVE
SAN JOSE, CALIFORNIA 95134
3
130 BAYTECH DRIVE
SAN JOSE, CALIFORNIA 95134
4
130 BAYTECH DRIVE
SAN JOSE, CALIFORNIA 95134
5
130 BAYTECH DRIVE
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
MORRISON & FOERSTER LLP
425 MARKET STREET
SAN FRANCISCO, CA 94105

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