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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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09802437
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Filing Dt:
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03/09/2001
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Title:
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SILYLATION PROCESS FOR FORMING CONTACTS
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Patent #:
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Issue Dt:
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02/04/2003
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09803831
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Filing Dt:
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03/12/2001
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Title:
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METHOD OF FABRICATING ABRUPT SOURCE/DRAIN JUNCTIONS
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Issue Dt:
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11/11/2003
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09803853
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Filing Dt:
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03/12/2001
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Title:
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ATTENUATED PHASE SHIFT MASK FOR USE IN EUV LITHOGRAPHY AND A METHOD OF MAKING SUCH A MASK
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09804535
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Filing Dt:
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03/12/2001
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Title:
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STRUCTURE AND METHOD FOR FORMING THE SAME OF A PRINTED WIRING BOARD HAVING BUILT-IN INSPECTION AIDS
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09805651
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Filing Dt:
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03/13/2001
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Title:
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POST-CMP-CU DEPOSITION AND CMP TO ELIMINATE SURFACE VOIDS
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Issue Dt:
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12/10/2002
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Application #:
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09808381
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Filing Dt:
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03/14/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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INTEGRATED COIL INDUCTORS FOR IC DEVICES
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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09808724
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Filing Dt:
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03/14/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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DEFECT-FREE DIELECTRIC COATINGS AND PREPARATION THEREOF USING POLYMERIC NITROGENOUS POROGENS
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09808726
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Filing Dt:
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03/14/2001
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Publication #:
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Pub Dt:
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09/19/2002
| | | | |
Title:
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NITROGEN-CONTAINING POLYMERS AS POROGENS IN THE PREPARATION OF HIGHLY POROUS, LOW DIELECTRIC CONSTANT MATERIALS
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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09809016
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Filing Dt:
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03/16/2001
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Title:
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EXTERNAL CPU ASSIST WHEN PERFORMING A NETWORK ADDRESS LOOKUP
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09809133
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Filing Dt:
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03/15/2001
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Title:
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FIELD EFFECT TRANSISTOR HAVING DOPED GATE WITH PREVENTION OF CONTAMINATION FROM THE GATE DURING IMPLANTATION
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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09809300
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Filing Dt:
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03/16/2001
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Title:
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PLASMA ETCHING USING COMBINATION OF CHF3 AND CH3F
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09809710
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Filing Dt:
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03/14/2001
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Publication #:
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Pub Dt:
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04/25/2002
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Title:
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METHOD OF CONTROLLING A SHAPE OF AN OXIDE LAYER FORMED ON A SUBSTRATE
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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09809766
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Filing Dt:
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03/15/2001
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Publication #:
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Pub Dt:
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09/19/2002
| | | | |
Title:
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SPATIAL PHASE LOCKING WITH SHAPED ELECTRON BEAM LITHOGRAPHY
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09809888
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Filing Dt:
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03/16/2001
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Title:
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METHOD AND STRUCTURE FOR CREATING HIGH DENSITY BURIED CONTACT FOR USE WITH SOI PROCESSES FOR HIGH PERFORMANCE LOGIC
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09810075
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03/15/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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APPARATUS AND METHOD FOR DETERMINING BUFFERED STEINER TREES FOR COMPLEX CIRCUITS
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09810771
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Filing Dt:
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03/16/2001
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Publication #:
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Pub Dt:
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04/25/2002
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Title:
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FULLY SELF-ALIGNED FET TECHNOLOGY
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09810856
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Filing Dt:
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03/16/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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METHOD FOR FABRICATING AN EPITAXIAL BASE BIPLOAR TRANSISTOR WITH RAISED EXTRINSIC BASE
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09811190
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Filing Dt:
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03/16/2001
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Title:
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SYSTEM AND METHOD FOR CALIBRATING ELECTRON BEAM DEFECT INSPECTION TOOL
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Patent #:
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Issue Dt:
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01/14/2003
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09811706
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Filing Dt:
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03/19/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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METHOD FOR FORMING NOTCH GATE HAVING SELF-ALIGNED RAISED SOURCE/DRAIN STRUCTURE
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09811707
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Filing Dt:
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03/19/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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FABRICATION OF NOTCHED GATES BY PASSIVATING PARTIALLY ETCHED GATE SIDEWALLS AND THEN USING AN ISOTROPIC ETCH
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09811733
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Filing Dt:
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03/19/2001
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Publication #:
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Pub Dt:
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04/25/2002
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Title:
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SIDEWALL SPACER BASED FET ALIGNMENT TECHNOLOGY
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09811979
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Filing Dt:
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03/19/2001
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Publication #:
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Pub Dt:
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09/19/2002
| | | | |
Title:
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INTERNALLY BALLASTED SILICON GERMANIUM TRANSISTOR
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09812006
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Filing Dt:
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03/19/2001
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Publication #:
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Pub Dt:
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09/19/2002
| | | | |
Title:
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EFFECTIVE CHANNEL LENGTH CONTROL USING ION IMPLANT FEED FORWARD
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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09812206
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Filing Dt:
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03/19/2001
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Title:
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METHOD FOR ULTRA THIN RESIST LINEWIDTH REDUCTION USING IMPLANTATION
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09812372
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Filing Dt:
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03/20/2001
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Publication #:
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Pub Dt:
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05/16/2002
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH REDUCED LINE-TO-LINE CAPACITANCE AND CROSS TALK NOISE
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09814231
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Filing Dt:
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03/21/2001
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Title:
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METHOD AND APPARATUS FOR CONTROLLING OPTICAL PARAMETERS IN A STEPPER
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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09814789
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Filing Dt:
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03/22/2001
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Publication #:
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Pub Dt:
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09/26/2002
| | | | |
Title:
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APPARATUS TO REDUCE THERMAL FATIGUE STRESS ON FLIP CHIP SOLDER CONNECTIONS
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Patent #:
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Issue Dt:
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07/04/2006
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Application #:
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09814812
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Filing Dt:
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03/23/2001
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Title:
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ACTION TAG GENERATION WITHIN A NETWORK BASED ON PRIORITY OR DIFFERENTIAL SERVICES INFORMATION
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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09814815
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Filing Dt:
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03/23/2001
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Title:
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SELECTIVE ADMISSION CONTROL IN A NETWORK DEVICE
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Patent #:
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Issue Dt:
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11/08/2005
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Application #:
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09814816
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Filing Dt:
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03/23/2001
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Title:
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ADMISSION CONTROL IN A NETWORK DEVICE
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Patent #:
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Issue Dt:
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05/18/2004
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Application #:
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09815445
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Filing Dt:
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03/22/2001
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Title:
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METHOD AND APPARATUS FOR USING TOOL STATE INFORMATION TO IDENTIFY FAULTY WAFERS
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09815540
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Filing Dt:
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03/22/2001
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Publication #:
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Pub Dt:
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09/26/2002
| | | | |
Title:
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METHOD OF MANUFACTURING HIGH ASPECT RATIO PHOTOLITHOGRAPHIC FEATURES
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09816278
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Filing Dt:
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03/23/2001
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Publication #:
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Pub Dt:
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09/26/2002
| | | | |
Title:
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TRI-LAYER DIELECTRIC FUSE CAP FOR LASER DELETION
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09816977
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Filing Dt:
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03/23/2001
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Title:
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DUAL DAMASCENE COPPER INTERCONNECT TO A DAMASCENE TUNGSTEN WIRING LEVEL
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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09817050
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Filing Dt:
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03/27/2001
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Title:
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SEMICONDUCTOR DEVICES WITH DUAL NATURE CAPPING/ARC LAYERS ON ORGANIC -DOPED SILICA GLASS INTERLAYER DIELECTRICS
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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09817120
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Filing Dt:
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03/27/2001
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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METHOD FOR MANUFACTURING DEVICE SUBSTRATE WITH METAL BACK-GATE AND STRUCTURE FORMED THEREBY
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09817518
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Filing Dt:
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03/26/2001
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Title:
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ACTIVE CONTROL OF PHASE SHIFT MASK ETCHING PROCESS
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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09817580
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Filing Dt:
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03/26/2001
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Title:
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METHOD OF LOCALLY FORMING A SILICON/GERMANIUM CHANNEL LAYER
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09817586
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Filing Dt:
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03/26/2001
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Title:
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METHOD OF CREATING NARROW TRENCH LINES USING HARD MASK
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09817625
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Filing Dt:
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03/26/2001
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Title:
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METHOD OF MAKING VERTICAL FIELD EFFECT TRANSISTOR HAVING CHANNEL LENGTH DETERMINED BY THE THICKNESS OF A LAYER OF DUMMY MATERIAL
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09817820
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Filing Dt:
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03/26/2001
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Publication #:
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Pub Dt:
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09/26/2002
| | | | |
Title:
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SCATTEROMETRY TECHNIQUES TO ASCERTAIN ASYMMETRY PROFILE OF FEATURES AND GENERATE FEEDBACK OR FEEDFORWARD PROCESS CONTROL DATA ASSOCIATED THEREWITH
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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09817858
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Filing Dt:
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03/26/2001
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Title:
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LOW DENSITY, TENSILE STRESS REDUCING MATERIAL FOR STI TRENCH FILL
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09817919
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Filing Dt:
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03/26/2001
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Title:
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MOS TRANSISTOR WITH REDUCED FLOATING BODY EFFECT
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09818458
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Filing Dt:
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03/27/2001
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Publication #:
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Pub Dt:
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01/02/2003
| | | | |
Title:
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HALOGEN FREE TRIAZINES, BISMALEIMIDE/EPOXY POLYMERS, PREPREGS MADE THEREFROM FOR CIRCUIT BOARDS AND RESIN COATED ARTICLES, AND USE
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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09819343
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Filing Dt:
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03/28/2001
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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SELECTIVE PHOTORESIST HARDENING TO FACILITATE LATERAL TRIMMING
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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09819344
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Filing Dt:
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03/28/2001
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Publication #:
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Pub Dt:
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10/31/2002
| | | | |
Title:
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PROCESS FOR REDUCING THE CRITICAL DIMENSIONS OF INTEGRATED CIRCUIT DEVICE FEATURES
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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09819552
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Filing Dt:
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03/28/2001
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Publication #:
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Pub Dt:
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10/03/2002
| | | | |
Title:
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PROCESS FOR IMPROVING THE ETCH STABILITY OF ULTRA-THIN PHOTORESIST
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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09819692
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Filing Dt:
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03/28/2001
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Title:
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PROCESS FOR PREVENTING DEFORMATION OF PATTERNED PHOTORESIST FEATURES
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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09820592
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Filing Dt:
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03/29/2001
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Publication #:
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Pub Dt:
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10/03/2002
| | | | |
Title:
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SYSTEM AND METHOD FOR REDUCING NOISE OF CONGESTED DATALINES IN AN EDRAM
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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09821675
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Filing Dt:
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03/29/2001
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Title:
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METHOD FOR PRIORITIZING PRODUCTION LOTS BASED ON GRADE ESTIMATES AND OUTPUT REQUIREMENTS
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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09822587
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Filing Dt:
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03/30/2001
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Publication #:
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Pub Dt:
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10/03/2002
| | | | |
Title:
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METHOD FOR FABRICATING HETEROJUNCTION BIPOLAR TRANSISTORS
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09824112
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Filing Dt:
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04/02/2001
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Publication #:
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Pub Dt:
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10/03/2002
| | | | |
Title:
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IN-SITU THICKNESS MEASUREMENT FOR USE IN SEMICONDUCTOR PROCESSING
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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09824135
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Filing Dt:
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04/02/2001
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Title:
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METHOD AND APPARATUS FOR DIRECT CONNECTION BETWEEN TWO INTEGRATED CIRCUITS VIA A CONNECTOR
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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09824285
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Filing Dt:
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04/02/2001
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Title:
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METHOD OF INTEGRATING SCATTEROMETRY METROLOGY STRUCTURES DIRECTLY INTO DIE DESIGN
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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09824389
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Filing Dt:
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04/02/2001
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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METHOD AND SYSTEM OF AUTOMATIC DELAY DETECTION AND RECEIVER ADJUSTMENT FOR SYNCHRONOUS BUS INTERFACE
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09824415
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Filing Dt:
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04/02/2001
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Title:
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METHOD OF FORMING SMALLER TRENCH LINE WIDTH USING A SPACER HARD MASK
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09824420
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Filing Dt:
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04/02/2001
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Title:
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METHOD OF FORMING SMALLER CONTACT SIZE USING A SPACER HARD MASK
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Patent #:
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Issue Dt:
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03/19/2002
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Application #:
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09824421
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Filing Dt:
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04/02/2001
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Title:
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Method of making ultra small vias for integrated circuits
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09824566
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Filing Dt:
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04/03/2001
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Publication #:
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Pub Dt:
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10/03/2002
| | | | |
Title:
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HIGH PERFORMANCE DELTA SIGMA ADC USING A FEEDBACK NRZ SIN DAC
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Patent #:
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Issue Dt:
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06/25/2002
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Application #:
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09824932
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Filing Dt:
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04/03/2001
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Title:
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SEMICONDUCTOR-ON-INSULATOR DEVICE WITH NITRIDED BURIED OXIDE AND METHOD OF FABRICATING
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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09824995
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Filing Dt:
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04/02/2001
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Publication #:
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Pub Dt:
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10/03/2002
| | | | |
Title:
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DESCRIPTOR TABLE STORING SEGMENT DESCRIPTORS OF VARYING SIZE
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09825704
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Filing Dt:
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04/04/2001
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Publication #:
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Pub Dt:
|
10/10/2002
| | | | |
Title:
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SOI FET AND METHOD FOR CREATING FET BODY CONNECTIONS WITH HIGH-QUALITY MATCHING CHARACTERISTICS AND NO AREA PENALTY FOR PARTIALLY DEPLETED SOI TECHNOLOGIES
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Patent #:
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Issue Dt:
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12/08/2009
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Application #:
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09825905
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Filing Dt:
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04/04/2001
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Publication #:
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Pub Dt:
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10/10/2002
| | | | |
Title:
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METHOD AND APPARATUS FOR SECURING PORTIONS OF MEMORY
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09826551
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Filing Dt:
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04/04/2001
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Title:
|
METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING AN ASYMMETRICAL DUAL-GATE SILICON-GERMANIUM (SIGE) CHANNEL MOSFET AND A DEVICE THEREBY FORMED
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09826591
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Filing Dt:
|
04/05/2001
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Publication #:
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Pub Dt:
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10/10/2002
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Title:
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FRACTIONAL INTEGRATION AND PROPORTIONAL MULTIPLIER CONTROL TO ACHIEVE DESIRED LOOP DYNAMICS
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Patent #:
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Issue Dt:
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06/22/2004
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Application #:
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09827014
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Filing Dt:
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04/05/2001
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Publication #:
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Pub Dt:
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10/10/2002
| | | | |
Title:
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ECONOMICAL HIGH DENSITY CHIP CARRIER
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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09827160
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Filing Dt:
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04/05/2001
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Publication #:
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Pub Dt:
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10/10/2002
| | | | |
Title:
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SPIN-ON CAP LAYER, AND SEMICONDUCTOR DEVICE CONTAINING SAME
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Patent #:
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Issue Dt:
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06/29/2004
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Application #:
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09829630
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Filing Dt:
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04/10/2001
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Publication #:
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Pub Dt:
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10/10/2002
| | | | |
Title:
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ALTERNATING CURRENT BUILT IN SELF TEST (AC BIST) WITH VARIABLE DATA RECEIVER VOLTAGE REFERENCE FOR PERFORMING HIGH-SPEED AC MEMORY SUBSYSTEM SELF-TEST
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Patent #:
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Issue Dt:
|
02/18/2003
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Application #:
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09832557
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Filing Dt:
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04/11/2001
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Publication #:
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Pub Dt:
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10/17/2002
| | | | |
Title:
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DUAL DAMASCENE HORN ANTENNA
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09832623
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Filing Dt:
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04/11/2001
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Publication #:
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Pub Dt:
|
01/02/2003
| | | | |
Title:
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TIMING-DRIVEN GLOBAL PLACEMENT BASED ON GEOMETRY-AWARE TIMING BUDGETS
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Patent #:
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Issue Dt:
|
01/21/2003
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Application #:
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09832697
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Filing Dt:
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04/11/2001
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Title:
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METHOD AND APPARATUS FOR MONITORING WAFER STRESS
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Patent #:
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Issue Dt:
|
05/13/2003
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Application #:
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09832781
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Filing Dt:
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04/11/2001
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Title:
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METHOD AND APPARATUS FOR FAULT DETECTION USING MULTIPLE TOOL ERROR SIGNALS
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Patent #:
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Issue Dt:
|
06/03/2003
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Application #:
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09833550
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Filing Dt:
|
04/12/2001
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Publication #:
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Pub Dt:
|
10/17/2002
| | | | |
Title:
|
THERMALLY STABLE POLY-SI/HIGH DIELECTRIC CONSTANT MATERIAL INTERFACES
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Patent #:
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Issue Dt:
|
12/17/2002
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Application #:
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09834280
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Filing Dt:
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04/12/2001
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Publication #:
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Pub Dt:
|
10/17/2002
| | | | |
Title:
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HIGH PERFORMANCE DENSE WIRE FOR PRINTED CIRCUIT BOARD
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|
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Patent #:
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|
Issue Dt:
|
10/15/2002
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Application #:
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09834281
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Filing Dt:
|
04/12/2001
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Publication #:
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Pub Dt:
|
10/17/2002
| | | | |
Title:
|
METHOD AND STRUCTURE FOR PRODUCING Z-AXIS INTERCONNECTION ASSEMBLY OF PRINTED WIRING BOARD ELEMENTS
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Patent #:
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Issue Dt:
|
12/10/2002
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Application #:
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09835732
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Filing Dt:
|
04/16/2001
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Publication #:
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Pub Dt:
|
10/17/2002
| | | | |
Title:
|
T-RAM STRUCTURE HAVING DUAL VERTICAL DEVICES AND METHOD FOR FABRICATING THE SAME
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|
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Patent #:
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|
Issue Dt:
|
02/25/2003
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Application #:
|
09837603
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Filing Dt:
|
04/18/2001
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Title:
|
METHOD AND APPARATUS FOR CONTROLLING A POLISHING PROCESS BASED ON SCATTEROMETRY DERIVED FILM THICKNESS VARIATION
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|
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Patent #:
|
|
Issue Dt:
|
05/07/2002
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Application #:
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09837712
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Filing Dt:
|
04/18/2001
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Title:
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METHOD AND APPARATUS FOR SELECTING WAFER ALIGNMENT MARKS BASED ON FILM THICKNESS VARIATION
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|
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Patent #:
|
|
Issue Dt:
|
12/30/2003
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Application #:
|
09837839
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Filing Dt:
|
04/18/2001
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Publication #:
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|
Pub Dt:
|
10/24/2002
| | | | |
Title:
|
SOI CMOS DEVICE WITH BODY TO GATE CONNECTION
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|
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Patent #:
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|
Issue Dt:
|
03/11/2003
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Application #:
|
09838417
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Filing Dt:
|
04/19/2001
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Publication #:
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Pub Dt:
|
10/24/2002
| | | | |
Title:
|
DUAL SIDEWALL SPACER FOR A SELF-ALIGNED EXTRINSIC BASE IN SIGE HETEROJUNCTION BIPOLAR TRANSISTORS
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|
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Patent #:
|
|
Issue Dt:
|
10/21/2003
|
Application #:
|
09838672
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Filing Dt:
|
04/19/2001
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Title:
|
SEMICONDUCTOR ANALYSIS ARRANGEMENT AND METHOD THEREFOR
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|
|
Patent #:
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|
Issue Dt:
|
06/15/2004
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Application #:
|
09838892
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Filing Dt:
|
04/20/2001
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Publication #:
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Pub Dt:
|
12/05/2002
| | | | |
Title:
|
EPITAXIAL AND POLYCRYSTALLINE GROWTH OF SI1-X-YGEXCY AND SI1-YCY ALLOY LAYERS ON SI BY UHV-CVD
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|
|
Patent #:
|
|
Issue Dt:
|
10/05/2004
|
Application #:
|
09840019
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Filing Dt:
|
04/23/2001
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Title:
|
INTEGRATED CIRCUIT COOLING DEVICE
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|
|
Patent #:
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|
Issue Dt:
|
03/23/2004
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Application #:
|
09840345
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Filing Dt:
|
04/23/2001
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Publication #:
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Pub Dt:
|
10/24/2002
| | | | |
Title:
|
METHOD AND APPARATUS TO MONITOR THE RUN STATE OF A MULTI-PARTITIONED COMPUTER SYSTEM
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|
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Patent #:
|
|
Issue Dt:
|
01/27/2004
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Application #:
|
09841469
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Filing Dt:
|
04/24/2001
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Title:
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MULTIPROCESSOR SYSTEM IMPLEMENTING VIRTUAL MEMORY USING A SHARED MEMORY, AND A PAGE REPLACEMENT METHOD FOR MAINTAINING PAGED MEMORY COHERENCE
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|
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Patent #:
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|
Issue Dt:
|
05/07/2002
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Application #:
|
09843111
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Filing Dt:
|
04/25/2001
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Title:
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METHOD OF USING SCATTEROMETRY MEASUREMENTS TO CONTROL DEPOSITION PROCESSES
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|
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Patent #:
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|
Issue Dt:
|
12/07/2004
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Application #:
|
09843504
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Filing Dt:
|
04/26/2001
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Publication #:
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Pub Dt:
|
10/31/2002
| | | | |
Title:
|
DESTRUCTIVE READ ARCHITECTURE FOR DYNAMIC RANDOM ACCESS MEMORIES
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|
|
Patent #:
|
|
Issue Dt:
|
01/14/2003
|
Application #:
|
09843782
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Filing Dt:
|
04/27/2001
|
Title:
|
METHOD OF FABRICATION BASED ON SOLID-PHASE EPITAXY FOR A MOSFET TRANSISTOR WITH A CONTROLLED DOPANT PROFILE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2004
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Application #:
|
09843783
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Filing Dt:
|
04/30/2001
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Publication #:
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|
Pub Dt:
|
10/31/2002
| | | | |
Title:
|
METHOD TO INCREASE CARBON AND BORON DOPING CONCENTRATIONS IN SI AND SIGE FILMS
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|
|
Patent #:
|
|
Issue Dt:
|
02/04/2003
|
Application #:
|
09843958
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Filing Dt:
|
04/27/2001
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Title:
|
REMOVAL OF HEAT FROM SOI DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09844183
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Filing Dt:
|
04/27/2001
|
Title:
|
VOLTAGE LEVEL SHIFTER WITH HIGH IMPEDANCE TRI-STATE OUTPUT AND METHOD OF OPERATION
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|
|
Patent #:
|
|
Issue Dt:
|
03/04/2003
|
Application #:
|
09844727
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Filing Dt:
|
04/30/2001
|
Title:
|
DEPOSITING AN ADHESION SKIN LAYER AND A CONFORMAL SEED LAYER TO FILL AN INTERCONNECT OPENING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2003
|
Application #:
|
09844773
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Filing Dt:
|
04/27/2001
|
Title:
|
MOSFET WITH DIFFERENTIAL HALO IMPLANT AND ANNEALING STRATEGY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
09844814
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Filing Dt:
|
04/27/2001
|
Publication #:
|
|
Pub Dt:
|
10/31/2002
| | | | |
Title:
|
PRINTED CIRCUIT BOARD WITH MIXED METALLURGY PADS OXIDE LAYER AND SOLDER MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09844848
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Filing Dt:
|
04/27/2001
|
Publication #:
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|
Pub Dt:
|
12/05/2002
| | | | |
Title:
|
RESIST COMPOSITIONS WITH POLYMERS HAVING PENDANT GROUPS CONTAINING PLURAL ACID LABILE MOIETIES
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|
|
Patent #:
|
|
Issue Dt:
|
03/18/2003
|
Application #:
|
09845266
|
Filing Dt:
|
04/30/2001
|
Title:
|
DEVICE AND METHOD FOR TESTING PERFORMANCE OF SILICON STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
09845454
|
Filing Dt:
|
04/30/2001
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Title:
|
SYSTEM AND METHOD FOR ACTIVE CONTROL OF ETCH PROCESS
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|
|
Patent #:
|
|
Issue Dt:
|
06/22/2004
|
Application #:
|
09845654
|
Filing Dt:
|
04/30/2001
|
Title:
|
METHOD OF ENHANCING GATE PATTERNING PROPERTIES WITH REFLECTIVE HARD MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09845859
|
Filing Dt:
|
04/30/2001
|
Title:
|
METHOD FOR PRODUCING METAL-SEMICONDUCTOR COMPOUND REGIONS ON SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2003
|
Application #:
|
09846186
|
Filing Dt:
|
05/02/2001
|
Title:
|
METHOD OF FORMING CAPPED COPPER INTERCONNECTS WITH REDUCED HILLOCK FORMATION AND IMPROVED ELECTROMIGRATION RESISTANCE
|
|