|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
12129765
|
Filing Dt:
|
05/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/03/2009
| | | | |
|
Title:
|
Method of Forming an Integrated Circuit with NAND Flash Array Segments and Intra Array Multiplexers and Corresponding Integrated Circuit with NAND Flash Array Segments and Intra Array Multiplexers
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
12131728
|
Filing Dt:
|
06/02/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/03/2009
| | | | |
|
Title:
|
SEMICONDUCTOR COMPONENT WITH MIM CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
12131794
|
Filing Dt:
|
06/02/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/03/2009
| | | | |
|
Title:
|
STORAGE CELL HAVING A T-SHAPED GATE ELECTRODE AND METHOD FOR MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
12131802
|
Filing Dt:
|
06/02/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/03/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT AND METHOD OF OPERATING AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12134380
|
Filing Dt:
|
06/06/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/10/2009
| | | | |
|
Title:
|
INTEGRATED BUFFER DEVICE HAVING A SELECTABLE MODE OF OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
12134485
|
Filing Dt:
|
06/06/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/10/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT THAT STORES FIRST AND SECOND DEFECTIVE MEMORY CELL ADDRESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
12134540
|
Filing Dt:
|
06/06/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/10/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT THAT STORES DEFECTIVE MEMORY CELL ADDRESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
12134740
|
Filing Dt:
|
06/06/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/10/2009
| | | | |
|
Title:
|
WORD LINE TO BIT LINE SPACING METHOD AND APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
12135318
|
Filing Dt:
|
06/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/10/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING A BURIED WIRING LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
|
Application #:
|
12135439
|
Filing Dt:
|
06/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/10/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING AN ARRAY OF DIODES COUPLED TO A LAYER OF RESISTANCE CHANGING MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12137096
|
Filing Dt:
|
06/11/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING A MEMORY ELEMENT PROGRAMMED USING A SEED PULSE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12137388
|
Filing Dt:
|
06/11/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUITS HAVING A CONTACT REGION AND METHODS FOR MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
12142239
|
Filing Dt:
|
06/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
12142910
|
Filing Dt:
|
06/20/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/22/2009
| | | | |
|
Title:
|
INTEGRATED LOGIC CIRCUIT AND METHOD FOR PRODUCING AN INTEGRATED LOGIC CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
12143948
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/19/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH HIGH SPEED LOW CURRENT PHASE CHANGE MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
12144482
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
ISOLATION TRENCHES WITH CONDUCTIVE PLATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
12145146
|
Filing Dt:
|
06/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR SELECTIVELY DISABLING TERMINATION CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
12145608
|
Filing Dt:
|
06/25/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
Resistive Memory Devices with Improved Resistive Changing Elements
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2012
|
Application #:
|
12152471
|
Filing Dt:
|
05/14/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/19/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUITS HAVING A CONTACT STRUCTURE HAVING AN ELONGATE STRUCTURE AND METHODS FOR MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
12164736
|
Filing Dt:
|
06/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT HAVING A MAGNETIC TUNNEL JUNCTION DEVICE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
12164765
|
Filing Dt:
|
06/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
MAGNETORESISTIVE SENSOR WITH TUNNEL BARRIER AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
12165132
|
Filing Dt:
|
06/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUITS, STANDARD CELLS, AND METHODS FOR GENERATING A LAYOUT OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
12166112
|
Filing Dt:
|
07/01/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUITS AND METHODS FOR OPERATING THE SAME USING A PLURALITY OF BUFFER CIRCUITS IN AN ACCESS OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2011
|
Application #:
|
12166755
|
Filing Dt:
|
07/02/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT FOR PROGRAMMING A MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
12167853
|
Filing Dt:
|
07/03/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/26/2009
| | | | |
|
Title:
|
METHOD FOR FABRICATING AN INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH SPATIALLY STABLE MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
12167886
|
Filing Dt:
|
07/03/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/26/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT WITH SPATIALLY STABLE MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2012
|
Application #:
|
12168671
|
Filing Dt:
|
07/07/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
|
Title:
|
MRAM DEVICE STRUCTURE EMPLOYING THERMALLY-ASSISTED WRITE OPERATIONS AND THERMALLY-UNASSISTED SELF-REFERENCING OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
12168747
|
Filing Dt:
|
07/07/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT AND METHOD FOR CHARGE REVERSAL OF A CIRCUIT PART OF THE INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
12170967
|
Filing Dt:
|
07/10/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/14/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING A DIELECTRIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
12173524
|
Filing Dt:
|
07/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING A VERTICAL TRANSISTOR AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
12175236
|
Filing Dt:
|
07/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT, MEMORY MODULE, AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
12175726
|
Filing Dt:
|
07/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
|
Title:
|
METHOD FOR MANUFACTURING A MULTICHIP MODULE ASSEMBLY
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12177435
|
Filing Dt:
|
07/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
MUSHROOM TYPE MEMORY CELL HAVING SELF-ALIGNED BOTTOM ELECTRODE AND DIODE ACCESS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
12177930
|
Filing Dt:
|
07/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT WITH AN ACTIVE AREA LINE HAVING AT LEAST ONE FORM-SUPPORTING ELEMENT AND CORRESPONDING METHOD OF MAKING AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
12178407
|
Filing Dt:
|
07/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
FB DRAM MEMORY WITH STATE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
12178912
|
Filing Dt:
|
07/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUITS HAVING A CONTROLLER TO CONTROL A READ OPERATION AND METHODS FOR OPERATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
12180054
|
Filing Dt:
|
07/25/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/29/2009
| | | | |
|
Title:
|
MEMORY MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
12180814
|
Filing Dt:
|
07/28/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2009
| | | | |
|
Title:
|
METHOD OF OPERATING A MEMORY APPARATUS, MEMORY DEVICE AND MEMORY APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12182419
|
Filing Dt:
|
07/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/04/2010
| | | | |
|
Title:
|
FIELD EFFECT TRANSISTORS WITH CHANNELS ORIENTED TO DIFFERENT CRYSTAL PLANES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2010
|
Application #:
|
12182698
|
Filing Dt:
|
07/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/04/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING AN ARRAY OF MEMORY CELLS AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
12182714
|
Filing Dt:
|
07/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/04/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
12184798
|
Filing Dt:
|
08/01/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/04/2010
| | | | |
|
Title:
|
ALIGNMENT CALCULATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2011
|
Application #:
|
12185472
|
Filing Dt:
|
08/04/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/04/2010
| | | | |
|
Title:
|
BUS TERMINATION SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
12186085
|
Filing Dt:
|
08/05/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/12/2009
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING A SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2011
|
Application #:
|
12186195
|
Filing Dt:
|
08/05/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/19/2009
| | | | |
|
Title:
|
METHOD OF OPERATING A MEMORY APPARATUS, MEMORY DEVICE AND MEMORY APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
12188401
|
Filing Dt:
|
08/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
|
Title:
|
ARRAY OF LOW RESISTIVE VERTICAL DIODES AND METHOD OF PRODUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
12188558
|
Filing Dt:
|
08/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING SELECTABLE ADDRESS AND DATA MULTIPLEXING MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
|
Application #:
|
12188966
|
Filing Dt:
|
08/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
|
Title:
|
INTEGRATED CIRCUIT COMPRISING AN ORGANIC SEMICONDUCTOR, AND METHOD FOR THE PRODUCTION OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2010
|
Application #:
|
12190379
|
Filing Dt:
|
08/12/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
|
Title:
|
METHOD FOR FABRICATING A NANOELEMENT FIELD EFFECT TRANSISTOR WITH SURROUNDED GATE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
12193267
|
Filing Dt:
|
08/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT WITH BIT LINES POSITIONED IN DIFFERENT PLANES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2010
|
Application #:
|
12193698
|
Filing Dt:
|
08/18/2008
|
|
Title:
|
CIRCUIT WITH SELECTABLE DATA PATHS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12193786
|
Filing Dt:
|
08/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR FAST AND LOCAL ANNEAL OF ANTI-FERROMAGNETIC (AF) EXCHANGE-BIASED MAGNETIC STACKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
12194414
|
Filing Dt:
|
08/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
|
Title:
|
HIGH SPEED MEMORY ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12195120
|
Filing Dt:
|
08/20/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12195964
|
Filing Dt:
|
08/21/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING MEMORY CELL HAVING CUP-SHAPED ELECTRODE INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2012
|
Application #:
|
12196215
|
Filing Dt:
|
08/21/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
|
Title:
|
ELECTRONIC DEVICE HAVING A CHIP STACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12198005
|
Filing Dt:
|
08/25/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
|
Title:
|
METHOD FOR PRODUCING A DIELECTRIC INTERLAYER AND STORAGE CAPACITOR WITH SUCH A DIELECTRIC INTERLAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
12198383
|
Filing Dt:
|
08/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/04/2010
| | | | |
|
Title:
|
CONCENTRIC PHASE CHANGE MEMORY ELEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2010
|
Application #:
|
12200041
|
Filing Dt:
|
08/28/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/04/2010
| | | | |
|
Title:
|
MEMORY DEVICE WITH MULTIPLE CAPACITOR TYPES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
12201192
|
Filing Dt:
|
08/29/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/12/2009
| | | | |
|
Title:
|
MEMORY DEVICE HAVING AN EVALUATION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
12201223
|
Filing Dt:
|
08/29/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/04/2010
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR REDUCING CHARGE TRAPPING IN HIGH-K DIELECTRIC MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12201524
|
Filing Dt:
|
08/29/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/26/2009
| | | | |
|
Title:
|
HEAT TRANSFER SYSTEM FOR MEMORY MODULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2014
|
Application #:
|
12201876
|
Filing Dt:
|
08/29/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/04/2010
| | | | |
|
Title:
|
DIGITAL DATA INVERSION FLAG GENERATOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12202485
|
Filing Dt:
|
09/02/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/04/2010
| | | | |
|
Title:
|
MULTI-MODE BUS INVERSION METHOD AND APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
12202581
|
Filing Dt:
|
09/02/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/04/2010
| | | | |
|
Title:
|
Memory scheduler for managing maintenance operations in a resistive memory in response to a trigger condition
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2011
|
Application #:
|
12206378
|
Filing Dt:
|
09/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT WITH MEMORY HAVING A CURRENT LIMITING SWITCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2012
|
Application #:
|
12206439
|
Filing Dt:
|
09/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING DOPED SEMICONDUCTOR LINE HAVING CONDUCTIVE CLADDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12207229
|
Filing Dt:
|
09/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2010
| | | | |
|
Title:
|
PHASE CHANGE MEMORY CELL WITH MOSFET DRIVEN BIPOLAR ACCESS DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
12209019
|
Filing Dt:
|
09/11/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/11/2010
| | | | |
|
Title:
|
HORIZONTAL DUAL IN-LINE MEMORY MODULES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
12212400
|
Filing Dt:
|
09/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/18/2010
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR PACKAGED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
12234312
|
Filing Dt:
|
09/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2010
| | | | |
|
Title:
|
MEMORY DIES FOR FLEXIBLE USE AND METHOD FOR CONFIGURING MEMORY DIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12234398
|
Filing Dt:
|
09/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
12235063
|
Filing Dt:
|
09/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2010
| | | | |
|
Title:
|
METHOD AND SYSTEM INCLUDING PLURAL MEMORY CONTROLLERS AND A MEMORY ACCESS CONTROL BUS FOR ACCESSING A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
12235396
|
Filing Dt:
|
09/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/25/2010
| | | | |
|
Title:
|
MULTI-PORT DRAM ARCHITECTURE FOR ACCESSING DIFFERENT MEMORY PARTITIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2010
|
Application #:
|
12239624
|
Filing Dt:
|
09/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
|
Title:
|
APPARATUS FOR THE DYNAMIC DETECTION, SELECTION AND DESELECTION OF LEAKING DECOUPLING CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2010
|
Application #:
|
12240331
|
Filing Dt:
|
09/29/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
|
Title:
|
MEMORY DEVICE REFRESH METHOD AND APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
12241992
|
Filing Dt:
|
09/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT WITH A RECTIFIER ELEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
12242039
|
Filing Dt:
|
09/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
|
Title:
|
METHOD OF MANUFACTURING INTEGRATED CIRCUITS INCLUDING A FET WITH A GATE SPACER AND A FIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
12242137
|
Filing Dt:
|
09/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING A HETERO-INTERFACE AND SELF ADJUSTED DIFFUSION METHOD FOR MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2011
|
Application #:
|
12247763
|
Filing Dt:
|
10/08/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/08/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
12248505
|
Filing Dt:
|
10/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT WITH SWITCHING UNIT FOR MEMORY CELL COUPLING, AND METHOD FOR PRODUCING AN INTEGRATED CIRCUIT FOR MEMORY CELL COUPLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2011
|
Application #:
|
12248759
|
Filing Dt:
|
10/09/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
|
Title:
|
MEMORY DEVICE AND MEMORY SYSTEM COMPRISING A MEMORY DEVICE AND A MEMORY CONTROL DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12249060
|
Filing Dt:
|
10/10/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
|
Title:
|
INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
12251010
|
Filing Dt:
|
10/14/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT WITH CONTROL CIRCUIT FOR PERFORMING RETENTION TEST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
12251864
|
Filing Dt:
|
10/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT WITH A CONTACT STRUCTURE INCLUDING A PORTION ARRANGED IN A CAVITY OF A SEMICONDUCTOR STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2012
|
Application #:
|
12252236
|
Filing Dt:
|
10/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
|
Title:
|
INTERCONNECT STRUCTURES AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12252244
|
Filing Dt:
|
10/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
|
Title:
|
PACKAGING SYSTEMS AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
12252826
|
Filing Dt:
|
10/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/22/2010
| | | | |
|
Title:
|
4 F2 MEMORY CELL ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
12252853
|
Filing Dt:
|
10/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/22/2010
| | | | |
|
Title:
|
MEMORY CELL ARRAY COMPRISING WIGGLED BIT LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
12255755
|
Filing Dt:
|
10/22/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/22/2010
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR PERFORMING INTERNAL HIDDEN REFRESHES WHILE LATCHING READ/WRITE COMMANDS, ADDRESS AND DATA INFORMATION FOR LATER OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
12262124
|
Filing Dt:
|
10/30/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
|
Title:
|
CONTROL CIRCUIT IN A MEMORY CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
12269612
|
Filing Dt:
|
11/12/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
|
Title:
|
METHOD FOR PRODUCING AN INTEGRATED CIRCUIT AND ARRANGEMENT COMPRISING A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
12271313
|
Filing Dt:
|
11/14/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/20/2010
| | | | |
|
Title:
|
INTEGRATED CIRCUIT WITH STACKED DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
12273348
|
Filing Dt:
|
11/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/20/2010
| | | | |
|
Title:
|
METHOD AND APPARATUS TO REDUCE POWER CONSUMPTION BY TRANSFERRING FUNCTIONALITY FROM MEMORY COMPONENTS TO A MEMORY INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12275372
|
Filing Dt:
|
11/21/2008
|
|
Publication #:
|
|
Pub Dt:
|
05/27/2010
| | | | |
|
Title:
|
DIGITALLY CONTROLLED CML BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2012
|
Application #:
|
12328690
|
Filing Dt:
|
12/04/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
|
Title:
|
DISTRIBUTED COMMAND AND ADDRESS BUS ARCHITECTURE FOR A MEMORY MODULE HAVING PORTIONS OF BUS LINES SEPARATELY DISPOSED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
12339722
|
Filing Dt:
|
12/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT COMPRISING A THYRISTOR AND METHOD OF CONTROLLING A MEMORY CELL COMPRISING A THYRISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
12351023
|
Filing Dt:
|
01/09/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/13/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT, METHOD TO PROGRAM A MEMORY CELL ARRAY OF AN INTEGRATED CIRCUIT, AND MEMORY MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
12354140
|
Filing Dt:
|
01/15/2009
|
|
Publication #:
|
|
Pub Dt:
|
07/23/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT COMPRISING CONDUCTIVE LINES AND CONTACT STRUCTURES AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
12485727
|
Filing Dt:
|
06/16/2009
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
CHIP ARRANGEMENT AND METHOD OF MANUFACTURING A CHIP ARRANGEMENT
|
|
